434 lines
12 KiB
C++
434 lines
12 KiB
C++
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/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Implements a 8250 UART
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*/
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#include <string>
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#include <vector>
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#include "base/inifile.hh"
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#include "base/str.hh" // for to_number
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#include "base/trace.hh"
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#include "dev/simconsole.hh"
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#include "dev/uart.hh"
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#include "dev/platform.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "targetarch/ev5.hh"
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using namespace std;
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Uart::IntrEvent::IntrEvent(Uart *u)
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: Event(&mainEventQueue), uart(u)
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{
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DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
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}
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const char *
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Uart::IntrEvent::description()
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{
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return "uart interrupt delay event";
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}
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void
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Uart::IntrEvent::process()
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{
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if (UART_IER_THRI & uart->IER) {
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DPRINTF(Uart, "UART InterEvent, interrupting\n");
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uart->platform->postConsoleInt();
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uart->status |= TX_INT;
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}
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else
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DPRINTF(Uart, "UART InterEvent, not interrupting\n");
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}
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void
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Uart::IntrEvent::scheduleIntr()
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{
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DPRINTF(Uart, "Scheduling IER interrupt\n");
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if (!scheduled())
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schedule(curTick + 300);
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else
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reschedule(curTick + 300);
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}
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Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
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Addr s, HierParams *hier, Bus *bus, Platform *p)
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: PioDevice(name), addr(a), size(s), cons(c), intrEvent(this), platform(p)
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{
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mmu->add_child(this, Range<Addr>(addr, addr + size));
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if (bus) {
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pioInterface = newPioInterface(name, hier, bus, this,
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&Uart::cacheAccess);
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pioInterface->addAddrRange(addr, addr + size - 1);
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}
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readAddr = 0;
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IER = 0;
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DLAB = 0;
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LCR = 0;
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MCR = 0;
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status = 0;
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// set back pointers
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cons->uart = this;
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platform->uart = this;
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}
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Fault
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Uart::read(MemReqPtr &req, uint8_t *data)
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{
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Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
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DPRINTF(Uart, " read register %#x\n", daddr);
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#ifdef ALPHA_TLASER
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switch (req->size) {
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case sizeof(uint64_t):
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*(uint64_t *)data = 0;
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break;
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case sizeof(uint32_t):
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*(uint32_t *)data = 0;
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break;
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case sizeof(uint16_t):
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*(uint16_t *)data = 0;
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break;
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case sizeof(uint8_t):
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*(uint8_t *)data = 0;
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break;
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}
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switch (daddr) {
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case 0x80: // Status Register
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if (readAddr == 3) {
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readAddr = 0;
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if (status & TX_INT)
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*data = (1 << 4);
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else if (status & RX_INT)
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*data = (1 << 5);
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else
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DPRINTF(Uart, "spurious read\n");
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} else {
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*data = (1 << 2);
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if (status & RX_INT)
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*data |= (1 << 0);
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}
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break;
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case 0xc0: // Data register (RX)
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if (!cons->dataAvailable())
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panic("No data to read");
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cons->in(*data);
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if (!cons->dataAvailable()) {
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platform->clearConsoleInt();
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status &= ~RX_INT;
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}
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DPRINTF(Uart, "read data register \'%c\' %2x\n",
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isprint(*data) ? *data : ' ', *data);
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break;
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}
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#else
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assert(req->size == 1);
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switch (daddr) {
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case 0x0:
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if (!(LCR & 0x80)) { // read byte
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//assert(cons->dataAvailable());
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if (cons->dataAvailable())
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cons->in(*data);
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else {
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*(uint8_t*)data = 0;
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// A limited amount of these are ok.
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DPRINTF(Uart, "empty read of RX register\n");
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}
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if (cons->dataAvailable())
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platform->postConsoleInt();
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else
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{
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status &= ~RX_INT;
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platform->clearConsoleInt();
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}
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} else { // dll divisor latch
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;
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}
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break;
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case 0x1:
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if (!(LCR & 0x80)) { // Intr Enable Register(IER)
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*(uint8_t*)data = IER;
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} else { // DLM divisor latch MSB
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;
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}
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break;
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case 0x2: // Intr Identification Register (IIR)
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if (status)
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*(uint8_t*)data = 1;
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else
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*(uint8_t*)data = 0;
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break;
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case 0x3: // Line Control Register (LCR)
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*(uint8_t*)data = LCR;
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break;
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case 0x4: // Modem Control Register (MCR)
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break;
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case 0x5: // Line Status Register (LSR)
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uint8_t lsr;
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lsr = 0;
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// check if there are any bytes to be read
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if (cons->dataAvailable())
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lsr = UART_LSR_DR;
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lsr |= UART_LSR_TEMT | UART_LSR_THRE;
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*(uint8_t*)data = lsr;
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break;
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case 0x6: // Modem Status Register (MSR)
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*(uint8_t*)data = 0;
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break;
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case 0x7: // Scratch Register (SCR)
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*(uint8_t*)data = 0; // doesn't exist with at 8250.
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break;
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default:
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panic("Tried to access a UART port that doesn't exist\n");
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break;
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}
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#endif
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return No_Fault;
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}
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Fault
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Uart::write(MemReqPtr &req, const uint8_t *data)
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{
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Addr daddr = req->paddr - (addr & PA_IMPL_MASK);
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DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
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#ifdef ALPHA_TLASER
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switch (daddr) {
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case 0x80:
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readAddr = *data;
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switch (*data) {
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case 0x28: // Ack of TX
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if ((status & TX_INT) == 0)
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panic("Ack of transmit, though there was no interrupt");
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status &= ~TX_INT;
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platform->clearConsoleInt();
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break;
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case 0x00:
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case 0x01:
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case 0x03: // going to read RR3
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case 0x12:
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break;
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default:
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DPRINTF(Uart, "writing status register %#x \n",
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*(uint64_t *)data);
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break;
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}
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break;
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case 0xc0: // Data register (TX)
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cons->out(*(uint64_t *)data);
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platform->postConsoleInt();
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status |= TX_INT;
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break;
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}
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#else
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switch (daddr) {
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case 0x0:
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if (!(LCR & 0x80)) { // write byte
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cons->out(*(uint64_t *)data);
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platform->clearConsoleInt();
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status &= ~TX_INT;
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if (UART_IER_THRI & IER)
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intrEvent.scheduleIntr();
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} else { // dll divisor latch
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;
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}
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break;
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case 0x1:
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if (!(LCR & 0x80)) { // Intr Enable Register(IER)
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IER = *(uint8_t*)data;
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if ((UART_IER_THRI & IER) || ((UART_IER_RDI & IER) && cons->dataAvailable()))
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platform->postConsoleInt();
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else
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{
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platform->clearConsoleInt();
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if (intrEvent.scheduled())
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intrEvent.deschedule();
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}
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if (!(UART_IER_THRI & IER))
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status &= ~TX_INT;
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if (!((UART_IER_RDI & IER) && cons->dataAvailable()))
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status &= ~RX_INT;
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} else { // DLM divisor latch MSB
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;
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}
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break;
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case 0x2: // FIFO Control Register (FCR)
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break;
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case 0x3: // Line Control Register (LCR)
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LCR = *(uint8_t*)data;
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break;
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case 0x4: // Modem Control Register (MCR)
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if (*(uint8_t*)data == (UART_MCR_LOOP | 0x0A))
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MCR = 0x9A;
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break;
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case 0x7: // Scratch Register (SCR)
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// We are emulating a 8250 so we don't have a scratch reg
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break;
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default:
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panic("Tried to access a UART port that doesn't exist\n");
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break;
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}
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#endif
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return No_Fault;
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}
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void
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Uart::dataAvailable()
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{
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#ifdef ALPHA_TLASER
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platform->postConsoleInt();
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status |= RX_INT;
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#else
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// if the kernel wants an interrupt when we have data
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if (IER & UART_IER_RDI)
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{
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platform->postConsoleInt();
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status |= RX_INT;
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}
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#endif
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}
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Tick
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Uart::cacheAccess(MemReqPtr &req)
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{
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return curTick + 1000;
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}
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void
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Uart::serialize(ostream &os)
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{
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#ifdef ALPHA_TLASER
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SERIALIZE_SCALAR(readAddr);
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SERIALIZE_SCALAR(status);
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#else
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SERIALIZE_SCALAR(status);
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SERIALIZE_SCALAR(IER);
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SERIALIZE_SCALAR(DLAB);
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SERIALIZE_SCALAR(LCR);
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SERIALIZE_SCALAR(MCR);
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Tick intrwhen;
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if (intrEvent.scheduled())
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intrwhen = intrEvent.when();
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else
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intrwhen = 0;
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SERIALIZE_SCALAR(intrwhen);
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#endif
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}
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void
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Uart::unserialize(Checkpoint *cp, const std::string §ion)
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{
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#ifdef ALPHA_TLASER
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UNSERIALIZE_SCALAR(readAddr);
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UNSERIALIZE_SCALAR(status);
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#else
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UNSERIALIZE_SCALAR(status);
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UNSERIALIZE_SCALAR(IER);
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UNSERIALIZE_SCALAR(DLAB);
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UNSERIALIZE_SCALAR(LCR);
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UNSERIALIZE_SCALAR(MCR);
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Tick intrwhen;
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UNSERIALIZE_SCALAR(intrwhen);
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if (intrwhen != 0)
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intrEvent.schedule(intrwhen);
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#endif
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart)
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SimObjectParam<SimConsole *> console;
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SimObjectParam<MemoryController *> mmu;
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SimObjectParam<Platform *> platform;
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Param<Addr> addr;
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Param<Addr> size;
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SimObjectParam<Bus*> io_bus;
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SimObjectParam<HierParams *> hier;
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END_DECLARE_SIM_OBJECT_PARAMS(Uart)
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BEGIN_INIT_SIM_OBJECT_PARAMS(Uart)
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INIT_PARAM(console, "The console"),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(platform, "Pointer to platfrom"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM_DFLT(size, "Device size", 0x8),
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INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
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INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
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END_INIT_SIM_OBJECT_PARAMS(Uart)
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CREATE_SIM_OBJECT(Uart)
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{
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return new Uart(getInstanceName(), console, mmu, addr, size, hier, io_bus,
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platform);
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}
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REGISTER_SIM_OBJECT("Uart", Uart)
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