2013-04-22 19:20:31 +02:00
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/*
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* Copyright (c) 2010-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Chris Emmons
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*/
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/** @file
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* Implementiation of the ARM HDLcd controller.
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*
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* This implementation aims to have sufficient detail such that underrun
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* conditions are reasonable / behave similar to reality. There are two
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* 'engines' going at once. First, the DMA engine running at LCD clock
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* frequency is responsible for filling the controller's internal buffer.
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* The second engine runs at the pixel clock frequency and reads the pixels
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* out of the internal buffer. The pixel rendering engine uses front / back
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* porch and sync delays between lines and frames.
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*
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* If the pixel rendering engine does not have a pixel to display, it will
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* cause an underrun event. The HDLcd controller, per spec, will stop
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* issuing DMA requests for the rest of the frame and resume normal behavior
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* on the subsequent frame. What pixels are rendered upon an underrun
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* condition is different than the real hardware; while the user will see
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* artifacts (previous frame mixed with current frame), it is not the same
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* behavior as real hardware which repeats the last pixel value for the rest
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* of the current frame. This compromise was made to save on memory and
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* complexity and assumes that it is not important to accurately model the
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* content of an underrun frame.
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*
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* KNOWN ISSUES
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* 1. The default kernel driver used in testing sets the line count to one
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* less than the expected 768. However, it also sets the v_count to 767.
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* The controller specifies that 1 should be added to v_count but does not
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* specify adding 1 to the line count. The driver is probably wrong.
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* However, to sync these two numbers up, this model uses fb_line_count and
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* fb_line_length rather than using v_data or h_data values to determine the
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* width and height of the frame; those values are ignored.
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* 2. The HDLcd is implemented here as an AmbaDmaDevice, but it doesn't have
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* an AMBA ID as far as I know. That is the only bit of the AmbaDmaDevice
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* interface that is irrelevant to it, so a fake AMBA ID is used for now.
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* I didn't think inserting an extra layer of hierachy between AmbaDmaDevice
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* and DmaDevice would be helpful to anyone else, but that may be the right
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* answer.
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* 3. The internal buffer size is either 1 or 2 KB depending on which
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* specification is referenced for the different Versatile Express tiles.
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* This implementation uses the larger 2 KB buffer by default.
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*/
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#ifndef __DEV_ARM_HDLCD_HH__
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#define __DEV_ARM_HDLCD_HH__
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#include <fstream>
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#include "dev/arm/amba_device.hh"
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#include "params/HDLcd.hh"
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#include "sim/serialize.hh"
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class VncInput;
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class Bitmap;
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class HDLcd: public AmbaDmaDevice
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{
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protected:
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/** fake AMBA ID -- unused */
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static const uint64_t AMBA_ID = ULL(0xb105f00d00141000);
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/** ARM HDLcd register offsets */
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enum RegisterOffset {
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Version = 0x0000,
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Int_RawStat = 0x0010,
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Int_Clear = 0x0014,
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Int_Mask = 0x0018,
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Int_Status = 0x001C,
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Fb_Base = 0x0100,
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Fb_Line_Length = 0x0104,
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Fb_Line_Count = 0x0108,
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Fb_Line_Pitch = 0x010C,
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Bus_Options = 0x0110,
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V_Sync = 0x0200,
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V_Back_Porch = 0x0204,
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V_Data = 0x0208,
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V_Front_Porch = 0x020C,
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H_Sync = 0x0210,
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H_Back_Porch = 0x0214,
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H_Data = 0x0218,
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H_Front_Porch = 0x021C,
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Polarities = 0x0220,
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Command = 0x0230,
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Pixel_Format = 0x0240,
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Red_Select = 0x0244,
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Green_Select = 0x0248,
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Blue_Select = 0x024C };
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/** Reset value for Bus_Options register */
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static const size_t BUS_OPTIONS_RESETV = 0x408;
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/** Reset value for Version register */
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static const size_t VERSION_RESETV = 0x1CDC0000;
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/** max number of outstanding DMA requests possible */
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static const size_t MAX_OUTSTANDING_DMA_REQ_CAPACITY = 16;
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/** max number of beats delivered in one dma burst */
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static const size_t MAX_BURST_LEN = 16;
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/** size of internal buffer in bytes */
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static const size_t PIXEL_BUFFER_CAPACITY = 2048;
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/** AXI port width in bytes */
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static const size_t AXI_PORT_WIDTH = 8;
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/**
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* @name RegisterFieldLayouts
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* Bit layout declarations for multi-field registers.
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*/
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/**@{*/
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BitUnion32(VersionReg)
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Bitfield<7,0> version_minor;
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Bitfield<15,8> version_major;
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Bitfield<31,16> product_id;
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EndBitUnion(VersionReg)
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BitUnion32(InterruptReg)
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Bitfield<0> dma_end;
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Bitfield<1> bus_error;
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Bitfield<2> vsync;
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Bitfield<3> underrun;
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EndBitUnion(InterruptReg)
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BitUnion32(FbLineCountReg)
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Bitfield<11,0> fb_line_count;
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Bitfield<31,12> reserved_31_12;
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EndBitUnion(FbLineCountReg)
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BitUnion32(BusOptsReg)
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Bitfield<4,0> burst_len;
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Bitfield<7,5> reserved_7_5;
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Bitfield<11,8> max_outstanding;
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Bitfield<31,12> reserved_31_12;
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EndBitUnion(BusOptsReg)
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BitUnion32(TimingReg)
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Bitfield<11,0> val;
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Bitfield<31,12> reserved_31_12;
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EndBitUnion(TimingReg)
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BitUnion32(PolaritiesReg)
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Bitfield<0> vsync_polarity;
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Bitfield<1> hsync_polarity;
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Bitfield<2> dataen_polarity;
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Bitfield<3> data_polarity;
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Bitfield<4> pxlclk_polarity;
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Bitfield<31,5> reserved_31_5;
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EndBitUnion(PolaritiesReg)
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BitUnion32(CommandReg)
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Bitfield<0> enable;
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Bitfield<31,1> reserved_31_1;
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EndBitUnion(CommandReg)
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BitUnion32(PixelFormatReg)
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Bitfield<2,0> reserved_2_0;
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Bitfield<4,3> bytes_per_pixel;
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Bitfield<30,5> reserved_30_5;
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Bitfield<31> big_endian;
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EndBitUnion(PixelFormatReg)
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BitUnion32(ColorSelectReg)
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Bitfield<4,0> offset;
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Bitfield<7,5> reserved_7_5;
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Bitfield<11,8> size;
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Bitfield<15,12> reserved_15_12;
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Bitfield<23,16> default_color;
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Bitfield<31,24> reserved_31_24;
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EndBitUnion(ColorSelectReg)
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/**@}*/
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/**
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* @name HDLCDRegisters
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* HDLCD register contents.
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*/
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/**@{*/
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VersionReg version; /**< Version register */
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InterruptReg int_rawstat; /**< Interrupt raw status register */
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InterruptReg int_clear; /**< Interrupt clear register */
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InterruptReg int_mask; /**< Interrupt mask register */
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InterruptReg int_status; /**< Interrupt status register */
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uint32_t fb_base; /**< Frame buffer base address register */
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uint32_t fb_line_length; /**< Frame buffer Line length register */
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FbLineCountReg fb_line_count; /**< Frame buffer Line count register */
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uint32_t fb_line_pitch; /**< Frame buffer Line pitch register */
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BusOptsReg bus_options; /**< Bus options register */
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TimingReg v_sync; /**< Vertical sync width register */
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TimingReg v_back_porch; /**< Vertical back porch width register */
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TimingReg v_data; /**< Vertical data width register */
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TimingReg v_front_porch; /**< Vertical front porch width register */
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TimingReg h_sync; /**< Horizontal sync width register */
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TimingReg h_back_porch; /**< Horizontal back porch width register */
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TimingReg h_data; /**< Horizontal data width register */
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TimingReg h_front_porch; /**< Horizontal front porch width reg */
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PolaritiesReg polarities; /**< Polarities register */
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CommandReg command; /**< Command register */
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PixelFormatReg pixel_format; /**< Pixel format register */
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ColorSelectReg red_select; /**< Red color select register */
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ColorSelectReg green_select; /**< Green color select register */
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ColorSelectReg blue_select; /**< Blue color select register */
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/** @} */
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/** Pixel clock period */
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const Tick pixelClock;
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/** VNC server */
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VncInput *vnc;
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/** Helper to write out bitmaps */
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Bitmap *bmp;
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/** Picture of what the current frame buffer looks like */
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std::ostream *pic;
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/**
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* Event wrapper for dmaDone()
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*
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* This event call pushes its this pointer onto the freeDoneEvent vector
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* and calls dmaDone() when triggered. While most of the time the burst
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* length of a transaction will be the max burst length set by the driver,
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* any trailing bytes must be handled with smaller lengths thus requiring
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* the configurable burst length option.
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*/
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class DmaDoneEvent : public Event
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{
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private:
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/** Reference to HDLCD that issued the corresponding DMA transaction */
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HDLcd &obj;
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/** Transaction size */
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size_t transSize;
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public:
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/**
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* Constructor.
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*
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* @param _obj HDLCD that issued the corresponding DMA transaction
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*/
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DmaDoneEvent(HDLcd *_obj)
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: Event(), obj(*_obj), transSize(0) {}
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/**
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* Sets the size of this transaction.
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*
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* @param len size of the transaction in bytes
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*/
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void setTransactionSize(size_t len) {
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transSize = len;
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}
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/**
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* Gets the size of this transaction.
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*
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* @return size of this transaction in bytes
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*/
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size_t getTransactionSize() const {
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return transSize;
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}
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void process() {
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obj.dmaDone(this);
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}
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const std::string name() const {
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return obj.name() + ".DmaDoneEvent";
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}
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};
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/** Start time for frame buffer dma read */
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Tick frameReadStartTime;
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/** Starting address for the current frame */
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Addr dmaStartAddr;
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/** Next address the dma should read from */
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Addr dmaCurAddr;
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/** One byte past the address of the last byte the dma should read
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* from */
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Addr dmaMaxAddr;
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/** Number of pending dma reads */
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size_t dmaPendingNum;
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/** Flag indicating whether current frame has underrun */
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bool frameUnderrun;
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/** HDLcd virtual display buffer */
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uint8_t *virtualDisplayBuffer;
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/** Size of the pixel buffer */
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size_t pixelBufferSize;
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/** Index of the next pixel to render */
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size_t pixelIndex;
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/** Flag indicating whether video parameters need updating */
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bool doUpdateParams;
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/** Flag indicating whether a frame read / display is in progress */
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bool frameUnderway;
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/**
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* Number of bytes in flight from DMA that have not reached the pixel
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* buffer yet
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*/
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uint32_t dmaBytesInFlight;
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/**
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* Gets the number of oustanding DMA transactions allowed on the bus at a
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* time.
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*
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* @return gets the driver-specified number of outstanding DMA transactions
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* from the hdlcd controller that are allowed on the bus at a time
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*/
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inline uint16_t maxOutstandingDma() const {
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return bus_options.max_outstanding;
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}
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/**
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* Gets the number of bytes free in the pixel buffer.
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*
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* @return number of bytes free in the internal pixel buffer
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*/
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inline uint32_t bytesFreeInPixelBuffer() const {
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return PIXEL_BUFFER_CAPACITY - (pixelBufferSize + dmaBytesInFlight);
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}
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/**
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* Gets the number of beats-per-burst for bus transactions.
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*
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* @return number of beats-per-burst per HDLcd DMA transaction
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*/
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inline size_t dmaBurstLength() const {
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assert(bus_options.burst_len <= MAX_BURST_LEN);
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return bus_options.burst_len;
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}
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/**
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* Gets the number of bytes per pixel.
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*
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* @return bytes per pixel
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|
*/
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inline size_t bytesPerPixel() const {
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return pixel_format.bytes_per_pixel + 1;
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|
}
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/**
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* Gets frame buffer width.
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*
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* @return frame buffer width (pixels per line)
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|
*/
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inline size_t width() const {
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return fb_line_length / bytesPerPixel();
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}
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/**
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* Gets frame buffer height.
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*
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* @return frame buffer height (lines per panel)
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|
*/
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|
inline size_t height() const {
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|
|
return fb_line_count.fb_line_count;
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|
|
}
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|
|
/**
|
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|
|
* Gets the total number of pixel clocks per display line.
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|
|
*
|
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|
|
* @return number of pixel clocks per display line including porch delays
|
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|
|
* and horizontal sync time
|
|
|
|
*/
|
|
|
|
inline uint64_t PClksPerLine() const {
|
|
|
|
return h_back_porch.val + 1 +
|
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|
|
h_data.val + 1 +
|
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|
|
h_front_porch.val + 1 +
|
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|
|
h_sync.val + 1;
|
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|
|
}
|
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|
|
/** Send updated parameters to the vnc server */
|
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|
|
void updateVideoParams(bool unserializing);
|
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|
|
/** Generates an interrupt */
|
|
|
|
void generateInterrupt();
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|
|
/** Start reading the next frame */
|
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|
|
void startFrame();
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|
|
/** End of frame reached */
|
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|
|
void endFrame();
|
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|
|
|
|
/** Generate DMA read requests from frame buffer into pixel buffer */
|
|
|
|
void fillPixelBuffer();
|
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|
|
/** DMA done event */
|
|
|
|
void dmaDone(DmaDoneEvent *event);
|
|
|
|
|
|
|
|
/** Called when it is time to render a pixel */
|
|
|
|
void renderPixel();
|
|
|
|
|
|
|
|
/** Start of frame event */
|
|
|
|
EventWrapper<HDLcd, &HDLcd::startFrame> startFrameEvent;
|
|
|
|
|
|
|
|
/** End of frame event */
|
|
|
|
EventWrapper<HDLcd, &HDLcd::endFrame> endFrameEvent;
|
|
|
|
|
|
|
|
/** Pixel render event */
|
|
|
|
EventWrapper<HDLcd, &HDLcd::renderPixel> renderPixelEvent;
|
|
|
|
|
|
|
|
/** Fill fifo */
|
|
|
|
EventWrapper<HDLcd, &HDLcd::fillPixelBuffer> fillPixelBufferEvent;
|
|
|
|
|
|
|
|
/** Wrapper to create an event out of the interrupt */
|
|
|
|
EventWrapper<HDLcd, &HDLcd::generateInterrupt> intEvent;
|
|
|
|
|
|
|
|
/**@{*/
|
|
|
|
/**
|
|
|
|
* All pre-allocated DMA done events
|
|
|
|
*
|
|
|
|
* The HDLCD model preallocates maxOutstandingDma() number of
|
|
|
|
* DmaDoneEvents to avoid having to heap allocate every single
|
|
|
|
* event when it is needed. In order to keep track of which events
|
|
|
|
* are in flight and which are ready to be used, we use two
|
|
|
|
* different vectors. dmaDoneEventAll contains <i>all</i>
|
|
|
|
* DmaDoneEvents that the object may use, while dmaDoneEventFree
|
|
|
|
* contains a list of currently <i>unused</i> events. When an
|
|
|
|
* event needs to be scheduled, the last element of the
|
|
|
|
* dmaDoneEventFree is used and removed from the list. When an
|
|
|
|
* event fires, it is added to the end of the
|
|
|
|
* dmaEventFreeList. dmaDoneEventAll is never used except for in
|
|
|
|
* initialization and serialization.
|
|
|
|
*/
|
|
|
|
std::vector<DmaDoneEvent> dmaDoneEventAll;
|
|
|
|
|
|
|
|
/** Unused DMA done events that are ready to be scheduled */
|
|
|
|
std::vector<DmaDoneEvent *> dmaDoneEventFree;
|
|
|
|
/**@}*/
|
|
|
|
|
2013-10-17 17:20:45 +02:00
|
|
|
bool enableCapture;
|
|
|
|
|
2013-04-22 19:20:31 +02:00
|
|
|
public:
|
|
|
|
typedef HDLcdParams Params;
|
|
|
|
|
|
|
|
const Params *
|
|
|
|
params() const
|
|
|
|
{
|
|
|
|
return dynamic_cast<const Params *>(_params);
|
|
|
|
}
|
|
|
|
HDLcd(const Params *p);
|
|
|
|
~HDLcd();
|
|
|
|
|
|
|
|
virtual Tick read(PacketPtr pkt);
|
|
|
|
virtual Tick write(PacketPtr pkt);
|
|
|
|
|
|
|
|
virtual void serialize(std::ostream &os);
|
|
|
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Determine the address ranges that this device responds to.
|
|
|
|
*
|
|
|
|
* @return a list of non-overlapping address ranges
|
|
|
|
*/
|
|
|
|
AddrRangeList getAddrRanges() const;
|
|
|
|
};
|
|
|
|
|
|
|
|
#endif
|