2014-10-16 11:49:39 +02:00
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# -*- mode:python -*-
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# Copyright (c) 2009-2014 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Matt Horsnell
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# Andreas Sandberg
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from m5.defines import buildEnv
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.params import isNullPointer
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from m5.proxy import *
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class ArmPMU(SimObject):
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type = 'ArmPMU'
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cxx_class = 'ArmISA::PMU'
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cxx_header = 'arch/arm/pmu.hh'
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@classmethod
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def export_methods(cls, code):
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code('''
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void addEventProbe(unsigned int id,
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SimObject *obj, const char *name);
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''')
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# To prevent cycles in the configuration hierarchy, we don't keep
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# a list of supported events as a configuration param. Instead, we
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# keep them in a local list and register them using the
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# addEventProbe interface when other SimObjects register their
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# probe listeners.
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_deferred_event_types = []
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# Override the normal SimObject::regProbeListeners method and
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# register deferred event handlers.
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def regProbeListeners(self):
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for event_id, obj, name in self._deferred_event_types:
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self.getCCObject().addEventProbe(event_id, obj.getCCObject(), name)
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self.getCCObject().regProbeListeners()
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def addEventProbe(self, event_id, obj, *args):
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"""Add a probe-based event to the PMU if obj is not None."""
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if obj is None:
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return
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for name in args:
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self._deferred_event_types.append((event_id, obj, name))
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2014-10-16 11:49:42 +02:00
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def addArchEvents(self,
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cpu=None,
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itb=None, dtb=None,
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icache=None, dcache=None,
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l2cache=None):
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"""Add architected events to the PMU.
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This method can be called multiple times with only a subset of
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the keyword arguments set. This enables event registration in
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configuration scripts to happen closer to the instantiation of
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the instrumented objects (e.g., the memory system) instead of
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a central point.
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CPU events should also be registered once per CPU that is
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sharing the PMU (e.g., when switching between CPU models).
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"""
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bpred = cpu.branchPred if cpu and not isNullPointer(cpu.branchPred) \
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else None
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# 0x01: L1I_CACHE_REFILL
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self.addEventProbe(0x02, itb, "Refills")
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# 0x03: L2D_CACHE_REFILL
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# 0x04: L1D_CACHE
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self.addEventProbe(0x05, dtb, "Refills")
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self.addEventProbe(0x06, cpu, "RetiredLoads")
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self.addEventProbe(0x07, cpu, "RetiredStores")
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self.addEventProbe(0x08, cpu, "RetiredInsts")
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# 0x09: EXC_TAKEN
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# 0x0A: EXC_RETURN
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# 0x0B: CID_WRITE_RETIRED
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self.addEventProbe(0x0C, cpu, "RetiredBranches")
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# 0x0D: BR_IMMED_RETIRED
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# 0x0E: BR_RETURN_RETIRED
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# 0x0F: UNALIGEND_LDST_RETIRED
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self.addEventProbe(0x10, bpred, "Misses")
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self.addEventProbe(0x11, cpu, "Cycles")
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self.addEventProbe(0x12, bpred, "Branches")
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self.addEventProbe(0x13, cpu, "RetiredLoads", "RetiredStores")
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# 0x14: L1I_CACHE
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# 0x15: L1D_CACHE_WB
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# 0x16: L2D_CACHE
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# 0x17: L2D_CACHE_REFILL
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# 0x18: L2D_CACHE_WB
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# 0x19: BUS_ACCESS
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# 0x1A: MEMORY_ERROR
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# 0x1B: INST_SPEC
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# 0x1C: TTBR_WRITE_RETIRED
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# 0x1D: BUS_CYCLES
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# 0x1E: CHAIN
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# 0x1F: L1D_CACHE_ALLOCATE
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# 0x20: L2D_CACHE_ALLOCATE
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2014-10-16 11:49:39 +02:00
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platform = Param.Platform(Parent.any, "Platform this device is part of.")
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eventCounters = Param.Int(31, "Number of supported PMU counters")
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pmuInterrupt = Param.Int(68, "PMU GIC interrupt number")
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