922 lines
27 KiB
Text
922 lines
27 KiB
Text
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/*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id$
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*/
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machine(L1Cache, "MOSI Broadcast Optimized") {
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MessageBuffer addressFromCache, network="To", virtual_network="0", ordered="true";
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MessageBuffer dataFromCache, network="To", virtual_network="1", ordered="false";
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MessageBuffer addressToCache, network="From", virtual_network="0", ordered="true";
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MessageBuffer dataToCache, network="From", virtual_network="1", ordered="false";
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// STATES
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enumeration(State, desc="Cache states", default="L1Cache_State_I") {
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NP, desc="Not Present";
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I, desc="Idle";
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S, desc="Shared";
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O, desc="Owned";
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M, desc="Modified", format="!b";
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IS_AD, "IS^AD", desc="idle, issued GETS, have not seen GETS or data yet";
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IM_AD, "IM^AD", desc="idle, issued GETX, have not seen GETX or data yet";
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SM_AD, "SM^AD",desc="shared, issued GETX, have not seen GETX or data yet";
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OM_A, "OM^A",desc="owned, issued GETX, have not seen GETX yet", format="!b";
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IS_A, "IS^A",desc="idle, issued GETS, have not seen GETS, have seen data";
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IM_A, "IM^A",desc="idle, issued GETX, have not seen GETX, have seen data";
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SM_A, "SM^A",desc="shared, issued GETX, have not seen GETX, have seen data", format="!b";
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MI_A, "MI^A", desc="modified, issued PUTX, have not seen PUTX yet";
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OI_A, "OI^A", desc="owned, issued PUTX, have not seen PUTX yet";
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II_A, "II^A", desc="modified, issued PUTX, have not seen PUTX, then saw other GETX", format="!b";
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IS_D, "IS^D", desc="idle, issued GETS, have seen GETS, have not seen data yet";
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IS_D_I, "IS^D^I", desc="idle, issued GETS, have seen GETS, have not seen data, then saw other GETX";
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IM_D, "IM^D", desc="idle, issued GETX, have seen GETX, have not seen data yet";
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IM_D_O, "IM^D^O", desc="idle, issued GETX, have seen GETX, have not seen data yet, then saw other GETS";
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IM_D_I, "IM^D^I", desc="idle, issued GETX, have seen GETX, have not seen data yet, then saw other GETX";
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IM_D_OI, "IM^D^OI", desc="idle, issued GETX, have seen GETX, have not seen data yet, then saw other GETS, then saw other GETX";
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SM_D, "SM^D", desc="shared, issued GETX, have seen GETX, have not seen data yet";
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SM_D_O, "SM^D^O", desc="shared, issued GETX, have seen GETX, have not seen data yet, then saw other GETS";
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}
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// ** EVENTS **
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enumeration(Event, desc="Cache events") {
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// From processor
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Load, desc="Load request from the processor";
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Ifetch, desc="I-fetch request from the processor";
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Store, desc="Store request from the processor";
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Replacement, desc="Replacement";
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Load_prefetch, desc="Read only prefetch";
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Store_prefetch, desc="Read write prefetch", format="!r";
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// From Address network
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Own_GETS, desc="Occurs when we observe our own GETS request in the global order";
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Own_GET_INSTR, desc="Occurs when we observe our own GETInstr request in the global order";
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Own_GETX, desc="Occurs when we observe our own GETX request in the global order";
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Own_PUTX, desc="Occurs when we observe our own PUTX request in the global order", format="!r";
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Other_GETS, desc="Occurs when we observe a GETS request from another processor";
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Other_GET_INSTR, desc="Occurs when we observe a GETInstr request from another processor";
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Other_GETX, desc="Occurs when we observe a GETX request from another processor";
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Other_PUTX, desc="Occurs when we observe a PUTX request from another processor", format="!r";
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// From Data network
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Data, desc="Data for this block from the data network";
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}
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// TYPES
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// CacheEntry
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structure(Entry, desc="...", interface="AbstractCacheEntry") {
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State CacheState, desc="cache state";
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DataBlock DataBlk, desc="data for the block";
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}
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// TBE fields
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structure(TBE, desc="...") {
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Address Address, desc="Physical address for this TBE";
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="Buffer for the data block";
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NetDest ForwardIDs, desc="IDs of the processors to forward the block";
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Address ForwardAddress, desc="Address of request for forwarding";
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bool isPrefetch, desc="Set if this request is a prefetch";
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}
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external_type(CacheMemory) {
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bool cacheAvail(Address);
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Address cacheProbe(Address);
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void allocate(Address);
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void deallocate(Address);
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Entry lookup(Address);
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void changePermission(Address, AccessPermission);
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bool isTagPresent(Address);
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}
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external_type(TBETable) {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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}
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MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
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MessageBuffer optionalQueue, ordered="true", abstract_chip_ptr="true";
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Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
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StoreBuffer storeBuffer, abstract_chip_ptr="true", constructor_hack="i";
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TBETable TBEs, template_hack="<L1Cache_TBE>";
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CacheMemory cacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_unified"', abstract_chip_ptr="true";
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int cache_state_to_int(State state);
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State getState(Address addr) {
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if(TBEs.isPresent(addr)) {
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return TBEs[addr].TBEState;
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} else if (cacheMemory.isTagPresent(addr)) {
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return cacheMemory[addr].CacheState;
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}
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return State:NP;
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}
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void setState(Address addr, State state) {
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if (TBEs.isPresent(addr)) {
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TBEs[addr].TBEState := state;
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}
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if (cacheMemory.isTagPresent(addr)) {
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cacheMemory[addr].CacheState := state;
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// Set permission
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if ((state == State:I) || (state == State:MI_A) || (state == State:II_A)) {
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cacheMemory.changePermission(addr, AccessPermission:Invalid);
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} else if (state == State:S || state == State:O) {
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cacheMemory.changePermission(addr, AccessPermission:Read_Only);
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} else if (state == State:M) {
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cacheMemory.changePermission(addr, AccessPermission:Read_Write);
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} else {
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cacheMemory.changePermission(addr, AccessPermission:Busy);
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}
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}
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}
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// ** OUT_PORTS **
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out_port(dataNetwork_out, DataMsg, dataFromCache);
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out_port(addressNetwork_out, AddressMsg, addressFromCache);
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// ** IN_PORTS **
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// Data Network
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in_port(dataNetwork_in, DataMsg, dataToCache) {
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if (dataNetwork_in.isReady()) {
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peek(dataNetwork_in, DataMsg) {
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trigger(Event:Data, in_msg.Address);
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}
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}
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}
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// Address Network
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in_port(addressNetwork_in, AddressMsg, addressToCache) {
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if (addressNetwork_in.isReady()) {
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peek(addressNetwork_in, AddressMsg) {
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if (in_msg.Type == CoherenceRequestType:GETS) {
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if (in_msg.Requestor == machineID) {
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trigger(Event:Own_GETS, in_msg.Address);
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} else {
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trigger(Event:Other_GETS, in_msg.Address);
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}
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} else if (in_msg.Type == CoherenceRequestType:GETX) {
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if (in_msg.Requestor == machineID) {
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trigger(Event:Own_GETX, in_msg.Address);
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} else {
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trigger(Event:Other_GETX, in_msg.Address);
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}
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} else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
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if (in_msg.Requestor == machineID) {
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trigger(Event:Own_GET_INSTR, in_msg.Address);
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} else {
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trigger(Event:Other_GET_INSTR, in_msg.Address);
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}
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} else if (in_msg.Type == CoherenceRequestType:PUTX) {
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if (in_msg.Requestor == machineID) {
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trigger(Event:Own_PUTX, in_msg.Address);
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} else {
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trigger(Event:Other_PUTX, in_msg.Address);
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}
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} else {
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error("Unexpected message");
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}
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}
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}
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}
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// Mandatory Queue
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in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
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if (mandatoryQueue_in.isReady()) {
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peek(mandatoryQueue_in, CacheMsg) {
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if (cacheMemory.cacheAvail(in_msg.Address) == false) {
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trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.Address));
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} else {
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if (in_msg.Type == CacheRequestType:LD) {
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trigger(Event:Load, in_msg.Address);
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} else if (in_msg.Type == CacheRequestType:IFETCH) {
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trigger(Event:Ifetch, in_msg.Address);
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} else if ((in_msg.Type == CacheRequestType:ST) || (in_msg.Type == CacheRequestType:ATOMIC)) {
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trigger(Event:Store, in_msg.Address);
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} else {
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error("Invalid CacheRequestType");
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}
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}
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}
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}
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}
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// Optional Queue
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in_port(optionalQueue_in, CacheMsg, optionalQueue, desc="...") {
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if (optionalQueue_in.isReady()) {
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peek(optionalQueue_in, CacheMsg) {
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if (cacheMemory.cacheAvail(in_msg.Address) == false) {
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trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.Address));
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} else {
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if ((in_msg.Type == CacheRequestType:LD) || (in_msg.Type == CacheRequestType:IFETCH)) {
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trigger(Event:Load_prefetch, in_msg.Address);
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} else if ((in_msg.Type == CacheRequestType:ST) || (in_msg.Type == CacheRequestType:ATOMIC)) {
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trigger(Event:Store_prefetch, in_msg.Address);
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} else {
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error("Invalid CacheRequestType");
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}
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}
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}
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}
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}
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// ACTIONS
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action(a_allocateTBE, "a", desc="Allocate TBE with Address=B, ForwardID=null, RetryCount=zero, ForwardIDRetryCount=zero, ForwardProgressBit=unset.") {
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check_allocate(TBEs);
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TBEs.allocate(address);
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TBEs[address].isPrefetch := false;
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TBEs[address].ForwardIDs.clear();
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// Keep the TBE state consistent with the cache state
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if (cacheMemory.isTagPresent(address)) {
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TBEs[address].TBEState := cacheMemory[address].CacheState;
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}
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}
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action(b_setPrefetchBit, "b", desc="Set prefetch bit in TBE.") {
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TBEs[address].isPrefetch := true;
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}
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action(c_allocateCacheBlock, "c", desc="Set cache tag equal to tag of block B.") {
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if (cacheMemory.isTagPresent(address) == false) {
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cacheMemory.allocate(address);
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}
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}
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action(d_deallocateTBE, "d", desc="Deallocate TBE.") {
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TBEs.deallocate(address);
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}
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action(e_recordForwardingInfo, "e", desc="Record ID of other processor in ForwardID.") {
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peek(addressNetwork_in, AddressMsg){
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TBEs[address].ForwardIDs.add(in_msg.Requestor);
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TBEs[address].ForwardAddress := in_msg.Address;
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}
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}
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action(f_issueGETS, "f", desc="Issue GETS.") {
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enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:GETS;
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out_msg.CacheState := cache_state_to_int(getState(address));
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out_msg.Requestor := machineID;
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out_msg.Destination.broadcast(MachineType:L1Cache);
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out_msg.Destination.add(map_Address_to_Directory(address)); // To memory
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out_msg.MessageSize := MessageSizeType:Control;
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}
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}
|
||
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action(g_issueGETX, "g", desc="Issue GETX.") {
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enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:GETX;
|
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out_msg.CacheState := cache_state_to_int(getState(address));
|
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out_msg.Requestor := machineID;
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out_msg.Destination.broadcast(MachineType:L1Cache);
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out_msg.Destination.add(map_Address_to_Directory(address)); // To memory
|
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out_msg.MessageSize := MessageSizeType:Control;
|
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}
|
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}
|
||
|
|
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action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") {
|
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DEBUG_EXPR(cacheMemory[address].DataBlk);
|
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if((TBEs.isPresent(address) == false) || (TBEs[address].isPrefetch == false)) {
|
||
|
// Non-prefetch
|
||
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sequencer.readCallback(address, cacheMemory[address].DataBlk);
|
||
|
} else {
|
||
|
// Prefetch - don't call back
|
||
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}
|
||
|
}
|
||
|
|
||
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action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that store completed.") {
|
||
|
DEBUG_EXPR(cacheMemory[address].DataBlk);
|
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if((TBEs.isPresent(address) == false) || (TBEs[address].isPrefetch == false)) {
|
||
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// Non-prefetch
|
||
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sequencer.writeCallback(address, cacheMemory[address].DataBlk);
|
||
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} else {
|
||
|
// Prefetch - don't call back
|
||
|
}
|
||
|
}
|
||
|
|
||
|
action(i_popAddressQueue, "i", desc="Pop incoming address queue.") {
|
||
|
addressNetwork_in.dequeue();
|
||
|
}
|
||
|
|
||
|
action(j_popDataQueue, "j", desc="Pop incoming data queue.") {
|
||
|
dataNetwork_in.dequeue();
|
||
|
}
|
||
|
|
||
|
action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
|
||
|
mandatoryQueue_in.dequeue();
|
||
|
}
|
||
|
|
||
|
action(l_popOptionalQueue, "l", desc="Pop optional queue.") {
|
||
|
optionalQueue_in.dequeue();
|
||
|
}
|
||
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|
||
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|
||
|
action(o_cacheToForward, "o", desc="Send data from the cache to the processor indicated by ForwardIDs.") {
|
||
|
peek(dataNetwork_in, DataMsg){
|
||
|
// This has a CACHE_RESPONSE_LATENCY latency because we want to avoid the
|
||
|
// timing strangeness that can occur if requests that source the
|
||
|
// data from the TBE are faster than data sourced from the cache
|
||
|
enqueue(dataNetwork_out, DataMsg, latency="CACHE_RESPONSE_LATENCY"){
|
||
|
out_msg.Address := TBEs[address].ForwardAddress;
|
||
|
out_msg.Sender := machineID;
|
||
|
out_msg.DataBlk := cacheMemory[address].DataBlk;
|
||
|
out_msg.Destination := TBEs[address].ForwardIDs;
|
||
|
out_msg.DestMachine := MachineType:L1Cache;
|
||
|
out_msg.MessageSize := MessageSizeType:Data;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
action(p_issuePUTX, "p", desc="Issue PUTX.") {
|
||
|
enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
|
||
|
out_msg.Address := address;
|
||
|
out_msg.Type := CoherenceRequestType:PUTX;
|
||
|
out_msg.CacheState := cache_state_to_int(getState(address));
|
||
|
out_msg.Requestor := machineID;
|
||
|
out_msg.Destination.add(map_Address_to_Directory(address)); // To memory
|
||
|
out_msg.Destination.add(machineID); // Back to us
|
||
|
out_msg.DataBlk := cacheMemory[address].DataBlk;
|
||
|
out_msg.MessageSize := MessageSizeType:Data;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
action(q_writeDataFromCacheToTBE, "q", desc="Write data from the cache into the TBE.") {
|
||
|
TBEs[address].DataBlk := cacheMemory[address].DataBlk;
|
||
|
DEBUG_EXPR(TBEs[address].DataBlk);
|
||
|
}
|
||
|
|
||
|
action(r_cacheToRequestor, "r", desc="Send data from the cache to the requestor") {
|
||
|
peek(addressNetwork_in, AddressMsg) {
|
||
|
enqueue(dataNetwork_out, DataMsg, latency="CACHE_RESPONSE_LATENCY") {
|
||
|
out_msg.Address := address;
|
||
|
out_msg.Sender := machineID;
|
||
|
out_msg.Destination.add(in_msg.Requestor);
|
||
|
out_msg.DestMachine := MachineType:L1Cache;
|
||
|
out_msg.DataBlk := cacheMemory[address].DataBlk;
|
||
|
out_msg.MessageSize := MessageSizeType:Data;
|
||
|
}
|
||
|
DEBUG_EXPR(cacheMemory[address].DataBlk);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
|
||
|
action(s_saveDataInTBE, "s", desc="Save data in data field of TBE.") {
|
||
|
peek(dataNetwork_in, DataMsg) {
|
||
|
TBEs[address].DataBlk := in_msg.DataBlk;
|
||
|
DEBUG_EXPR(TBEs[address].DataBlk);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
action(t_issueGET_INSTR, "t", desc="Issue GETInstr.") {
|
||
|
enqueue(addressNetwork_out, AddressMsg, latency="ISSUE_LATENCY") {
|
||
|
out_msg.Address := address;
|
||
|
out_msg.Type := CoherenceRequestType:GET_INSTR;
|
||
|
out_msg.CacheState := cache_state_to_int(getState(address));
|
||
|
out_msg.Requestor := machineID;
|
||
|
out_msg.Destination.broadcast(MachineType:L1Cache);
|
||
|
out_msg.Destination.add(map_Address_to_Directory(address)); // To memory
|
||
|
out_msg.MessageSize := MessageSizeType:Control;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
action(w_writeDataFromTBEToCache, "w", desc="Write data from the TBE into the cache.") {
|
||
|
cacheMemory[address].DataBlk := TBEs[address].DataBlk;
|
||
|
DEBUG_EXPR(cacheMemory[address].DataBlk);
|
||
|
}
|
||
|
|
||
|
action(y_tbeToReq, "y", desc="Send data from the TBE to the requestor.") {
|
||
|
peek(addressNetwork_in, AddressMsg) {
|
||
|
enqueue(dataNetwork_out, DataMsg, latency="CACHE_RESPONSE_LATENCY") { // Either this or the PutX should have a real latency
|
||
|
out_msg.Address := address;
|
||
|
out_msg.Sender := machineID;
|
||
|
out_msg.Destination.add(in_msg.Requestor);
|
||
|
out_msg.DestMachine := MachineType:L1Cache;
|
||
|
out_msg.DataBlk := TBEs[address].DataBlk;
|
||
|
out_msg.MessageSize := MessageSizeType:Data;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
action(ff_deallocateCacheBlock, "\f", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
|
||
|
cacheMemory.deallocate(address);
|
||
|
}
|
||
|
|
||
|
action(z_stall, "z", desc="Cannot be handled right now.") {
|
||
|
// Special name recognized as do nothing case
|
||
|
}
|
||
|
|
||
|
// TRANSITIONS
|
||
|
|
||
|
// Transitions from Idle
|
||
|
transition({NP, I}, Load, IS_AD) {
|
||
|
f_issueGETS;
|
||
|
c_allocateCacheBlock;
|
||
|
a_allocateTBE;
|
||
|
k_popMandatoryQueue;
|
||
|
}
|
||
|
|
||
|
transition({NP, I}, Ifetch, IS_AD) {
|
||
|
t_issueGET_INSTR;
|
||
|
c_allocateCacheBlock;
|
||
|
a_allocateTBE;
|
||
|
k_popMandatoryQueue;
|
||
|
}
|
||
|
|
||
|
transition({NP, I}, Load_prefetch, IS_AD) {
|
||
|
f_issueGETS;
|
||
|
c_allocateCacheBlock;
|
||
|
a_allocateTBE;
|
||
|
b_setPrefetchBit;
|
||
|
l_popOptionalQueue;
|
||
|
}
|
||
|
|
||
|
transition({NP, I}, Store, IM_AD) {
|
||
|
g_issueGETX;
|
||
|
c_allocateCacheBlock;
|
||
|
a_allocateTBE;
|
||
|
k_popMandatoryQueue;
|
||
|
}
|
||
|
|
||
|
transition({NP, I}, Store_prefetch, IM_AD) {
|
||
|
g_issueGETX;
|
||
|
c_allocateCacheBlock;
|
||
|
a_allocateTBE;
|
||
|
b_setPrefetchBit;
|
||
|
l_popOptionalQueue;
|
||
|
}
|
||
|
|
||
|
transition(I, Replacement) {
|
||
|
ff_deallocateCacheBlock; // the cache line is now in NotPresent
|
||
|
}
|
||
|
|
||
|
transition({NP, I}, { Other_GETS, Other_GET_INSTR, Other_GETX } ) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
// Transitions from Shared
|
||
|
transition(S, {Load,Ifetch}) {
|
||
|
h_load_hit;
|
||
|
k_popMandatoryQueue;
|
||
|
}
|
||
|
|
||
|
transition(S, Load_prefetch) {
|
||
|
l_popOptionalQueue;
|
||
|
}
|
||
|
|
||
|
transition(S, Store, SM_AD) {
|
||
|
g_issueGETX;
|
||
|
a_allocateTBE;
|
||
|
k_popMandatoryQueue;
|
||
|
}
|
||
|
|
||
|
transition(S, Store_prefetch, IM_AD) {
|
||
|
g_issueGETX;
|
||
|
a_allocateTBE;
|
||
|
b_setPrefetchBit; // Must be after allocate TBE
|
||
|
l_popOptionalQueue;
|
||
|
}
|
||
|
|
||
|
transition(S, Replacement, I) {
|
||
|
ff_deallocateCacheBlock; // the cache line is now in NotPresent
|
||
|
}
|
||
|
|
||
|
transition(S, {Other_GETS, Other_GET_INSTR}) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(S, Other_GETX, I) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
// Transitions from Owned
|
||
|
transition(O, {Load,Ifetch}) {
|
||
|
h_load_hit;
|
||
|
k_popMandatoryQueue;
|
||
|
}
|
||
|
|
||
|
transition(O, Store, OM_A){
|
||
|
g_issueGETX;
|
||
|
a_allocateTBE;
|
||
|
k_popMandatoryQueue;
|
||
|
}
|
||
|
|
||
|
transition(O, Load_prefetch) {
|
||
|
l_popOptionalQueue;
|
||
|
}
|
||
|
|
||
|
transition(O, Store_prefetch, OM_A) {
|
||
|
g_issueGETX;
|
||
|
a_allocateTBE;
|
||
|
b_setPrefetchBit;
|
||
|
l_popOptionalQueue;
|
||
|
}
|
||
|
|
||
|
transition(O, Replacement, OI_A) {
|
||
|
p_issuePUTX;
|
||
|
a_allocateTBE;
|
||
|
q_writeDataFromCacheToTBE;// the cache line is now empty
|
||
|
ff_deallocateCacheBlock; // the cache line is now in NotPresent
|
||
|
}
|
||
|
|
||
|
transition(O, {Other_GETS,Other_GET_INSTR}) {
|
||
|
r_cacheToRequestor;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(O, Other_GETX, I) {
|
||
|
r_cacheToRequestor;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
// Transitions from Modified
|
||
|
transition(M, {Load,Ifetch}) {
|
||
|
h_load_hit;
|
||
|
k_popMandatoryQueue;
|
||
|
}
|
||
|
|
||
|
transition(M, Store) {
|
||
|
hh_store_hit;
|
||
|
k_popMandatoryQueue;
|
||
|
}
|
||
|
|
||
|
transition(M, {Load_prefetch,Store_prefetch}) {
|
||
|
l_popOptionalQueue;
|
||
|
}
|
||
|
|
||
|
transition(M, Replacement, MI_A) {
|
||
|
p_issuePUTX;
|
||
|
a_allocateTBE;
|
||
|
q_writeDataFromCacheToTBE;// the cache line is now empty
|
||
|
ff_deallocateCacheBlock; // the cache line is now in NotPresent
|
||
|
}
|
||
|
|
||
|
transition(M, {Other_GETS,Other_GET_INSTR}, O) {
|
||
|
r_cacheToRequestor;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(M, Other_GETX, I) {
|
||
|
r_cacheToRequestor;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
|
||
|
// Transitions for Load/Store/Replacement from transient states
|
||
|
|
||
|
transition({IS_AD, IM_AD, IS_A, IM_A, SM_AD, OM_A, SM_A, IS_D, IS_D_I, IM_D, IM_D_O, IM_D_I, IM_D_OI, SM_D, SM_D_O}, {Load, Ifetch, Store, Replacement}) {
|
||
|
z_stall;
|
||
|
}
|
||
|
|
||
|
transition({IS_AD, IM_AD, IS_A, IM_A, SM_AD, OM_A, SM_A, IS_D, IM_D, IM_D_O, SM_D, SM_D_O}, Load_prefetch) {
|
||
|
l_popOptionalQueue;
|
||
|
}
|
||
|
|
||
|
transition({IS_D_I, IM_D_I, IM_D_OI}, Load_prefetch) {
|
||
|
z_stall;
|
||
|
}
|
||
|
|
||
|
transition({IM_AD, SM_AD, OM_A, IM_A, SM_A, IM_D, SM_D}, Store_prefetch) {
|
||
|
l_popOptionalQueue;
|
||
|
}
|
||
|
|
||
|
transition({IS_AD, IS_A, IS_D, IS_D_I, IM_D_O, IM_D_I, IM_D_OI, SM_D_O}, Store_prefetch) {
|
||
|
z_stall;
|
||
|
}
|
||
|
|
||
|
transition({MI_A, OI_A, II_A}, {Load, Ifetch, Store, Load_prefetch, Store_prefetch, Replacement}) {
|
||
|
z_stall;
|
||
|
}
|
||
|
|
||
|
// Always ignore PUTXs which we are not the owner of
|
||
|
transition({NP, I, S, O, M, IS_AD, IM_AD, SM_AD, OM_A, IS_A, IM_A, SM_A, MI_A, OI_A, II_A, IS_D, IS_D_I, IM_D, IM_D_O, IM_D_I, IM_D_OI, SM_D, SM_D_O }, Other_PUTX) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
// transitions from IS_AD
|
||
|
|
||
|
transition(IS_AD, {Own_GETS,Own_GET_INSTR}, IS_D) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(IS_AD, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(IS_AD, Data, IS_A) {
|
||
|
s_saveDataInTBE;
|
||
|
j_popDataQueue;
|
||
|
}
|
||
|
|
||
|
|
||
|
// Transitions from IM_AD
|
||
|
|
||
|
transition(IM_AD, Own_GETX, IM_D) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(IM_AD, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(IM_AD, Data, IM_A) {
|
||
|
s_saveDataInTBE;
|
||
|
j_popDataQueue;
|
||
|
}
|
||
|
|
||
|
// Transitions from OM_A
|
||
|
|
||
|
transition(OM_A, Own_GETX, M){
|
||
|
hh_store_hit;
|
||
|
d_deallocateTBE;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(OM_A, {Other_GETS, Other_GET_INSTR}){
|
||
|
r_cacheToRequestor;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(OM_A, Other_GETX, IM_AD){
|
||
|
r_cacheToRequestor;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(OM_A, Data, IM_A) { // if we get data, we know we're going to lose block before we see own GETX
|
||
|
s_saveDataInTBE;
|
||
|
j_popDataQueue;
|
||
|
}
|
||
|
|
||
|
// Transitions from SM_AD
|
||
|
|
||
|
transition(SM_AD, Own_GETX, SM_D) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(SM_AD, {Other_GETS,Other_GET_INSTR}) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(SM_AD, Other_GETX, IM_AD) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(SM_AD, Data, SM_A) {
|
||
|
s_saveDataInTBE;
|
||
|
j_popDataQueue;
|
||
|
}
|
||
|
|
||
|
|
||
|
// Transitions from IS_A
|
||
|
|
||
|
transition(IS_A, {Own_GETS,Own_GET_INSTR}, S) {
|
||
|
w_writeDataFromTBEToCache;
|
||
|
h_load_hit;
|
||
|
d_deallocateTBE;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(IS_A, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
// Transitions from IM_A
|
||
|
|
||
|
transition(IM_A, Own_GETX, M) {
|
||
|
w_writeDataFromTBEToCache;
|
||
|
hh_store_hit;
|
||
|
d_deallocateTBE;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(IM_A, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
// Transitions from SM_A
|
||
|
|
||
|
transition(SM_A, Own_GETX, M) {
|
||
|
w_writeDataFromTBEToCache;
|
||
|
hh_store_hit;
|
||
|
d_deallocateTBE;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(SM_A, {Other_GETS,Other_GET_INSTR}) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(SM_A, Other_GETX, IM_A) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
|
||
|
// Transitions from MI_A
|
||
|
|
||
|
transition(MI_A, Own_PUTX, I) {
|
||
|
d_deallocateTBE;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(MI_A, {Other_GETS, Other_GET_INSTR}) {
|
||
|
y_tbeToReq;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(MI_A, Other_GETX, II_A) {
|
||
|
y_tbeToReq;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
// Transitions from OI_A
|
||
|
|
||
|
transition(OI_A, Own_PUTX, I) {
|
||
|
d_deallocateTBE;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(OI_A, {Other_GETS, Other_GET_INSTR}) {
|
||
|
y_tbeToReq;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(OI_A, Other_GETX, II_A) {
|
||
|
y_tbeToReq;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
|
||
|
// Transitions from II_A
|
||
|
|
||
|
transition(II_A, Own_PUTX, I) {
|
||
|
d_deallocateTBE;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(II_A, {Other_GETS, Other_GET_INSTR, Other_GETX}) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
// Transitions from IS_D, IS_D_I
|
||
|
|
||
|
transition({IS_D, IS_D_I}, {Other_GETS,Other_GET_INSTR}) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(IS_D, Other_GETX, IS_D_I) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(IS_D_I, Other_GETX) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
transition(IS_D, Data, S) {
|
||
|
s_saveDataInTBE;
|
||
|
w_writeDataFromTBEToCache;
|
||
|
h_load_hit;
|
||
|
d_deallocateTBE;
|
||
|
j_popDataQueue;
|
||
|
}
|
||
|
|
||
|
transition(IS_D_I, Data, I) {
|
||
|
s_saveDataInTBE;
|
||
|
w_writeDataFromTBEToCache;
|
||
|
h_load_hit;
|
||
|
d_deallocateTBE;
|
||
|
j_popDataQueue;
|
||
|
}
|
||
|
|
||
|
// Transitions from IM_D, IM_D_O, IM_D_I, IM_D_OI
|
||
|
|
||
|
transition( IM_D, {Other_GETS,Other_GET_INSTR}, IM_D_O ) {
|
||
|
e_recordForwardingInfo;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition( IM_D, Other_GETX, IM_D_I ) {
|
||
|
e_recordForwardingInfo;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(IM_D_O, {Other_GETS,Other_GET_INSTR} ) {
|
||
|
e_recordForwardingInfo;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(IM_D_O, Other_GETX, IM_D_OI) {
|
||
|
e_recordForwardingInfo;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition( {IM_D_I, IM_D_OI}, {Other_GETS, Other_GET_INSTR, Other_GETX} ) {
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(IM_D, Data, M) {
|
||
|
s_saveDataInTBE;
|
||
|
w_writeDataFromTBEToCache;
|
||
|
hh_store_hit;
|
||
|
d_deallocateTBE;
|
||
|
j_popDataQueue;
|
||
|
}
|
||
|
|
||
|
transition(IM_D_O, Data, O) {
|
||
|
s_saveDataInTBE;
|
||
|
w_writeDataFromTBEToCache;
|
||
|
hh_store_hit;
|
||
|
o_cacheToForward;
|
||
|
d_deallocateTBE;
|
||
|
j_popDataQueue;
|
||
|
}
|
||
|
|
||
|
transition(IM_D_I, Data, I) {
|
||
|
s_saveDataInTBE;
|
||
|
w_writeDataFromTBEToCache;
|
||
|
hh_store_hit;
|
||
|
o_cacheToForward;
|
||
|
d_deallocateTBE;
|
||
|
j_popDataQueue;
|
||
|
}
|
||
|
|
||
|
transition(IM_D_OI, Data, I) {
|
||
|
s_saveDataInTBE;
|
||
|
w_writeDataFromTBEToCache;
|
||
|
hh_store_hit;
|
||
|
o_cacheToForward;
|
||
|
d_deallocateTBE;
|
||
|
j_popDataQueue;
|
||
|
}
|
||
|
|
||
|
// Transitions for SM_D, SM_D_O
|
||
|
|
||
|
transition(SM_D, {Other_GETS,Other_GET_INSTR}, SM_D_O) {
|
||
|
e_recordForwardingInfo;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(SM_D, Other_GETX, IM_D_I) {
|
||
|
e_recordForwardingInfo;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(SM_D_O, {Other_GETS,Other_GET_INSTR}) {
|
||
|
e_recordForwardingInfo;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(SM_D_O, Other_GETX, IM_D_OI) {
|
||
|
e_recordForwardingInfo;
|
||
|
i_popAddressQueue;
|
||
|
}
|
||
|
|
||
|
transition(SM_D, Data, M) {
|
||
|
s_saveDataInTBE;
|
||
|
w_writeDataFromTBEToCache;
|
||
|
hh_store_hit;
|
||
|
d_deallocateTBE;
|
||
|
j_popDataQueue;
|
||
|
}
|
||
|
|
||
|
transition(SM_D_O, Data, O) {
|
||
|
s_saveDataInTBE;
|
||
|
w_writeDataFromTBEToCache;
|
||
|
hh_store_hit;
|
||
|
o_cacheToForward;
|
||
|
d_deallocateTBE;
|
||
|
j_popDataQueue;
|
||
|
}
|
||
|
|
||
|
}
|