gem5/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats

================ Begin RubySystem Configuration Print ================

RubySystem config:
  random_seed: 580633
  randomization: 0
  tech_nm: 45
  freq_mhz: 3000
  block_size_bytes: 64
  block_size_bits: 6
  memory_size_bytes: 1073741824
  memory_size_bits: 30
DMA_Controller config: DMAController_0
  version: 0
  buffer_size: 32
  dma_sequencer: DMASequencer_0
  number_of_TBEs: 128
  transitions_per_cycle: 32
Directory_Controller config: DirectoryController_0
  version: 0
  buffer_size: 32
  directory_latency: 6
  directory_name: DirectoryMemory_0
  memory_controller_name: MemoryControl_0
  memory_latency: 158
  number_of_TBEs: 128
  recycle_latency: 10
  to_mem_ctrl_latency: 1
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_0
  version: 0
  buffer_size: 32
  cache: l1u_0
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 128
  sequencer: Sequencer_0
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_1
  version: 1
  buffer_size: 32
  cache: l1u_1
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 128
  sequencer: Sequencer_1
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_2
  version: 2
  buffer_size: 32
  cache: l1u_2
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 128
  sequencer: Sequencer_2
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_3
  version: 3
  buffer_size: 32
  cache: l1u_3
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 128
  sequencer: Sequencer_3
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_4
  version: 4
  buffer_size: 32
  cache: l1u_4
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 128
  sequencer: Sequencer_4
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_5
  version: 5
  buffer_size: 32
  cache: l1u_5
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 128
  sequencer: Sequencer_5
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_6
  version: 6
  buffer_size: 32
  cache: l1u_6
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 128
  sequencer: Sequencer_6
  transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_7
  version: 7
  buffer_size: 32
  cache: l1u_7
  cache_response_latency: 12
  issue_latency: 2
  number_of_TBEs: 128
  sequencer: Sequencer_7
  transitions_per_cycle: 32
Cache config: l1u_0
  controller: L1CacheController_0
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_1
  controller: L1CacheController_1
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_2
  controller: L1CacheController_2
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_3
  controller: L1CacheController_3
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_4
  controller: L1CacheController_4
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_5
  controller: L1CacheController_5
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_6
  controller: L1CacheController_6
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
Cache config: l1u_7
  controller: L1CacheController_7
  cache_associativity: 8
  num_cache_sets_bits: 2
  num_cache_sets: 4
  cache_set_size_bytes: 256
  cache_set_size_Kbytes: 0.25
  cache_set_size_Mbytes: 0.000244141
  cache_size_bytes: 2048
  cache_size_Kbytes: 2
  cache_size_Mbytes: 0.00195312
DirectoryMemory Global Config: 
  number of directory memories: 1
  total memory size bytes: 1073741824
  total memory size bits: 30
DirectoryMemory module config: DirectoryMemory_0
  controller: DirectoryController_0
  version: 0
  memory_bits: 30
  memory_size_bytes: 1073741824
  memory_size_Kbytes: 1.04858e+06
  memory_size_Mbytes: 1024
  memory_size_Gbytes: 1
Seqeuncer config: Sequencer_0
  controller: L1CacheController_0
  version: 0
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_1
  controller: L1CacheController_1
  version: 1
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_2
  controller: L1CacheController_2
  version: 2
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_3
  controller: L1CacheController_3
  version: 3
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_4
  controller: L1CacheController_4
  version: 4
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_5
  controller: L1CacheController_5
  version: 5
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_6
  controller: L1CacheController_6
  version: 6
  max_outstanding_requests: 16
  deadlock_threshold: 500000
Seqeuncer config: Sequencer_7
  controller: L1CacheController_7
  version: 7
  max_outstanding_requests: 16
  deadlock_threshold: 500000

Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: theTopology

virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_2: active, ordered
virtual_net_3: inactive
virtual_net_4: active, ordered
virtual_net_5: active, ordered

--- Begin Topology Print ---

Topology print ONLY indicates the _NETWORK_ latency between two machines
It does NOT include the latency within the machines

L1Cache-0 Network Latencies
  L1Cache-0 -> L1Cache-1 net_lat: 7
  L1Cache-0 -> L1Cache-2 net_lat: 7
  L1Cache-0 -> L1Cache-3 net_lat: 7
  L1Cache-0 -> L1Cache-4 net_lat: 7
  L1Cache-0 -> L1Cache-5 net_lat: 7
  L1Cache-0 -> L1Cache-6 net_lat: 7
  L1Cache-0 -> L1Cache-7 net_lat: 7
  L1Cache-0 -> Directory-0 net_lat: 7
  L1Cache-0 -> DMA-0 net_lat: 7

L1Cache-1 Network Latencies
  L1Cache-1 -> L1Cache-0 net_lat: 7
  L1Cache-1 -> L1Cache-2 net_lat: 7
  L1Cache-1 -> L1Cache-3 net_lat: 7
  L1Cache-1 -> L1Cache-4 net_lat: 7
  L1Cache-1 -> L1Cache-5 net_lat: 7
  L1Cache-1 -> L1Cache-6 net_lat: 7
  L1Cache-1 -> L1Cache-7 net_lat: 7
  L1Cache-1 -> Directory-0 net_lat: 7
  L1Cache-1 -> DMA-0 net_lat: 7

L1Cache-2 Network Latencies
  L1Cache-2 -> L1Cache-0 net_lat: 7
  L1Cache-2 -> L1Cache-1 net_lat: 7
  L1Cache-2 -> L1Cache-3 net_lat: 7
  L1Cache-2 -> L1Cache-4 net_lat: 7
  L1Cache-2 -> L1Cache-5 net_lat: 7
  L1Cache-2 -> L1Cache-6 net_lat: 7
  L1Cache-2 -> L1Cache-7 net_lat: 7
  L1Cache-2 -> Directory-0 net_lat: 7
  L1Cache-2 -> DMA-0 net_lat: 7

L1Cache-3 Network Latencies
  L1Cache-3 -> L1Cache-0 net_lat: 7
  L1Cache-3 -> L1Cache-1 net_lat: 7
  L1Cache-3 -> L1Cache-2 net_lat: 7
  L1Cache-3 -> L1Cache-4 net_lat: 7
  L1Cache-3 -> L1Cache-5 net_lat: 7
  L1Cache-3 -> L1Cache-6 net_lat: 7
  L1Cache-3 -> L1Cache-7 net_lat: 7
  L1Cache-3 -> Directory-0 net_lat: 7
  L1Cache-3 -> DMA-0 net_lat: 7

L1Cache-4 Network Latencies
  L1Cache-4 -> L1Cache-0 net_lat: 7
  L1Cache-4 -> L1Cache-1 net_lat: 7
  L1Cache-4 -> L1Cache-2 net_lat: 7
  L1Cache-4 -> L1Cache-3 net_lat: 7
  L1Cache-4 -> L1Cache-5 net_lat: 7
  L1Cache-4 -> L1Cache-6 net_lat: 7
  L1Cache-4 -> L1Cache-7 net_lat: 7
  L1Cache-4 -> Directory-0 net_lat: 7
  L1Cache-4 -> DMA-0 net_lat: 7

L1Cache-5 Network Latencies
  L1Cache-5 -> L1Cache-0 net_lat: 7
  L1Cache-5 -> L1Cache-1 net_lat: 7
  L1Cache-5 -> L1Cache-2 net_lat: 7
  L1Cache-5 -> L1Cache-3 net_lat: 7
  L1Cache-5 -> L1Cache-4 net_lat: 7
  L1Cache-5 -> L1Cache-6 net_lat: 7
  L1Cache-5 -> L1Cache-7 net_lat: 7
  L1Cache-5 -> Directory-0 net_lat: 7
  L1Cache-5 -> DMA-0 net_lat: 7

L1Cache-6 Network Latencies
  L1Cache-6 -> L1Cache-0 net_lat: 7
  L1Cache-6 -> L1Cache-1 net_lat: 7
  L1Cache-6 -> L1Cache-2 net_lat: 7
  L1Cache-6 -> L1Cache-3 net_lat: 7
  L1Cache-6 -> L1Cache-4 net_lat: 7
  L1Cache-6 -> L1Cache-5 net_lat: 7
  L1Cache-6 -> L1Cache-7 net_lat: 7
  L1Cache-6 -> Directory-0 net_lat: 7
  L1Cache-6 -> DMA-0 net_lat: 7

L1Cache-7 Network Latencies
  L1Cache-7 -> L1Cache-0 net_lat: 7
  L1Cache-7 -> L1Cache-1 net_lat: 7
  L1Cache-7 -> L1Cache-2 net_lat: 7
  L1Cache-7 -> L1Cache-3 net_lat: 7
  L1Cache-7 -> L1Cache-4 net_lat: 7
  L1Cache-7 -> L1Cache-5 net_lat: 7
  L1Cache-7 -> L1Cache-6 net_lat: 7
  L1Cache-7 -> Directory-0 net_lat: 7
  L1Cache-7 -> DMA-0 net_lat: 7

Directory-0 Network Latencies
  Directory-0 -> L1Cache-0 net_lat: 7
  Directory-0 -> L1Cache-1 net_lat: 7
  Directory-0 -> L1Cache-2 net_lat: 7
  Directory-0 -> L1Cache-3 net_lat: 7
  Directory-0 -> L1Cache-4 net_lat: 7
  Directory-0 -> L1Cache-5 net_lat: 7
  Directory-0 -> L1Cache-6 net_lat: 7
  Directory-0 -> L1Cache-7 net_lat: 7
  Directory-0 -> DMA-0 net_lat: 7

DMA-0 Network Latencies
  DMA-0 -> L1Cache-0 net_lat: 7
  DMA-0 -> L1Cache-1 net_lat: 7
  DMA-0 -> L1Cache-2 net_lat: 7
  DMA-0 -> L1Cache-3 net_lat: 7
  DMA-0 -> L1Cache-4 net_lat: 7
  DMA-0 -> L1Cache-5 net_lat: 7
  DMA-0 -> L1Cache-6 net_lat: 7
  DMA-0 -> L1Cache-7 net_lat: 7
  DMA-0 -> Directory-0 net_lat: 7

--- End Topology Print ---

Profiler Configuration
----------------------
periodic_stats_period: 1000000

================ End RubySystem Configuration Print ================


Real time: Jul/06/2009 11:20:36

Profiler Stats
--------------
Elapsed_time_in_seconds: 569
Elapsed_time_in_minutes: 9.48333
Elapsed_time_in_hours: 0.158056
Elapsed_time_in_days: 0.00658565

Virtual_time_in_seconds: 568.45
Virtual_time_in_minutes: 9.47417
Virtual_time_in_hours:   0.157903
Virtual_time_in_days:    0.157903

Ruby_current_time: 31772572
Ruby_start_time: 1
Ruby_cycles: 31772571

mbytes_resident: 152.301
mbytes_total: 1465.35
resident_ratio: 0.103937

Total_misses: 0
total_misses: 0 [ 0 0 0 0 0 0 0 0 ]
user_misses: 0 [ 0 0 0 0 0 0 0 0 ]
supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ]

instruction_executed: 8 [ 1 1 1 1 1 1 1 1 ]
ruby_cycles_executed: 254180576 [ 31772572 31772572 31772572 31772572 31772572 31772572 31772572 31772572 ]
cycles_per_instruction: 3.17726e+07 [ 3.17726e+07 3.17726e+07 3.17726e+07 3.17726e+07 3.17726e+07 3.17726e+07 3.17726e+07 3.17726e+07 ]
misses_per_thousand_instructions: 0 [ 0 0 0 0 0 0 0 0 ]

transactions_started: 0 [ 0 0 0 0 0 0 0 0 ]
transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ]
instructions_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]

L1D_cache cache stats: 
  L1D_cache_total_misses: 0
  L1D_cache_total_demand_misses: 0
  L1D_cache_total_prefetches: 0
  L1D_cache_total_sw_prefetches: 0
  L1D_cache_total_hw_prefetches: 0
  L1D_cache_misses_per_transaction: 0
  L1D_cache_misses_per_instruction: 0
  L1D_cache_instructions_per_misses: NaN

  L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

L1I_cache cache stats: 
  L1I_cache_total_misses: 0
  L1I_cache_total_demand_misses: 0
  L1I_cache_total_prefetches: 0
  L1I_cache_total_sw_prefetches: 0
  L1I_cache_total_hw_prefetches: 0
  L1I_cache_misses_per_transaction: 0
  L1I_cache_misses_per_instruction: 0
  L1I_cache_instructions_per_misses: NaN

  L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

L2_cache cache stats: 
  L2_cache_total_misses: 0
  L2_cache_total_demand_misses: 0
  L2_cache_total_prefetches: 0
  L2_cache_total_sw_prefetches: 0
  L2_cache_total_hw_prefetches: 0
  L2_cache_misses_per_transaction: 0
  L2_cache_misses_per_instruction: 0
  L2_cache_instructions_per_misses: NaN

  L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]


Memory control:
  memory_total_requests: 1386652
  memory_reads: 693391
  memory_writes: 693137
  memory_refreshes: 66193
  memory_total_request_delays: 425383597
  memory_delays_per_request: 306.77
  memory_delays_in_input_queue: 87505480
  memory_delays_behind_head_of_bank_queue: 257647415
  memory_delays_stalled_at_head_of_bank_queue: 80230702
  memory_stalls_for_bank_busy: 12120239
  memory_stalls_for_random_busy: 0
  memory_stalls_for_anti_starvation: 24602446
  memory_stalls_for_arbitration: 15581979
  memory_stalls_for_bus: 20484518
  memory_stalls_for_tfaw: 0
  memory_stalls_for_read_write_turnaround: 5997915
  memory_stalls_for_read_read_turnaround: 1443605
  accesses_per_bank: 43227  43770  43588  43651  43802  43745  43711  43760  43603  43212  43434  43102  43434  43422  43256  43302  43196  43303  43310  43252  43452  42855  43145  43038  43112  43034  43388  42984  43208  43144  43317  42895  

Busy Controller Counts:
L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:1  L1Cache-7:0  

Directory-0:0  
DMA-0:0  

Busy Bank Count:0

L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
L2TBE_usage: [binsize: 1 max: 41 count: 1440815 average: 18.4457 | standard deviation: 7.12583 | 1873 4135 6801 9875 13162 16875 21071 25498 30277 35703 41476 47234 53104 58918 64131 68752 72371 74737 75823 75450 74014 71134 67287 62894 58093 52984 47909 43558 39550 35395 30307 23965 16658 10087 5476 2567 1043 416 156 45 8 3 ]
StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 747282 average: 11.806 | standard deviation: 3.40201 | 0 1002 2816 5419 9403 15581 23827 33488 44954 55155 63893 69711 72180 71798 69044 65458 143553 ]
store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 128 max: 22580 count: 747194 average: 3867.5 | standard deviation: 2354.99 | 21535 1972 3656 6661 8836 8395 7586 8534 10272 11799 13885 13644 12134 13137 16118 17390 16320 16141 17180 16917 16977 18248 18899 16678 15870 17672 18251 16191 15742 16573 15646 14127 14576 15467 13603 12280 12802 13515 11634 10747 11479 11014 9459 9506 10097 9085 7694 7799 8370 7046 6434 6737 6821 5704 5328 5656 5336 4327 4234 4669 4050 3400 3449 3599 3052 2651 2644 2669 2175 1979 2103 1959 1494 1455 1602 1251 1058 1077 1030 938 720 788 720 592 502 555 506 395 375 403 344 261 248 239 215 218 216 188 132 135 144 129 88 96 97 81 52 65 67 53 37 50 40 25 32 30 27 32 24 17 17 10 19 18 11 11 8 9 11 7 11 8 6 4 8 6 3 5 8 7 1 2 3 0 0 3 1 1 2 5 1 1 2 2 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_2: [binsize: 128 max: 20316 count: 486115 average: 3867.51 | standard deviation: 2355.78 | 14004 1287 2374 4317 5819 5471 4963 5567 6673 7691 8934 8760 7806 8555 10555 11280 10582 10542 11223 11065 11078 11885 12461 10861 10313 11551 11930 10376 10304 10686 10209 9162 9418 10103 8902 7919 8357 8800 7489 7050 7485 7179 6147 6192 6463 5897 5070 5055 5439 4577 4161 4371 4428 3725 3371 3684 3521 2835 2775 3058 2629 2240 2274 2312 1994 1706 1702 1739 1448 1269 1368 1264 970 952 1052 776 699 693 656 628 483 508 459 376 332 368 327 249 247 263 228 172 165 165 137 150 144 117 80 93 93 87 64 62 58 50 33 37 50 39 27 32 26 13 24 22 18 21 20 11 10 8 15 13 4 7 6 5 9 4 8 5 2 3 3 2 2 4 6 5 1 1 0 0 0 2 1 1 2 4 0 1 1 2 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_3: [binsize: 128 max: 22580 count: 261079 average: 3867.49 | standard deviation: 2353.54 | 7531 685 1282 2344 3017 2924 2623 2967 3599 4108 4951 4884 4328 4582 5563 6110 5738 5599 5957 5852 5899 6363 6438 5817 5557 6121 6321 5815 5438 5887 5437 4965 5158 5364 4701 4361 4445 4715 4145 3697 3994 3835 3312 3314 3634 3188 2624 2744 2931 2469 2273 2366 2393 1979 1957 1972 1815 1492 1459 1611 1421 1160 1175 1287 1058 945 942 930 727 710 735 695 524 503 550 475 359 384 374 310 237 280 261 216 170 187 179 146 128 140 116 89 83 74 78 68 72 71 52 42 51 42 24 34 39 31 19 28 17 14 10 18 14 12 8 8 9 11 4 6 7 2 4 5 7 4 2 4 2 3 3 3 4 1 5 4 1 1 2 2 0 1 3 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

Request vs. RubySystem State Profile
--------------------------------


filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 28 count: 1494483 average: 0.00199668 | standard deviation: 0.174223 | 1494276 0 3 0 1 0 1 0 4 0 22 0 33 0 35 0 62 0 45 0 0 0 0 0 0 0 0 0 1 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 28 count: 1494483 average: 0.00199668 | standard deviation: 0.174223 | 1494276 0 3 0 1 0 1 0 4 0 22 0 33 0 35 0 62 0 45 0 0 0 0 0 0 0 0 0 1 ]
  virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 747194 average:     0 | standard deviation: 0 | 747194 ]
  virtual_network_2_delay_cycles: [binsize: 1 max: 28 count: 747289 average: 0.0039931 | standard deviation: 0.246365 | 747082 0 3 0 1 0 1 0 4 0 22 0 33 0 35 0 62 0 45 0 0 0 0 0 0 0 0 0 1 ]
  virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

Resource Usage
--------------
page_size: 4096
user_time: 568
system_time: 0
page_reclaims: 39706
page_faults: 0
swaps: 0
block_inputs: 8
block_outputs: 152

Network Stats
-------------

switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.018376
  links_utilized_percent_switch_0_link_0: 0.00734962 bw: 640000 base_latency: 1
  links_utilized_percent_switch_0_link_1: 0.0294024 bw: 160000 base_latency: 1

  outgoing_messages_switch_0_link_0_Response_Data: 93403 747224 [ 0 93403 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_0_Writeback_Control: 93410 747280 [ 0 0 93410 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_1_Control: 93415 747320 [ 93415 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_1_Data: 86732 693856 [ 86732 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_1_Response_Data: 6691 53528 [ 0 6691 0 0 0 0 ] base_latency: 1

switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0.0183719
  links_utilized_percent_switch_1_link_0: 0.00734816 bw: 640000 base_latency: 1
  links_utilized_percent_switch_1_link_1: 0.0293956 bw: 160000 base_latency: 1

  outgoing_messages_switch_1_link_0_Response_Data: 93382 747056 [ 0 93382 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_0_Writeback_Control: 93394 747152 [ 0 0 93394 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_1_Control: 93392 747136 [ 93392 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_1_Data: 86505 692040 [ 86505 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_1_Response_Data: 6898 55184 [ 0 6898 0 0 0 0 ] base_latency: 1

switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0.0183854
  links_utilized_percent_switch_2_link_0: 0.00735332 bw: 640000 base_latency: 1
  links_utilized_percent_switch_2_link_1: 0.0294175 bw: 160000 base_latency: 1

  outgoing_messages_switch_2_link_0_Response_Data: 93445 747560 [ 0 93445 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_2_link_0_Writeback_Control: 93462 747696 [ 0 0 93462 0 0 0 ] base_latency: 1
  outgoing_messages_switch_2_link_1_Control: 93459 747672 [ 93459 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_2_link_1_Data: 86854 694832 [ 86854 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_2_link_1_Response_Data: 6621 52968 [ 0 6621 0 0 0 0 ] base_latency: 1

switch_3_inlinks: 2
switch_3_outlinks: 2
links_utilized_percent_switch_3: 0.0183732
  links_utilized_percent_switch_3_link_0: 0.00734887 bw: 640000 base_latency: 1
  links_utilized_percent_switch_3_link_1: 0.0293975 bw: 160000 base_latency: 1

  outgoing_messages_switch_3_link_0_Response_Data: 93391 747128 [ 0 93391 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_0_Writeback_Control: 93403 747224 [ 0 0 93403 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_1_Control: 93397 747176 [ 93397 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_1_Data: 86604 692832 [ 86604 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_1_Response_Data: 6806 54448 [ 0 6806 0 0 0 0 ] base_latency: 1

switch_4_inlinks: 2
switch_4_outlinks: 2
links_utilized_percent_switch_4: 0.0183723
  links_utilized_percent_switch_4_link_0: 0.00734871 bw: 640000 base_latency: 1
  links_utilized_percent_switch_4_link_1: 0.0293958 bw: 160000 base_latency: 1

  outgoing_messages_switch_4_link_0_Response_Data: 93389 747112 [ 0 93389 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_4_link_0_Writeback_Control: 93401 747208 [ 0 0 93401 0 0 0 ] base_latency: 1
  outgoing_messages_switch_4_link_1_Control: 93390 747120 [ 93390 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_4_link_1_Data: 86681 693448 [ 86681 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_4_link_1_Response_Data: 6725 53800 [ 0 6725 0 0 0 0 ] base_latency: 1

switch_5_inlinks: 2
switch_5_outlinks: 2
links_utilized_percent_switch_5: 0.0183691
  links_utilized_percent_switch_5_link_0: 0.00734702 bw: 640000 base_latency: 1
  links_utilized_percent_switch_5_link_1: 0.0293912 bw: 160000 base_latency: 1

  outgoing_messages_switch_5_link_0_Response_Data: 93369 746952 [ 0 93369 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_5_link_0_Writeback_Control: 93378 747024 [ 0 0 93378 0 0 0 ] base_latency: 1
  outgoing_messages_switch_5_link_1_Control: 93378 747024 [ 93378 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_5_link_1_Data: 86787 694296 [ 86787 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_5_link_1_Response_Data: 6602 52816 [ 0 6602 0 0 0 0 ] base_latency: 1

switch_6_inlinks: 2
switch_6_outlinks: 2
links_utilized_percent_switch_6: 0.0183742
  links_utilized_percent_switch_6_link_0: 0.00734918 bw: 640000 base_latency: 1
  links_utilized_percent_switch_6_link_1: 0.0293993 bw: 160000 base_latency: 1

  outgoing_messages_switch_6_link_0_Response_Data: 93393 747144 [ 0 93393 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_6_link_0_Writeback_Control: 93409 747272 [ 0 0 93409 0 0 0 ] base_latency: 1
  outgoing_messages_switch_6_link_1_Control: 93400 747200 [ 93400 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_6_link_1_Data: 86807 694456 [ 86807 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_6_link_1_Response_Data: 6611 52888 [ 0 6611 0 0 0 0 ] base_latency: 1

switch_7_inlinks: 2
switch_7_outlinks: 2
links_utilized_percent_switch_7: 0.0183789
  links_utilized_percent_switch_7_link_0: 0.00735123 bw: 640000 base_latency: 1
  links_utilized_percent_switch_7_link_1: 0.0294067 bw: 160000 base_latency: 1

  outgoing_messages_switch_7_link_0_Response_Data: 93422 747376 [ 0 93422 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_7_link_0_Writeback_Control: 93432 747456 [ 0 0 93432 0 0 0 ] base_latency: 1
  outgoing_messages_switch_7_link_1_Control: 93426 747408 [ 93426 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_7_link_1_Data: 86588 692704 [ 86588 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_7_link_1_Response_Data: 6851 54808 [ 0 6851 0 0 0 0 ] base_latency: 1

switch_8_inlinks: 2
switch_8_outlinks: 2
links_utilized_percent_switch_8: 0.141701
  links_utilized_percent_switch_8_link_0: 0.0566845 bw: 640000 base_latency: 1
  links_utilized_percent_switch_8_link_1: 0.226717 bw: 160000 base_latency: 1

  outgoing_messages_switch_8_link_0_Control: 747255 5978040 [ 747255 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_8_link_0_Data: 693556 5548448 [ 693556 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_8_link_1_Response_Data: 693389 5547112 [ 0 693389 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_8_link_1_Writeback_Control: 747289 5978312 [ 0 0 747289 0 0 0 ] base_latency: 1

switch_9_inlinks: 2
switch_9_outlinks: 2
links_utilized_percent_switch_9: 0
  links_utilized_percent_switch_9_link_0: 0 bw: 640000 base_latency: 1
  links_utilized_percent_switch_9_link_1: 0 bw: 160000 base_latency: 1


switch_10_inlinks: 10
switch_10_outlinks: 10
links_utilized_percent_switch_10: 0.0461923
  links_utilized_percent_switch_10_link_0: 0.0293985 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_1: 0.0293926 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_2: 0.0294133 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_3: 0.0293955 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_4: 0.0293949 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_5: 0.0293881 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_6: 0.0293967 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_7: 0.0294049 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_8: 0.226738 bw: 160000 base_latency: 1
  links_utilized_percent_switch_10_link_9: 0 bw: 160000 base_latency: 1

  outgoing_messages_switch_10_link_0_Response_Data: 93403 747224 [ 0 93403 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_0_Writeback_Control: 93410 747280 [ 0 0 93410 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_1_Response_Data: 93382 747056 [ 0 93382 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_1_Writeback_Control: 93394 747152 [ 0 0 93394 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_2_Response_Data: 93445 747560 [ 0 93445 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_2_Writeback_Control: 93462 747696 [ 0 0 93462 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_3_Response_Data: 93391 747128 [ 0 93391 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_3_Writeback_Control: 93403 747224 [ 0 0 93403 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_4_Response_Data: 93389 747112 [ 0 93389 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_4_Writeback_Control: 93401 747208 [ 0 0 93401 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_5_Response_Data: 93369 746952 [ 0 93369 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_5_Writeback_Control: 93378 747024 [ 0 0 93378 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_6_Response_Data: 93393 747144 [ 0 93393 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_6_Writeback_Control: 93409 747272 [ 0 0 93409 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_7_Response_Data: 93422 747376 [ 0 93422 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_7_Writeback_Control: 93432 747456 [ 0 0 93432 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_8_Control: 747256 5978048 [ 747256 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_10_link_8_Data: 693557 5548456 [ 693557 0 0 0 0 0 ] base_latency: 1

 --- DMA ---
 - Event Counts -
ReadRequest  0
WriteRequest  0
Data  0
Ack  0

 - Transitions -
READY  ReadRequest  0 <-- 
READY  WriteRequest  0 <-- 

BUSY_RD  Data  0 <-- 

BUSY_WR  Ack  0 <-- 

 --- Directory ---
 - Event Counts -
GETX  7346943
GETS  0
PUTX  693205
PUTX_NotOwner  351
DMA_READ  0
DMA_WRITE  0
Memory_Data  693390
Memory_Ack  693133

 - Transitions -
I  GETX  693447
I  PUTX_NotOwner  0 <-- 
I  DMA_READ  0 <-- 
I  DMA_WRITE  0 <-- 

M  GETX  53805
M  PUTX  693205
M  PUTX_NotOwner  351
M  DMA_READ  0 <-- 
M  DMA_WRITE  0 <-- 

M_DRD  GETX  0 <-- 
M_DRD  PUTX  0 <-- 

M_DWR  GETX  0 <-- 
M_DWR  PUTX  0 <-- 

M_DWRI  Memory_Ack  0 <-- 

IM  GETX  3167967
IM  GETS  0 <-- 
IM  PUTX  0 <-- 
IM  PUTX_NotOwner  0 <-- 
IM  DMA_READ  0 <-- 
IM  DMA_WRITE  0 <-- 
IM  Memory_Data  693390

MI  GETX  3431724
MI  GETS  0 <-- 
MI  PUTX  0 <-- 
MI  PUTX_NotOwner  0 <-- 
MI  DMA_READ  0 <-- 
MI  DMA_WRITE  0 <-- 
MI  Memory_Ack  693133

ID  GETX  0 <-- 
ID  GETS  0 <-- 
ID  PUTX  0 <-- 
ID  PUTX_NotOwner  0 <-- 
ID  DMA_READ  0 <-- 
ID  DMA_WRITE  0 <-- 
ID  Memory_Data  0 <-- 

ID_W  GETX  0 <-- 
ID_W  GETS  0 <-- 
ID_W  PUTX  0 <-- 
ID_W  PUTX_NotOwner  0 <-- 
ID_W  DMA_READ  0 <-- 
ID_W  DMA_WRITE  0 <-- 
ID_W  Memory_Ack  0 <-- 

 --- L1Cache ---
 - Event Counts -
Load  486166
Ifetch  0
Store  261091
Data  747194
Fwd_GETX  53805
Inv  0
Replacement  747001
Writeback_Ack  693133
Writeback_Nack  351

 - Transitions -
I  Load  486166
I  Ifetch  0 <-- 
I  Store  261091
I  Inv  0 <-- 
I  Replacement  53443

II  Writeback_Nack  351

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  53454
M  Inv  0 <-- 
M  Replacement  693558

MI  Fwd_GETX  351
MI  Inv  0 <-- 
MI  Writeback_Ack  693133

IS  Data  486115

IM  Data  261079

 --- L1Cache ---
 - Event Counts -
Load  486166
Ifetch  0
Store  261091
Data  747194
Fwd_GETX  53805
Inv  0
Replacement  747001
Writeback_Ack  693133
Writeback_Nack  351

 - Transitions -
I  Load  486166
I  Ifetch  0 <-- 
I  Store  261091
I  Inv  0 <-- 
I  Replacement  53443

II  Writeback_Nack  351

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  53454
M  Inv  0 <-- 
M  Replacement  693558

MI  Fwd_GETX  351
MI  Inv  0 <-- 
MI  Writeback_Ack  693133

IS  Data  486115

IM  Data  261079

 --- L1Cache ---
 - Event Counts -
Load  486166
Ifetch  0
Store  261091
Data  747194
Fwd_GETX  53805
Inv  0
Replacement  747001
Writeback_Ack  693133
Writeback_Nack  351

 - Transitions -
I  Load  486166
I  Ifetch  0 <-- 
I  Store  261091
I  Inv  0 <-- 
I  Replacement  53443

II  Writeback_Nack  351

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  53454
M  Inv  0 <-- 
M  Replacement  693558

MI  Fwd_GETX  351
MI  Inv  0 <-- 
MI  Writeback_Ack  693133

IS  Data  486115

IM  Data  261079

 --- L1Cache ---
 - Event Counts -
Load  486166
Ifetch  0
Store  261091
Data  747194
Fwd_GETX  53805
Inv  0
Replacement  747001
Writeback_Ack  693133
Writeback_Nack  351

 - Transitions -
I  Load  486166
I  Ifetch  0 <-- 
I  Store  261091
I  Inv  0 <-- 
I  Replacement  53443

II  Writeback_Nack  351

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  53454
M  Inv  0 <-- 
M  Replacement  693558

MI  Fwd_GETX  351
MI  Inv  0 <-- 
MI  Writeback_Ack  693133

IS  Data  486115

IM  Data  261079

 --- L1Cache ---
 - Event Counts -
Load  486166
Ifetch  0
Store  261091
Data  747194
Fwd_GETX  53805
Inv  0
Replacement  747001
Writeback_Ack  693133
Writeback_Nack  351

 - Transitions -
I  Load  486166
I  Ifetch  0 <-- 
I  Store  261091
I  Inv  0 <-- 
I  Replacement  53443

II  Writeback_Nack  351

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  53454
M  Inv  0 <-- 
M  Replacement  693558

MI  Fwd_GETX  351
MI  Inv  0 <-- 
MI  Writeback_Ack  693133

IS  Data  486115

IM  Data  261079

 --- L1Cache ---
 - Event Counts -
Load  486166
Ifetch  0
Store  261091
Data  747194
Fwd_GETX  53805
Inv  0
Replacement  747001
Writeback_Ack  693133
Writeback_Nack  351

 - Transitions -
I  Load  486166
I  Ifetch  0 <-- 
I  Store  261091
I  Inv  0 <-- 
I  Replacement  53443

II  Writeback_Nack  351

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  53454
M  Inv  0 <-- 
M  Replacement  693558

MI  Fwd_GETX  351
MI  Inv  0 <-- 
MI  Writeback_Ack  693133

IS  Data  486115

IM  Data  261079

 --- L1Cache ---
 - Event Counts -
Load  486166
Ifetch  0
Store  261091
Data  747194
Fwd_GETX  53805
Inv  0
Replacement  747001
Writeback_Ack  693133
Writeback_Nack  351

 - Transitions -
I  Load  486166
I  Ifetch  0 <-- 
I  Store  261091
I  Inv  0 <-- 
I  Replacement  53443

II  Writeback_Nack  351

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  53454
M  Inv  0 <-- 
M  Replacement  693558

MI  Fwd_GETX  351
MI  Inv  0 <-- 
MI  Writeback_Ack  693133

IS  Data  486115

IM  Data  261079

 --- L1Cache ---
 - Event Counts -
Load  486166
Ifetch  0
Store  261091
Data  747194
Fwd_GETX  53805
Inv  0
Replacement  747001
Writeback_Ack  693133
Writeback_Nack  351

 - Transitions -
I  Load  486166
I  Ifetch  0 <-- 
I  Store  261091
I  Inv  0 <-- 
I  Replacement  53443

II  Writeback_Nack  351

M  Load  0 <-- 
M  Ifetch  0 <-- 
M  Store  0 <-- 
M  Fwd_GETX  53454
M  Inv  0 <-- 
M  Replacement  693558

MI  Fwd_GETX  351
MI  Inv  0 <-- 
MI  Writeback_Ack  693133

IS  Data  486115

IM  Data  261079