164 lines
5.3 KiB
C++
164 lines
5.3 KiB
C++
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/*
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* Copyright (c) 2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Hansson
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*/
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/**
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* @file
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* DRAMSim2Wrapper declaration
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*/
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#ifndef __MEM_DRAMSIM2_WRAPPER_HH__
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#define __MEM_DRAMSIM2_WRAPPER_HH__
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#include <string>
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#include "DRAMSim2/Callback.h"
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/**
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* Forward declaration to avoid includes
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*/
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namespace DRAMSim {
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class MultiChannelMemorySystem;
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}
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/**
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* Wrapper class to avoid having DRAMSim2 names like ClockDomain etc
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* clashing with the normal gem5 world. Many of the DRAMSim2 headers
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* do not make use of namespaces, and quite a few also open up
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* std. The only thing that needs to be exposed externally are the
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* callbacks. This wrapper effectively avoids clashes by not including
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* any of the conventional gem5 headers (e.g. Packet or SimObject).
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*/
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class DRAMSim2Wrapper
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{
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private:
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DRAMSim::MultiChannelMemorySystem* dramsim;
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double _clockPeriod;
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unsigned int _queueSize;
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unsigned int _burstSize;
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template <typename T>
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T extractConfig(const std::string& field_name,
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const std::string& file_name) const;
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public:
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/**
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* Create an instance of the DRAMSim2 multi-channel memory
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* controller using a specific config and system description.
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*
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* @param config_file Memory config file
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* @param system_file Controller config file
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* @param working_dir Path pre-pended to config files
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* @param trace_file Output trace file
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* @param memory_size_mb Total memory size in MByte
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* @param enable_debug Enable debug output
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*/
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DRAMSim2Wrapper(const std::string& config_file,
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const std::string& system_file,
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const std::string& working_dir,
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const std::string& trace_file,
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unsigned int memory_size_mb,
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bool enable_debug);
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~DRAMSim2Wrapper();
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/**
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* Print the stats gathered in DRAMsim2.
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*/
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void printStats();
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/**
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* Set the callbacks to use for read and write completion.
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*
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* @param read_callback Callback used for read completions
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* @param write_callback Callback used for write completions
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*/
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void setCallbacks(DRAMSim::TransactionCompleteCB* read_callback,
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DRAMSim::TransactionCompleteCB* write_callback);
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/**
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* Determine if the controller can accept a new packet or not.
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*
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* @return true if the controller can accept transactions
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*/
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bool canAccept() const;
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/**
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* Enqueue a packet. This assumes that canAccept has returned true.
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*
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* @param pkt Packet to turn into a DRAMSim2 transaction
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*/
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void enqueue(bool is_write, uint64_t addr);
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/**
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* Get the internal clock period used by DRAMSim2, specified in
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* ns.
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*
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* @return The clock period of the DRAM interface in ns
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*/
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double clockPeriod() const;
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/**
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* Get the transaction queue size used by DRAMSim2.
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*
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* @return The queue size counted in number of transactions
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*/
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unsigned int queueSize() const;
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/**
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* Get the burst size in bytes used by DRAMSim2.
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*
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* @return The burst size in bytes (data width * burst length)
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*/
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unsigned int burstSize() const;
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/**
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* Progress the memory controller one cycle
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*/
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void tick();
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};
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#endif //__MEM_DRAMSIM2_WRAPPER_HH__
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