gem5/.hgignore

syntax: glob
build
parser.out
parsetab.py
cscope.files
cscope.out
*.pyc
*~
.*.swp
m5out
src/doxygen
ext/dramsim2/DRAMSim2
ext/mcpat/regression/*/*.out
ignore stuff that we don't want to see in the status --HG-- extra : convert_revision : c4a4711cf515507d4debcacacef5799adcfe3bef 2007-07-14 07:39:41 +02:00			`syntax: glob`
			`build`
			`parser.out`
			`parsetab.py`
Add cscope files to .hgignore. --HG-- extra : convert_revision : 82598579baf50cd258714c7e533b96bc6bd1305a 2007-08-04 01:27:51 +02:00			`cscope.files`
			`cscope.out`
ignore stuff that we don't want to see in the status --HG-- extra : convert_revision : c4a4711cf515507d4debcacacef5799adcfe3bef 2007-07-14 07:39:41 +02:00			`*.pyc`
			`*~`
Add base ARM code to M5 --HG-- extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af 2008-02-06 05:44:13 +01:00			`.*.swp`
m5: Added the default m5out directory to the hg ignore list 2009-11-19 01:34:32 +01:00			`m5out`
.hgignore: added src/doxygen 2010-07-28 05:00:38 +02:00			`src/doxygen`
mem: Add a wrapped DRAMSim2 memory controller This patch adds DRAMSim2 as a memory controller by wrapping the external library and creating a sublass of AbstractMemory that bridges between the semantics of gem5 and the DRAMSim2 interface. The DRAMSim2 wrapper extracts the clock period from the config file. There is no way of extracting this information from DRAMSim2 itself, so we simply read the same config file and get it from there. To properly model the response queue, the wrapper keeps track of how many transactions are in the actual controller, and how many are stacking up waiting to be sent back as responses (in the wrapper). The latter requires us to move away from the queued port and manage the packets ourselves. This is due to DRAMSim2 not having any flow control on the response path. DRAMSim2 assumes that the transactions it is given are matching the burst size of the choosen memory. The wrapper checks to ensure the cache line size of the system matches the burst size of DRAMSim2 as there are currently no provisions to split the system requests. In theory we could allow a cache line size smaller than the burst size, but that would lead to inefficient use of the DRAM, so for not we fatal also in this case. 2014-02-18 11:50:53 +01:00			`ext/dramsim2/DRAMSim2`
ext: Add a McPAT regression tester Add a regression tester to McPAT. Joel Hestness wrote these tests and Yasuko Eckert modified them to reflect the new McPAT interface and other changes the previous patch made. 2014-06-04 16:48:20 +02:00			`ext/mcpat/regression//.out`