243 lines
7.8 KiB
C++
243 lines
7.8 KiB
C++
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/* @file
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* Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers.
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*/
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namespace iGbReg {
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const uint32_t CTRL = 0x00000;
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const uint32_t STATUS = 0x00008;
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const uint32_t EECD = 0x00010;
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const uint32_t CTRL_EXT = 0x00018;
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const uint32_t PBA = 0x01000;
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const uint32_t ICR = 0x000C0;
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const uint32_t ITR = 0x000C4;
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const uint32_t ICS = 0x000C8;
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const uint32_t IMS = 0x000D0;
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const uint32_t IMC = 0x000D8;
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const uint32_t RCTL = 0x00100;
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const uint32_t RDBAL = 0x02800;
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const uint32_t RDBAH = 0x02804;
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const uint32_t RDLEN = 0x02808;
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const uint32_t RDH = 0x02810;
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const uint32_t RDT = 0x02818;
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const uint32_t RDTR = 0x02820;
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const uint32_t RADV = 0x0282C;
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const uint32_t RSRPD = 0x02C00;
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const uint32_t TCTL = 0x00400;
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const uint32_t TDBAL = 0x03800;
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const uint32_t TDBAH = 0x03804;
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const uint32_t TDLEN = 0x03808;
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const uint32_t TDH = 0x03810;
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const uint32_t THT = 0x03818;
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const uint32_t TIDV = 0x03820;
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const uint32_t TXDMAC = 0x03000;
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const uint32_t TXDCTL = 0x03828;
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const uint32_t TADV = 0x0282C;
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const uint32_t TSPMT = 0x03830;
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const uint32_t RXDCTL = 0x02828;
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const uint32_t RXCSUM = 0x05000;
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struct RxDesc {
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Addr buf;
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uint16_t len;
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uint16_t csum;
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union {
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uint8_t status;
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struct { // these may be in the worng order
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uint8_t dd:1; // descriptor done (hw is done when 1)
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uint8_t eop:1; // end of packet
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uint8_t xism:1; // ignore checksum
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uint8_t vp:1; // packet is vlan packet
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uint8_t rsv:1; // reserved
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uint8_t tcpcs:1; // TCP checksum done
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uint8_t ipcs:1; // IP checksum done
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uint8_t pif:1; // passed in-exact filter
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} st;
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};
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union {
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uint8_t errors;
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struct {
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uint8_t ce:1; // crc error or alignment error
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uint8_t se:1; // symbol error
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uint8_t seq:1; // sequence error
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uint8_t rsv:1; // reserved
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uint8_t cxe:1; // carrier extension error
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uint8_t tcpe:1; // tcp checksum error
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uint8_t ipe:1; // ip checksum error
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uint8_t rxe:1; // PX data error
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} er;
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};
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union {
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uint16_t special;
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struct {
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uint16_t vlan:12; //vlan id
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uint16_t cfi:1; // canocial form id
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uint16_t pri:3; // user priority
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} sp;
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};
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};
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union TxDesc {
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uint8_t data[16];
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struct {
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Addr buf;
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uint16_t len;
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uint8_t cso;
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union {
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uint8_t command;
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struct {
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uint8_t eop:1; // end of packet
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uint8_t ifcs:1; // insert crc
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uint8_t ic:1; // insert checksum
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uint8_t rs:1; // report status
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uint8_t rps:1; // report packet sent
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uint8_t dext:1; // extension
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uint8_t vle:1; // vlan enable
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uint8_t ide:1; // interrupt delay enable
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} cmd;
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};
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union {
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uint8_t status:4;
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struct {
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uint8_t dd:1; // descriptor done
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uint8_t ec:1; // excess collisions
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uint8_t lc:1; // late collision
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uint8_t tu:1; // transmit underrun
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} st;
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};
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uint8_t reserved:4;
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uint8_t css;
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union {
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uint16_t special;
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struct {
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uint16_t vlan:12; //vlan id
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uint16_t cfi:1; // canocial form id
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uint16_t pri:3; // user priority
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} sp;
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};
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} legacy;
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// Type 0000 descriptor
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struct {
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uint8_t ipcss;
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uint8_t ipcso;
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uint16_t ipcse;
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uint8_t tucss;
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uint8_t tucso;
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uint16_t tucse;
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uint32_t paylen:20;
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uint8_t dtype:4;
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union {
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uint8_t tucommand;
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struct {
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uint8_t tcp:1; // tcp/udp
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uint8_t ip:1; // ip ipv4/ipv6
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uint8_t tse:1; // tcp segment enbale
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uint8_t rs:1; // report status
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uint8_t rsv0:1; // reserved
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uint8_t dext:1; // descriptor extension
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uint8_t rsv1:1; // reserved
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uint8_t ide:1; // interrupt delay enable
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} tucmd;
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};
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union {
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uint8_t status:4;
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struct {
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uint8_t dd:1;
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uint8_t rsvd:3;
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} sta;
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};
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uint8_t reserved:4;
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uint8_t hdrlen;
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uint16_t mss;
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} t0;
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// Type 0001 descriptor
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struct {
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Addr buf;
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uint32_t dtalen:20;
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uint8_t dtype:4;
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union {
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uint8_t dcommand;
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struct {
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uint8_t eop:1; // end of packet
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uint8_t ifcs:1; // insert crc
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uint8_t tse:1; // segmentation enable
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uint8_t rs:1; // report status
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uint8_t rps:1; // report packet sent
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uint8_t dext:1; // extension
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uint8_t vle:1; // vlan enable
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uint8_t ide:1; // interrupt delay enable
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} dcmd;
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};
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union {
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uint8_t status:4;
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struct {
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uint8_t dd:1; // descriptor done
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uint8_t ec:1; // excess collisions
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uint8_t lc:1; // late collision
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uint8_t tu:1; // transmit underrun
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} sta;
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};
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union {
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uint8_t pktopts;
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struct {
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uint8_t ixsm:1; // insert ip checksum
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uint8_t txsm:1; // insert tcp checksum
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};
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};
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union {
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uint16_t special;
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struct {
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uint16_t vlan:12; //vlan id
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uint16_t cfi:1; // canocial form id
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uint16_t pri:3; // user priority
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} sp;
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};
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} t1;
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// Junk to test descriptor type!
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struct {
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uint64_t junk;
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uint32_t junk1:20;
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uint8_t dtype;
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uint8_t junk2:5;
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uint8_t dext:1;
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uint8_t junk3:2;
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uint8_t junk4:4;
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uint32_t junk5;
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} type;
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};
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}; // iGbReg namespace
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