283 lines
8.7 KiB
Text
283 lines
8.7 KiB
Text
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// -*- mode:c++ -*-
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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////////////////////////////////////////////////////////////////////
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//
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// Utility functions for execute methods
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//
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//
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output header {{
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// Shift types for ARM instructions
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enum ArmShiftType {
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LSL = 0,
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LSR,
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ASR,
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ROR
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};
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enum ArmShiftMode {
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};
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inline uint32_t number_of_ones(int32_t val)
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{
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uint32_t ones = 0;
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for (int i = 0; i < 32; i++ )
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{
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if ( val & (1<<i) )
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ones++;
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}
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return ones;
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}
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}};
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output exec {{
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static int32_t arm_NEG(int32_t val) { return (val >> 31); }
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static int32_t arm_POS(int32_t val) { return ((~val) >> 31); }
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// Shift Rm by an immediate value
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inline int32_t
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shift_rm_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval)
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{
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enum ArmShiftType shiftType;
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shiftType = (enum ArmShiftType) type;
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switch (shiftType)
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{
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case LSL:
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return (base << shamt);
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case LSR:
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if (shamt == 0)
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return (0);
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else
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return (base >> shamt);
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case ASR:
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if (shamt == 0)
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return ((uint32_t) ((int32_t) base >> 31L));
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else
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return ((uint32_t) (((int32_t) base) >> shamt));
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case ROR:
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//shamt = shamt & 0x1f;
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if (shamt == 0)
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return (cfval << 31) | (base >> 1); // RRX
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else
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return (base << (32 - shamt)) | (base >> shamt);
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default:
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fprintf(stderr, "Unhandled shift type\n");
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exit(1);
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break;
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}
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return 0;
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}
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// Shift Rm by Rs
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inline int32_t
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shift_rm_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval)
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{
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enum ArmShiftType shiftType;
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shiftType = (enum ArmShiftType) type;
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switch (shiftType)
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{
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case LSL:
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if (shamt == 0)
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return (base);
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else if (shamt >= 32)
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return (0);
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else
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return (base << shamt);
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case LSR:
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if (shamt == 0)
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return (base);
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else if (shamt >= 32)
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return (0);
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else
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return (base >> shamt);
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case ASR:
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if (shamt == 0)
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return base;
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else if (shamt >= 32)
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return ((uint32_t) ((int32_t) base >> 31L));
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else
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return ((uint32_t) (((int32_t) base) >> (int) shamt));
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case ROR:
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shamt = shamt & 0x1f;
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if (shamt == 0)
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return (base);
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else
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return ((base << (32 - shamt)) | (base >> shamt));
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default:
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fprintf(stderr, "Unhandled shift type\n");
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exit(1);
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break;
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}
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return 0;
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}
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// Generate C for a shift by immediate
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inline int32_t
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shift_carry_imm(uint32_t base, uint32_t shamt, uint32_t type,
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uint32_t cfval)
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{
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enum ArmShiftType shiftType;
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shiftType = (enum ArmShiftType) type;
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switch (shiftType)
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{
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case LSL:
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return (base >> (32 - shamt)) & 1;
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case LSR:
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if (shamt == 0)
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return (base >> 31) & 1;
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else
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return (base >> (shamt - 1)) & 1;
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case ASR:
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if (shamt == 0)
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return (base >> 31L);
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else
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return ((uint32_t) (((int32_t) base) >> (shamt - 1))) & 1;
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case ROR:
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shamt = shamt & 0x1f;
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if (shamt == 0)
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return (base & 1); // RRX
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else
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return (base >> (shamt - 1)) & 1;
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default:
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fprintf(stderr, "Unhandled shift type\n");
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exit(1);
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break;
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}
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return 0;
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}
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// Generate C for a shift by Rs
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inline int32_t
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shift_carry_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval)
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{
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enum ArmShiftType shiftType;
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shiftType = (enum ArmShiftType) type;
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switch (shiftType)
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{
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case LSL:
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if (shamt == 0)
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return (!!cfval);
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else if (shamt == 32)
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return (base & 1);
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else if (shamt > 32)
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return (0);
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else
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return ((base >> (32 - shamt)) & 1);
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case LSR:
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if (shamt == 0)
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return (!!cfval);
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else if (shamt == 32)
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return (base >> 31);
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else if (shamt > 32)
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return (0);
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else
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return ((base >> (shamt - 1)) & 1);
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case ASR:
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if (shamt == 0)
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return (!!cfval);
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else if (shamt >= 32)
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return (base >> 31L);
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else
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return (((uint32_t) (((int32_t) base) >> (shamt - 1))) & 1);
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case ROR:
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if (shamt == 0)
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return (!!cfval);
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shamt = shamt & 0x1f;
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if (shamt == 0)
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return (base >> 31); // RRX
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else
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return ((base >> (shamt - 1)) & 1);
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default:
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fprintf(stderr, "Unhandled shift type\n");
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exit(1);
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break;
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}
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return 0;
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}
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// Generate the appropriate carry bit for an addition operation
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inline int32_t
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arm_add_carry(int32_t result, int32_t lhs, int32_t rhs)
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{
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if ((lhs | rhs) >> 30)
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return ((arm_NEG(lhs) && arm_NEG(rhs)) ||
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(arm_NEG(lhs) && arm_POS(result)) ||
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(arm_NEG(rhs) && arm_POS(result)));
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else
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return 0;
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}
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// Generate the appropriate carry bit for a subtraction operation
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inline int32_t
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arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs)
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{
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if ((lhs >= rhs) || ((rhs | lhs) >> 31))
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return ((arm_NEG(lhs) && arm_POS(rhs)) ||
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(arm_NEG(lhs) && arm_POS(result)) ||
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(arm_POS(rhs) && arm_POS(result)));
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else
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return 0;
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}
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inline int32_t
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arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs)
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{
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if ((lhs | rhs) >> 30)
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return ((arm_NEG(lhs) && arm_NEG(rhs) && arm_POS(result)) ||
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(arm_POS(lhs) && arm_POS(rhs) && arm_NEG(result)));
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else
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return 0;
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}
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inline int32_t
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arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs)
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{
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if ((lhs >= rhs) || ((rhs | lhs) >> 31))
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return ((arm_NEG(lhs) && arm_POS(rhs) && arm_POS(result)) ||
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(arm_POS(lhs) && arm_NEG(rhs) && arm_NEG(result)));
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else
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return 0;
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}
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}};
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