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gem5/src/mem/ruby/slicc_interface/AbstractController.hh

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ruby: Import the latest ruby changes from gems. This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore.
2009-07-07 00:49:47 +02:00
#ifndef ABSTRACTCONTROLLER_H
#define ABSTRACTCONTROLLER_H
ruby: Convert most Ruby objects to M5 SimObjects. The necessary companion conversion of Ruby objects generated by SLICC are converted to M5 SimObjects in the following patch, so this patch alone does not compile. Conversion of Garnet network models is also handled in a separate patch; that code is temporarily disabled from compiling to allow testing of interim code.
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#include "sim/sim_object.hh"
#include "params/RubyController.hh"
ruby: Import the latest ruby changes from gems. This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore.
2009-07-07 00:49:47 +02:00
#include "mem/ruby/common/Consumer.hh"
#include "mem/protocol/MachineType.hh"
Multi-line RMW handling
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#include "mem/ruby/common/Address.hh"
ruby: connects sm queues to the network
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#include "mem/ruby/network/Network.hh"
ruby: Import the latest ruby changes from gems. This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore.
2009-07-07 00:49:47 +02:00
class MessageBuffer;
class Network;
ruby: Convert most Ruby objects to M5 SimObjects. The necessary companion conversion of Ruby objects generated by SLICC are converted to M5 SimObjects in the following patch, so this patch alone does not compile. Conversion of Garnet network models is also handled in a separate patch; that code is temporarily disabled from compiling to allow testing of interim code.
2010-01-30 05:29:17 +01:00
class AbstractController : public SimObject, public Consumer {
ruby: Import the latest ruby changes from gems. This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore.
2009-07-07 00:49:47 +02:00
public:
ruby: Convert most Ruby objects to M5 SimObjects. The necessary companion conversion of Ruby objects generated by SLICC are converted to M5 SimObjects in the following patch, so this patch alone does not compile. Conversion of Garnet network models is also handled in a separate patch; that code is temporarily disabled from compiling to allow testing of interim code.
2010-01-30 05:29:17 +01:00
typedef RubyControllerParams Params;
AbstractController(const Params *p) : SimObject(p) {}
ruby: Import the latest ruby changes from gems. This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore.
2009-07-07 00:49:47 +02:00
// returns the number of controllers created of the specific subtype
// virtual int getNumberOfControllers() const = 0;
virtual MessageBuffer* getMandatoryQueue() const = 0;
virtual const int & getVersion() const = 0;
virtual const string toString() const = 0; // returns text version of controller type
virtual const string getName() const = 0; // return instance name
virtual const MachineType getMachineType() const = 0;
ruby: new atomics implementation This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
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virtual void blockOnQueue(Address, MessageBuffer*) = 0;
virtual void unblock(Address) = 0;
ruby: connects sm queues to the network
2010-01-30 05:29:18 +01:00
virtual void initNetworkPtr(Network* net_ptr) = 0;
ruby: Import the latest ruby changes from gems. This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore.
2009-07-07 00:49:47 +02:00
virtual void print(ostream & out) const = 0;
virtual void printStats(ostream & out) const = 0;
virtual void printConfig(ostream & out) const = 0;
virtual void wakeup() = 0;
// virtual void dumpStats(ostream & out) = 0;
virtual void clearStats() = 0;
};
#endif
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