2010-11-10 07:48:03 +01:00
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1961801 # Simulator instruction rate (inst/s)
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host_mem_usage 209312 # Number of bytes of host memory used
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host_seconds 1.02 # Real time elapsed on the host
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host_tick_rate 714851017 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1999954 # Number of instructions simulated
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sim_seconds 0.000729 # Number of seconds simulated
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sim_ticks 728920000 # Number of ticks simulated
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system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency
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system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
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system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_avg_miss_latency 56064.748201 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53064.748201 # average WriteReq mshr miss latency
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system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_miss_latency 7793000 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_mshr_miss_latency 7376000 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
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system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_avg_miss_latency 55244.060475 # average overall miss latency
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system.cpu0.dcache.demand_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency
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system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits
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system.cpu0.dcache.demand_miss_latency 25578000 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
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system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses
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system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu0.dcache.demand_mshr_miss_latency 24189000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.occ_%::0 0.534216 # Average percentage of cache occupancy
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system.cpu0.dcache.occ_blocks::0 273.518805 # Average occupied blocks per context
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system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_avg_miss_latency 55244.060475 # average overall miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu0.dcache.overall_hits 180312 # number of overall hits
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system.cpu0.dcache.overall_miss_latency 25578000 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
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system.cpu0.dcache.overall_misses 463 # number of overall misses
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system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu0.dcache.overall_mshr_miss_latency 24189000 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
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system.cpu0.dcache.overall_mshr_misses 463 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu0.dcache.replacements 61 # number of replacements
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system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
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system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu0.dcache.tagsinuse 273.518805 # Cycle average of tags in use
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system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
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system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.writebacks 29 # number of writebacks
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system.cpu0.dtb.data_accesses 180793 # DTB accesses
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system.cpu0.dtb.data_acv 0 # DTB access violations
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system.cpu0.dtb.data_hits 180775 # DTB hits
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system.cpu0.dtb.data_misses 18 # DTB misses
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system.cpu0.dtb.fetch_accesses 0 # ITB accesses
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system.cpu0.dtb.fetch_acv 0 # ITB acv
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system.cpu0.dtb.fetch_hits 0 # ITB hits
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system.cpu0.dtb.fetch_misses 0 # ITB misses
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system.cpu0.dtb.read_accesses 124443 # DTB read accesses
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system.cpu0.dtb.read_acv 0 # DTB read access violations
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system.cpu0.dtb.read_hits 124435 # DTB read hits
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system.cpu0.dtb.read_misses 8 # DTB read misses
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system.cpu0.dtb.write_accesses 56350 # DTB write accesses
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system.cpu0.dtb.write_acv 0 # DTB write access violations
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system.cpu0.dtb.write_hits 56340 # DTB write hits
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system.cpu0.dtb.write_misses 10 # DTB write misses
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system.cpu0.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.ReadReq_avg_miss_latency 50699.784017 # average ReadReq miss latency
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system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47699.784017 # average ReadReq mshr miss latency
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system.cpu0.icache.ReadReq_hits 499557 # number of ReadReq hits
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system.cpu0.icache.ReadReq_miss_latency 23474000 # number of ReadReq miss cycles
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system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
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system.cpu0.icache.ReadReq_mshr_miss_latency 22085000 # number of ReadReq MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
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system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
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system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.demand_accesses 500020 # number of demand (read+write) accesses
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system.cpu0.icache.demand_avg_miss_latency 50699.784017 # average overall miss latency
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system.cpu0.icache.demand_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency
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system.cpu0.icache.demand_hits 499557 # number of demand (read+write) hits
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system.cpu0.icache.demand_miss_latency 23474000 # number of demand (read+write) miss cycles
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system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
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system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
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system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu0.icache.demand_mshr_miss_latency 22085000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
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system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
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system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.icache.occ_%::0 0.422639 # Average percentage of cache occupancy
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system.cpu0.icache.occ_blocks::0 216.390931 # Average occupied blocks per context
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system.cpu0.icache.overall_accesses 500020 # number of overall (read+write) accesses
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system.cpu0.icache.overall_avg_miss_latency 50699.784017 # average overall miss latency
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system.cpu0.icache.overall_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu0.icache.overall_hits 499557 # number of overall hits
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system.cpu0.icache.overall_miss_latency 23474000 # number of overall miss cycles
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system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
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system.cpu0.icache.overall_misses 463 # number of overall misses
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system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu0.icache.overall_mshr_miss_latency 22085000 # number of overall MSHR miss cycles
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system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
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system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses
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system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu0.icache.replacements 152 # number of replacements
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system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
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system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu0.icache.tagsinuse 216.390931 # Cycle average of tags in use
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system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
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system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.writebacks 0 # number of writebacks
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system.cpu0.idle_fraction 0 # Percentage of idle cycles
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system.cpu0.itb.data_accesses 0 # DTB accesses
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system.cpu0.itb.data_acv 0 # DTB access violations
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system.cpu0.itb.data_hits 0 # DTB hits
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system.cpu0.itb.data_misses 0 # DTB misses
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system.cpu0.itb.fetch_accesses 500033 # ITB accesses
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system.cpu0.itb.fetch_acv 0 # ITB acv
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system.cpu0.itb.fetch_hits 500020 # ITB hits
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system.cpu0.itb.fetch_misses 13 # ITB misses
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system.cpu0.itb.read_accesses 0 # DTB read accesses
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system.cpu0.itb.read_acv 0 # DTB read access violations
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system.cpu0.itb.read_hits 0 # DTB read hits
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system.cpu0.itb.read_misses 0 # DTB read misses
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system.cpu0.itb.write_accesses 0 # DTB write accesses
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system.cpu0.itb.write_acv 0 # DTB write access violations
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system.cpu0.itb.write_hits 0 # DTB write hits
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system.cpu0.itb.write_misses 0 # DTB write misses
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system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu0.numCycles 1457840 # number of cpu cycles simulated
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system.cpu0.num_insts 500001 # Number of instructions executed
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system.cpu0.num_refs 180793 # Number of memory references
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system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
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system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
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system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency
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system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency
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system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits
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system.cpu1.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles
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|
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system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
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system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
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|
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system.cpu1.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles
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|
|
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system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
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|
|
|
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system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
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system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
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system.cpu1.dcache.WriteReq_avg_miss_latency 56136.690647 # average WriteReq miss latency
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system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53136.690647 # average WriteReq mshr miss latency
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system.cpu1.dcache.WriteReq_hits 56200 # number of WriteReq hits
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system.cpu1.dcache.WriteReq_miss_latency 7803000 # number of WriteReq miss cycles
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system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
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system.cpu1.dcache.WriteReq_misses 139 # number of WriteReq misses
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system.cpu1.dcache.WriteReq_mshr_miss_latency 7386000 # number of WriteReq MSHR miss cycles
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system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
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system.cpu1.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
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system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks.
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system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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system.cpu1.dcache.demand_accesses 180774 # number of demand (read+write) accesses
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system.cpu1.dcache.demand_avg_miss_latency 55265.658747 # average overall miss latency
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system.cpu1.dcache.demand_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
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|
|
system.cpu1.dcache.demand_hits 180311 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.dcache.demand_miss_latency 25588000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.demand_misses 463 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_latency 24199000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu1.dcache.occ_%::0 0.534204 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.dcache.occ_blocks::0 273.512548 # Average occupied blocks per context
|
|
|
|
|
system.cpu1.dcache.overall_accesses 180774 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu1.dcache.overall_hits 180311 # number of overall hits
|
|
|
|
|
system.cpu1.dcache.overall_miss_latency 25588000 # number of overall miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.overall_misses 463 # number of overall misses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_latency 24199000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_misses 463 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu1.dcache.replacements 61 # number of replacements
|
|
|
|
|
system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu1.dcache.tagsinuse 273.512548 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu1.dcache.writebacks 29 # number of writebacks
|
|
|
|
|
system.cpu1.dtb.data_accesses 180792 # DTB accesses
|
|
|
|
|
system.cpu1.dtb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu1.dtb.data_hits 180774 # DTB hits
|
|
|
|
|
system.cpu1.dtb.data_misses 18 # DTB misses
|
|
|
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
|
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
|
|
|
system.cpu1.dtb.read_accesses 124443 # DTB read accesses
|
|
|
|
|
system.cpu1.dtb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu1.dtb.read_hits 124435 # DTB read hits
|
|
|
|
|
system.cpu1.dtb.read_misses 8 # DTB read misses
|
|
|
|
|
system.cpu1.dtb.write_accesses 56349 # DTB write accesses
|
|
|
|
|
system.cpu1.dtb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu1.dtb.write_hits 56339 # DTB write hits
|
|
|
|
|
system.cpu1.dtb.write_misses 10 # DTB write misses
|
|
|
|
|
system.cpu1.icache.ReadReq_accesses 500012 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_miss_latency 50697.624190 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47697.624190 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.icache.ReadReq_hits 499549 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_latency 23473000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency 22084000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu1.icache.demand_accesses 500012 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.icache.demand_avg_miss_latency 50697.624190 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency 47697.624190 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.demand_hits 499549 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.icache.demand_miss_latency 23473000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_latency 22084000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu1.icache.occ_%::0 0.422630 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.icache.occ_blocks::0 216.386658 # Average occupied blocks per context
|
|
|
|
|
system.cpu1.icache.overall_accesses 500012 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.icache.overall_avg_miss_latency 50697.624190 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency 47697.624190 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu1.icache.overall_hits 499549 # number of overall hits
|
|
|
|
|
system.cpu1.icache.overall_miss_latency 23473000 # number of overall miss cycles
|
|
|
|
|
system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_misses 463 # number of overall misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_latency 22084000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu1.icache.replacements 152 # number of replacements
|
|
|
|
|
system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu1.icache.tagsinuse 216.386658 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu1.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu1.idle_fraction 0 # Percentage of idle cycles
|
|
|
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu1.itb.fetch_accesses 500025 # ITB accesses
|
|
|
|
|
system.cpu1.itb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu1.itb.fetch_hits 500012 # ITB hits
|
|
|
|
|
system.cpu1.itb.fetch_misses 13 # ITB misses
|
|
|
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu1.numCycles 1457840 # number of cpu cycles simulated
|
|
|
|
|
system.cpu1.num_insts 499993 # Number of instructions executed
|
|
|
|
|
system.cpu1.num_refs 180792 # Number of memory references
|
|
|
|
|
system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
|
|
|
|
|
system.cpu2.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency
|
|
|
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu2.dcache.ReadReq_hits 124109 # number of ReadReq hits
|
|
|
|
|
system.cpu2.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
|
|
|
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu2.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency 56093.525180 # average WriteReq miss latency
|
|
|
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53093.525180 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu2.dcache.WriteReq_hits 56200 # number of WriteReq hits
|
|
|
|
|
system.cpu2.dcache.WriteReq_miss_latency 7797000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses
|
|
|
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency 7380000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu2.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu2.dcache.demand_accesses 180772 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu2.dcache.demand_avg_miss_latency 55272.138229 # average overall miss latency
|
|
|
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency
|
|
|
|
|
system.cpu2.dcache.demand_hits 180309 # number of demand (read+write) hits
|
|
|
|
|
system.cpu2.dcache.demand_miss_latency 25591000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
|
|
|
|
|
system.cpu2.dcache.demand_misses 463 # number of demand (read+write) misses
|
|
|
|
|
system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu2.dcache.demand_mshr_miss_latency 24202000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu2.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu2.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu2.dcache.occ_%::0 0.534196 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu2.dcache.occ_blocks::0 273.508588 # Average occupied blocks per context
|
|
|
|
|
system.cpu2.dcache.overall_accesses 180772 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu2.dcache.overall_avg_miss_latency 55272.138229 # average overall miss latency
|
|
|
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency
|
|
|
|
|
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu2.dcache.overall_hits 180309 # number of overall hits
|
|
|
|
|
system.cpu2.dcache.overall_miss_latency 25591000 # number of overall miss cycles
|
|
|
|
|
system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
|
|
|
|
|
system.cpu2.dcache.overall_misses 463 # number of overall misses
|
|
|
|
|
system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu2.dcache.overall_mshr_miss_latency 24202000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu2.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu2.dcache.overall_mshr_misses 463 # number of overall MSHR misses
|
|
|
|
|
system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu2.dcache.replacements 61 # number of replacements
|
|
|
|
|
system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu2.dcache.tagsinuse 273.508588 # Cycle average of tags in use
|
|
|
|
|
system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu2.dcache.writebacks 29 # number of writebacks
|
|
|
|
|
system.cpu2.dtb.data_accesses 180790 # DTB accesses
|
|
|
|
|
system.cpu2.dtb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu2.dtb.data_hits 180772 # DTB hits
|
|
|
|
|
system.cpu2.dtb.data_misses 18 # DTB misses
|
|
|
|
|
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
|
|
|
|
|
system.cpu2.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu2.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu2.dtb.fetch_misses 0 # ITB misses
|
|
|
|
|
system.cpu2.dtb.read_accesses 124441 # DTB read accesses
|
|
|
|
|
system.cpu2.dtb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu2.dtb.read_hits 124433 # DTB read hits
|
|
|
|
|
system.cpu2.dtb.read_misses 8 # DTB read misses
|
|
|
|
|
system.cpu2.dtb.write_accesses 56349 # DTB write accesses
|
|
|
|
|
system.cpu2.dtb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu2.dtb.write_hits 56339 # DTB write hits
|
|
|
|
|
system.cpu2.dtb.write_misses 10 # DTB write misses
|
|
|
|
|
system.cpu2.icache.ReadReq_accesses 500001 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu2.icache.ReadReq_avg_miss_latency 50719.222462 # average ReadReq miss latency
|
|
|
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47719.222462 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu2.icache.ReadReq_hits 499538 # number of ReadReq hits
|
|
|
|
|
system.cpu2.icache.ReadReq_miss_latency 23483000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses
|
|
|
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency 22094000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu2.icache.avg_refs 1078.915767 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu2.icache.demand_accesses 500001 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu2.icache.demand_avg_miss_latency 50719.222462 # average overall miss latency
|
|
|
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency 47719.222462 # average overall mshr miss latency
|
|
|
|
|
system.cpu2.icache.demand_hits 499538 # number of demand (read+write) hits
|
|
|
|
|
system.cpu2.icache.demand_miss_latency 23483000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
|
|
|
|
|
system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
|
|
|
|
|
system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu2.icache.demand_mshr_miss_latency 22094000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu2.icache.occ_%::0 0.422624 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu2.icache.occ_blocks::0 216.383557 # Average occupied blocks per context
|
|
|
|
|
system.cpu2.icache.overall_accesses 500001 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu2.icache.overall_avg_miss_latency 50719.222462 # average overall miss latency
|
|
|
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency 47719.222462 # average overall mshr miss latency
|
|
|
|
|
system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu2.icache.overall_hits 499538 # number of overall hits
|
|
|
|
|
system.cpu2.icache.overall_miss_latency 23483000 # number of overall miss cycles
|
|
|
|
|
system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
|
|
|
|
|
system.cpu2.icache.overall_misses 463 # number of overall misses
|
|
|
|
|
system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu2.icache.overall_mshr_miss_latency 22094000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses
|
|
|
|
|
system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu2.icache.replacements 152 # number of replacements
|
|
|
|
|
system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu2.icache.tagsinuse 216.383557 # Cycle average of tags in use
|
|
|
|
|
system.cpu2.icache.total_refs 499538 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu2.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu2.idle_fraction 0 # Percentage of idle cycles
|
|
|
|
|
system.cpu2.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu2.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu2.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu2.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu2.itb.fetch_accesses 500014 # ITB accesses
|
|
|
|
|
system.cpu2.itb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu2.itb.fetch_hits 500001 # ITB hits
|
|
|
|
|
system.cpu2.itb.fetch_misses 13 # ITB misses
|
|
|
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu2.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu2.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu2.numCycles 1457840 # number of cpu cycles simulated
|
|
|
|
|
system.cpu2.num_insts 499982 # Number of instructions executed
|
|
|
|
|
system.cpu2.num_refs 180789 # Number of memory references
|
|
|
|
|
system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
|
|
|
|
|
system.cpu3.dcache.ReadReq_accesses 124431 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency
|
|
|
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu3.dcache.ReadReq_hits 124107 # number of ReadReq hits
|
|
|
|
|
system.cpu3.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
|
|
|
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency 56093.525180 # average WriteReq miss latency
|
|
|
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53093.525180 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu3.dcache.WriteReq_hits 56200 # number of WriteReq hits
|
|
|
|
|
system.cpu3.dcache.WriteReq_miss_latency 7797000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu3.dcache.WriteReq_misses 139 # number of WriteReq misses
|
|
|
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency 7380000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu3.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu3.dcache.demand_accesses 180770 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu3.dcache.demand_avg_miss_latency 55265.658747 # average overall miss latency
|
|
|
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
|
|
|
|
|
system.cpu3.dcache.demand_hits 180307 # number of demand (read+write) hits
|
|
|
|
|
system.cpu3.dcache.demand_miss_latency 25588000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu3.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
|
|
|
|
|
system.cpu3.dcache.demand_misses 463 # number of demand (read+write) misses
|
|
|
|
|
system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu3.dcache.demand_mshr_miss_latency 24199000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu3.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu3.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu3.dcache.occ_%::0 0.534191 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu3.dcache.occ_blocks::0 273.505617 # Average occupied blocks per context
|
|
|
|
|
system.cpu3.dcache.overall_accesses 180770 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu3.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency
|
|
|
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
|
|
|
|
|
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu3.dcache.overall_hits 180307 # number of overall hits
|
|
|
|
|
system.cpu3.dcache.overall_miss_latency 25588000 # number of overall miss cycles
|
|
|
|
|
system.cpu3.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
|
|
|
|
|
system.cpu3.dcache.overall_misses 463 # number of overall misses
|
|
|
|
|
system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu3.dcache.overall_mshr_miss_latency 24199000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu3.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu3.dcache.overall_mshr_misses 463 # number of overall MSHR misses
|
|
|
|
|
system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu3.dcache.replacements 61 # number of replacements
|
|
|
|
|
system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu3.dcache.tagsinuse 273.505617 # Cycle average of tags in use
|
|
|
|
|
system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu3.dcache.writebacks 29 # number of writebacks
|
|
|
|
|
system.cpu3.dtb.data_accesses 180788 # DTB accesses
|
|
|
|
|
system.cpu3.dtb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu3.dtb.data_hits 180770 # DTB hits
|
|
|
|
|
system.cpu3.dtb.data_misses 18 # DTB misses
|
|
|
|
|
system.cpu3.dtb.fetch_accesses 0 # ITB accesses
|
|
|
|
|
system.cpu3.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu3.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu3.dtb.fetch_misses 0 # ITB misses
|
|
|
|
|
system.cpu3.dtb.read_accesses 124439 # DTB read accesses
|
|
|
|
|
system.cpu3.dtb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu3.dtb.read_hits 124431 # DTB read hits
|
|
|
|
|
system.cpu3.dtb.read_misses 8 # DTB read misses
|
|
|
|
|
system.cpu3.dtb.write_accesses 56349 # DTB write accesses
|
|
|
|
|
system.cpu3.dtb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu3.dtb.write_hits 56339 # DTB write hits
|
|
|
|
|
system.cpu3.dtb.write_misses 10 # DTB write misses
|
|
|
|
|
system.cpu3.icache.ReadReq_accesses 499997 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu3.icache.ReadReq_avg_miss_latency 50738.660907 # average ReadReq miss latency
|
|
|
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47738.660907 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu3.icache.ReadReq_hits 499534 # number of ReadReq hits
|
|
|
|
|
system.cpu3.icache.ReadReq_miss_latency 23492000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses
|
|
|
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency 22103000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu3.icache.avg_refs 1078.907127 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu3.icache.demand_accesses 499997 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu3.icache.demand_avg_miss_latency 50738.660907 # average overall miss latency
|
|
|
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency
|
|
|
|
|
system.cpu3.icache.demand_hits 499534 # number of demand (read+write) hits
|
|
|
|
|
system.cpu3.icache.demand_miss_latency 23492000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
|
|
|
|
|
system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses
|
|
|
|
|
system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu3.icache.demand_mshr_miss_latency 22103000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu3.icache.occ_%::0 0.422621 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu3.icache.occ_blocks::0 216.381810 # Average occupied blocks per context
|
|
|
|
|
system.cpu3.icache.overall_accesses 499997 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu3.icache.overall_avg_miss_latency 50738.660907 # average overall miss latency
|
|
|
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency
|
|
|
|
|
system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu3.icache.overall_hits 499534 # number of overall hits
|
|
|
|
|
system.cpu3.icache.overall_miss_latency 23492000 # number of overall miss cycles
|
|
|
|
|
system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
|
|
|
|
|
system.cpu3.icache.overall_misses 463 # number of overall misses
|
|
|
|
|
system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu3.icache.overall_mshr_miss_latency 22103000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses
|
|
|
|
|
system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu3.icache.replacements 152 # number of replacements
|
|
|
|
|
system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu3.icache.tagsinuse 216.381810 # Cycle average of tags in use
|
|
|
|
|
system.cpu3.icache.total_refs 499534 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu3.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu3.idle_fraction 0 # Percentage of idle cycles
|
|
|
|
|
system.cpu3.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu3.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu3.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu3.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu3.itb.fetch_accesses 500010 # ITB accesses
|
|
|
|
|
system.cpu3.itb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu3.itb.fetch_hits 499997 # ITB hits
|
|
|
|
|
system.cpu3.itb.fetch_misses 13 # ITB misses
|
|
|
|
|
system.cpu3.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu3.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu3.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu3.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu3.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu3.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu3.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu3.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu3.numCycles 1457840 # number of cpu cycles simulated
|
|
|
|
|
system.cpu3.num_insts 499978 # Number of instructions executed
|
|
|
|
|
system.cpu3.num_refs 180787 # Number of memory references
|
|
|
|
|
system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
|
|
|
|
|
system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::0 208021.582734 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::1 208021.582734 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::2 208021.582734 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::3 208021.582734 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::total 832086.330935 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40005.395683 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_miss_latency 28915000 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_misses::0 139 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::1 139 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency 22243000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 4 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 4 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::2 4 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::3 4 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 16 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_accesses::0 787 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::1 787 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::0 208043.175487 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::1 208043.175487 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::2 208043.175487 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::3 208043.175487 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::total 832172.701950 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40010.793872 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_hits::0 69 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::1 69 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::2 69 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::3 69 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_miss_latency 149375000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::3 0.912325 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::total 3.649301 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_misses::0 718 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::1 718 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::2 718 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::3 718 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency 114911000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::0 3.649301 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::1 3.649301 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::2 3.649301 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::3 3.649301 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::total 14.597205 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_hits::0 116 # number of Writeback hits
|
|
|
|
|
system.l2c.Writeback_hits::total 116 # number of Writeback hits
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
|
|
|
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.l2c.demand_accesses::0 926 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::1 926 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_avg_miss_latency::0 208039.673279 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::1 208039.673279 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::2 208039.673279 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::3 208039.673279 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::total 832158.693116 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency 40009.918320 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_hits::0 69 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::1 69 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::2 69 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::3 69 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::total 276 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_miss_latency 178290000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::3 0.925486 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::total 3.701944 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_misses::0 857 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::1 857 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::2 857 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::3 857 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.l2c.demand_mshr_miss_latency 137154000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::0 3.701944 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::1 3.701944 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::2 3.701944 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::3 3.701944 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::total 14.807775 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_misses 3428 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.l2c.occ_%::0 0.007348 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_%::1 0.007347 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_%::2 0.007347 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_%::3 0.007347 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_%::4 0.000263 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_blocks::0 481.530369 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::1 481.519672 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::2 481.512310 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::3 481.507730 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::4 17.228456 # Average occupied blocks per context
|
|
|
|
|
system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_avg_miss_latency::0 208039.673279 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::1 208039.673279 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::2 208039.673279 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::3 208039.673279 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::total 832158.693116 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency 40009.918320 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.l2c.overall_hits::0 69 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::1 69 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::2 69 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::3 69 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::total 276 # number of overall hits
|
|
|
|
|
system.l2c.overall_miss_latency 178290000 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_misses::0 857 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::1 857 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::2 857 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::3 857 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::total 3428 # number of overall misses
|
|
|
|
|
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.l2c.overall_mshr_miss_latency 137154000 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::0 3.701944 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::1 3.701944 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::2 3.701944 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::3 3.701944 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::total 14.807775 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.l2c.replacements 0 # number of replacements
|
|
|
|
|
system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
|
|
|
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.l2c.tagsinuse 1943.298536 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 332 # Total number of references to valid blocks.
|
|
|
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.l2c.writebacks 0 # number of writebacks
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
