147 lines
4.8 KiB
INI
147 lines
4.8 KiB
INI
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# Copyright (c) 2010 Massachusetts Institute of Technology
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Chia-Hsin Owen Chen
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# Technology related parameters
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# technology node in nm (90, 65, 45, 32)
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TECH_NODE = 65
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# transistor type (HVT, NVT, LVT)
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TRANSISTOR_TYPE = NVT
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# operating voltage supply in volt
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VDD = 1.0
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# operating frequency in Hz
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FREQUENCY = 1.0e9
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# router module parameters
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# general parameters
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# number of router input ports
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NUM_INPUT_PORT = 0
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# number of router output ports
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NUM_OUTPUT_PORT = 0
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# flit width in bit
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FLIT_WIDTH = 0
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# virtual channel parameters
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# number of message classes per port
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NUM_VIRTUAL_CLASS = 0
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# number of virtual channels per message class
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NUM_VIRTUAL_CHANNEL = 0
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# Are input virtual channels managed in a shared buffer? (Private buffer otherwise)
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IS_IN_SHARED_BUFFER = FALSE
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# Are output virtual channels managed in a shared buffer? (Private buffer otherwise)
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IS_OUT_SHARED_BUFFER = FALSE
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# Are input virtual channels sharing the same crossbar input ports?
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IS_IN_SHARED_SWITCH = TRUE
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# Are output virtual channels sharing the same crossbar output ports?
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IS_OUT_SHARED_SWITCH = TRUE
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# crossbar parameters
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# crossbar model
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CROSSBAR_MODEL = MULTREE_CROSSBAR
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CROSSBAR_CONNECT_TYPE = TRISTATE_GATE
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CROSSBAR_TRANS_GATE_TYPE = NP_GATE
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CROSSBAR_MUX_DEGREE = 4
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CROSSBAR_NUM_IN_SEG = 1
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CROSSBAR_NUM_OUT_SEG = 1
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# crossbar input line length
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CROSSBAR_LEN_IN_WIRE = 0
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# crossbar output line length
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CROSSBAR_LEN_OUT_WIRE = 0
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# input buffer parameters
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IS_INPUT_BUFFER = TRUE
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# input buffer model (SRAM, REGISTER)
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IN_BUF_MODEL = REGISTER
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IN_BUF_NUM_SET = 0
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IN_BUF_NUM_READ_PORT = 1
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# output buffer parameters */
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IS_OUTPUT_BUFFER = FALSE
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# output buffer model (SRAM, REGISTER)
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OUT_BUF_MODEL = SRAM
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OUT_BUF_NUM_SET = 0
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OUT_BUF_NUM_WRITE_PORT = 0
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# array parameters shared by various sram buffers
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SRAM_ROWDEC_MODEL = GENERIC_DEC
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SRAM_ROWDEC_PRE_MODEL = SINGLE_OTHER
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SRAM_WORDLINE_MODEL = RW_WORDLINE
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SRAM_BITLINE_MODEL = RW_BITLINE
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SRAM_OUTDRV_MODEL = REG_OUTDRV
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# these 3 should be changed together
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# use double-ended bitline because the array is too large
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SRAM_NUM_DATA_END = 2
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SRAM_AMP_MODEL = GENERIC_AMP
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SRAM_BITLINE_PRE_MODEL = EQU_BITLINE
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# SRAM_NUM_DATA_END = 1
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# SRAM_AMP_MODEL = NO_MODEL
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# SRAM_BITLINE_PRE_MODEL = SINGLE_OTHER
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# switch allocator arbiter parameters
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# arbiter mode (MATRIX_ARBITER, RR_ARBITER)
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SA_IN_ARB_MODEL = RR_ARBITER
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# flip-flop model
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SA_IN_ARB_FF_MODEL = NEG_DFF
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# arbiter mode (MATRIX_ARBITER, RR_ARBITER)
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SA_OUT_ARB_MODEL = MATRIX_ARBITER
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# flip-flop model
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SA_OUT_ARB_FF_MODEL = NEG_DFF
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# virtual channel allocator arbiter parameters
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# allocator model (ONE_STAGE_ARB, TWO_STAGE_ARB, VC_SELECT)
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VA_MODEL = TWO_STAGE_ARB
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# arbiter mode (MATRIX_ARBITER, RR_ARBITER)
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VA_IN_ARB_MODEL = RR_ARBITER
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# flip-flop model
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VA_IN_ARB_FF_MODEL = NEG_DFF
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# arbiter mode (MATRIX_ARBITER, RR_ARBITER)
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VA_OUT_ARB_MODEL = MATRIX_ARBITER
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# flip-flop model
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VA_OUT_ARB_FF_MODEL = NEG_DFF
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# buffer model if VC_SELECT is used (SRAM, REGISTER)
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VA_BUF_MODEL = REGISTER
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# link wire parameters
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#link length in metres
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LINK_LENGTH = 1e-3
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# wire layer model (INTERMEDIATE, GLOBAL)
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WIRE_LAYER_TYPE = GLOBAL
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# wire width spacing (SWIDTH_SSPACE, SWIDTH_DSPACE, DWIDTH_SSPACE, DWIDTH_DSPACE)
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WIRE_WIDTH_SPACING = DWIDTH_DSPACE
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# buffering model (MIN_DELAY, STAGGERED)
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WIRE_BUFFERING_MODEL = MIN_DELAY
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# is shielding
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WIRE_IS_SHIELDING = FALSE
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# clock power parameters
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NUM_PIPELINE_STAGE = 3
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IS_HTREE_CLOCK = FALSE
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# router diagonal in um
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ROUTER_DIAGONAL = 442
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