2014-07-23 23:09:04 +02:00
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# Copyright (c) 2013 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andrew Bardsley
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#
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# minor.pic: Pipeline appearance of the Minor pipeline for minorview
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# Markup of the pipeline blocks.
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# '>' and '<' are connecting arrows.
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# '/', ':' and '\' mark multi-line arrows.
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# All other (non-space) character rectangles are the shapes of the
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# corresponding blocks below the markup.
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<<<
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IPIPIPIPIPIPIPIPIP LSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLS KKKKKKKKKK
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IP IP LS LS KK KK
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IPiririr-\itititIP LSimimim drdrdr-\dtdtdtdt sbsbsbsbsbsbLS KK KK
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IPiririr-/itititIP LSimimim drdrdr-/dtdtdtdt sbsbsbsbsbsbLS KK KK
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IPIPIPIPIPIPIPIPIP LSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLSLS KK KK
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KK KK
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KK KK
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acacac sasasasasasasasa EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE KK KK
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acacac sasasasasasasasa EE EE KK KK
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EEscscscscscscscscscscscscscscscscscscscEE KK KK
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EEscscscscscscscscscscscscscscscscscscscEE KK KK
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EE EE KK KK
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F1F1F1F1-\1212-\F2F2F2F2-\2D2D-\DDDD-\DEDE-\EEiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqEE KK KK
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F1 F1 :1212 :F2 F2 :2D2D :DDDD :DEDE :EEiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqiqEE KK KK
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F1fefeF1 :1212 :F2fifiF2 :2D2D :DDDD :DEDE :EE EE KK KK
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F1fefeF1 :1212 :F2fifiF2 :2D2D :DDDD :DEDE :EEEiEiEiEi f0f0f0f0f0f0f0f0f0f0f0 ccccEE KK KK
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F1fefeF1 :1212 :F2fifiF2 :2D2D :DDDD :DEDE :EEEiEiEiEi f0f0f0f0f0f0f0f0f0f0f0 ccccEE KK KK
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F1fefeF1 :1212 :F2fifiF2-/2D2D-/DDDD-/DEDE-/EEEiEiEiEi f1f1f1f1f1f1f1f1f1f1f1 ccccEE KKKKKKKKKK
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F1fefeF1 :1212 :F2fifiF2 DDDD EEEiEiEiEi f1f1f1f1f1f1f1f1f1f1f1 ccccEE
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F1fefeF1-/1212-/F2fifiF2 DDDD EEEiEiEiEi f2f2f2f2f2f2f2f2f2f2f2 ccccEE
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b2b2-\F1fefeF1 -\F2fifiF2 DDDD EEEiEiEiEi f2f2f2f2f2f2f2f2f2f2f2 ccccEE-\b1b1
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b2b2-/F1fefeF1 -/F2fifiF2 DDDD EEEiEiEiEi f3f3f3f3f3f3f3f3f3f3f3 ccccEE-/b1b1
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F1fefeF1/-2121/-F2fifiF2 DDDD EEEiEiEiEi f3f3f3f3f3f3f3f3f3f3f3 ccccEE
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F1F1F1F1\-2121\-F2F2F2F2 DDDD EEEiEiEiEi f4f4f4f4f4f4f4f4f4f4f4 ccccEE
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EEEiEiEiEi f4f4f4f4f4f4f4f4f4f4f4 ccccEE
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FiFiFiFi DiDiDiDi EE f5f5f5f5f5f5f5f5f5f5f5 ccccEE
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Fi Fi Di Di EE f5f5f5f5f5f5f5f5f5f5f5 ccccEE
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FiFiFiFi DiDiDiDi EE f6f6f6f6f6f6f6f6f6f6f6 ccccEE
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EE f6f6f6f6f6f6f6f6f6f6f6 ccccEE
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EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE
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>>>
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# Macros for block type appearance. Macros are expanded in the 'block'
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# lines below and can include other macros.
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#
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# Attributes are name=value pairs.
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# Available names (and valid values);
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#
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# shape: {fifo, box, openBottom}
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# stripDir: {vert, horiz}
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# stripOrd: {RL, LR}
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# decoder: {insts, lines, branch, dcache, counts}
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# border: {thin, mid, thick}
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# dataElement: <name>
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# hideId: ({T, S, P, L, F, E})*
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# name: <string>
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# colours: ({U, B, -, E, R, F, r, w, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9})*
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# type: {key, block}
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# macro fifo: shape=fifo stripDir=vert
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macro fifo: shape=openBottom stripDir=horiz stripOrd=RL border=mid
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macro fu: decoder=insts border=mid name="" nameLoc=left
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# macro back: decoder=back border=mid dataElement=space name=""
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macro prediction: decoder=branch border=mid dataElement=prediction name=""
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macro forward: border=mid name=""
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macro dcache: fifo decoder=dcache dataElement=addr
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macro icache: fifo decoder=lines
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macro cacheFrame: stripDir=vert decoder=frame blankStrips=5 \
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dataElement=in_tlb_mem
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macro activity: decoder=counts shorten=2 border=mid
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macro inputBuffer: name="inputBuffer" fifo
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macro seqNum: decoder=counts border=mid
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macro streamFrame: decoder=frame stripDir=vert dataElement=streamSeqNum
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macro predictionFrame: decoder=frame stripDir=vert dataElement=predictionSeqNum
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# Block descriptions:
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# description ::= <char>: <unit-name-in-trace>
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# ( {<macro-name>, <name>=<value> )*
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# name ::= ? alphanumeric name with dots ?
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# value ::= "(<char-except-">)*", <char-except-' '>* }
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2016-07-21 18:19:16 +02:00
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Fi: fetch2.inputBuffer0 inputBuffer decoder=lines
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Di: decode.inputBuffer0 inputBuffer decoder=insts hideId=E
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Ei: execute.inputBuffer0 inputBuffer stripDir=horiz decoder=insts border=mid
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2014-07-23 23:09:04 +02:00
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F1: fetch1 streamFrame blankStrips=11 name="Fetch1"
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fe: fetch1 decoder=lines border=thin name="Line"
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F2: fetch2 predictionFrame blankStrips=11 name="Fetch2"
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fi: fetch2 decoder=insts border=thin name="Insts"
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DD: decode decoder=insts name="Decode"
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EE: execute streamFrame blankStrips=21 name="Execute"
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cc: execute decoder=insts name="Commit" border=mid
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12: f1ToF2 forward decoder=lines
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21: f2ToF1 prediction
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2D: f2ToD forward decoder=insts hideId=E
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DE: dToE forward decoder=insts
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b1: eToF1 forward decoder=branch
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b2: eToF1 forward decoder=branch
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IP: fetch1 cacheFrame name="Fetch queues"
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LS: execute.lsq cacheFrame name="LSQ"
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ir: fetch1.requests icache name="Requests"
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it: fetch1.transfers icache name="Transfers"
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dr: execute.lsq.requests dcache name="Requests"
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dt: execute.lsq.transfers dcache name="Transfers"
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sb: execute.lsq.storeBuffer dcache name="Store buffer"
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KK: _ type=key colours="UB-ERFrw0123456789"
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f0: execute.fu.0 fu shorten=2 name=Int
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f1: execute.fu.1 fu shorten=2 name=Int
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f2: execute.fu.2 fu shorten=2 name=Mul
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f3: execute.fu.3 fu shorten=2 name=Div
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f4: execute.fu.4 fu shorten=2 name=Float
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f5: execute.fu.5 fu shorten=2 name=Mem
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f6: execute.fu.6 fu shorten=2 name=Misc
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2016-07-21 18:19:16 +02:00
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iq: execute.inFlightInsts0 fifo decoder=insts name="inFlightInsts"
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im: execute.inFUMemInsts0 fifo decoder=insts name="inFU..."
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sc: execute.scoreboard0 name="scoreboard" decoder=indexedCounts \
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2014-07-23 23:09:04 +02:00
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dataElement=busy border=mid name="scoreboard" strips=38 stripelems=3
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sa: activity dataElement=stages activity name="Stage activity"
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ac: activity dataElement=activity decoder=counts border=mid name="Activity"
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