449 lines
7.8 KiB
INI
449 lines
7.8 KiB
INI
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[root]
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type=Root
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children=system
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eventq_index=0
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full_system=false
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sim_quantum=0
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=System
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children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus
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boot_osflags=a
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cache_line_size=64
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clk_domain=system.clk_domain
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eventq_index=0
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init_param=0
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kernel=
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kernel_addr_check=true
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load_addr_mask=1099511627775
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load_offset=0
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mem_mode=timing
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mem_ranges=0:536870911
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memories=system.mem_ctrl
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mmap_using_noreserve=false
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num_work_ids=16
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readfile=
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symbolfile=
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[1]
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[system.clk_domain]
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type=SrcClockDomain
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children=voltage_domain
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clock=1000
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domain_id=-1
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eventq_index=0
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init_perf_level=0
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voltage_domain=system.clk_domain.voltage_domain
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[system.clk_domain.voltage_domain]
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type=VoltageDomain
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eventq_index=0
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voltage=1.000000
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[system.cpu]
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type=TimingSimpleCPU
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children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload
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branchPred=Null
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checker=Null
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clk_domain=system.clk_domain
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cpu_id=-1
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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dstage2_mmu=system.cpu.dstage2_mmu
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dtb=system.cpu.dtb
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eventq_index=0
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function_trace=false
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function_trace_start=0
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interrupts=system.cpu.interrupts
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isa=system.cpu.isa
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istage2_mmu=system.cpu.istage2_mmu
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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profile=0
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progress_interval=0
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simpoint_start_insts=
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socket_id=0
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switched_out=false
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system=system
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tracer=system.cpu.tracer
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workload=system.cpu.workload
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dcache_port=system.cpu.dcache.cpu_side
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icache_port=system.cpu.icache.cpu_side
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[system.cpu.dcache]
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type=Cache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
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clk_domain=system.clk_domain
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_read_only=false
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=65536
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system=system
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tags=system.cpu.dcache.tags
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tgts_per_mshr=20
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write_buffers=8
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cpu_side=system.cpu.dcache_port
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mem_side=system.l2bus.slave[1]
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[system.cpu.dcache.tags]
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type=LRU
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assoc=2
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block_size=64
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clk_domain=system.clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=65536
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[system.cpu.dstage2_mmu]
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type=ArmStage2MMU
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children=stage2_tlb
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eventq_index=0
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stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
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sys=system
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tlb=system.cpu.dtb
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[system.cpu.dstage2_mmu.stage2_tlb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=true
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size=32
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walker=system.cpu.dstage2_mmu.stage2_tlb.walker
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[system.cpu.dstage2_mmu.stage2_tlb.walker]
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type=ArmTableWalker
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clk_domain=system.clk_domain
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eventq_index=0
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is_stage2=true
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num_squash_per_cycle=2
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sys=system
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[system.cpu.dtb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=false
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size=64
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walker=system.cpu.dtb.walker
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[system.cpu.dtb.walker]
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type=ArmTableWalker
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clk_domain=system.clk_domain
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eventq_index=0
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is_stage2=false
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num_squash_per_cycle=2
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sys=system
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[system.cpu.icache]
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type=Cache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
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clk_domain=system.clk_domain
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_read_only=false
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=16384
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system=system
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tags=system.cpu.icache.tags
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tgts_per_mshr=20
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write_buffers=8
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cpu_side=system.cpu.icache_port
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mem_side=system.l2bus.slave[0]
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[system.cpu.icache.tags]
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type=LRU
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assoc=2
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block_size=64
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clk_domain=system.clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=16384
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[system.cpu.interrupts]
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type=ArmInterrupts
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eventq_index=0
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[system.cpu.isa]
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type=ArmISA
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eventq_index=0
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fpsid=1090793632
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id_aa64afr0_el1=0
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id_aa64afr1_el1=0
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id_aa64dfr0_el1=1052678
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id_aa64dfr1_el1=0
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id_aa64isar0_el1=0
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id_aa64isar1_el1=0
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id_aa64mmfr0_el1=15728642
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id_aa64mmfr1_el1=0
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id_aa64pfr0_el1=17
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id_aa64pfr1_el1=0
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id_isar0=34607377
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id_isar1=34677009
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id_isar2=555950401
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id_isar3=17899825
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id_isar4=268501314
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id_isar5=0
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id_mmfr0=270536963
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id_mmfr1=0
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id_mmfr2=19070976
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id_mmfr3=34611729
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id_pfr0=49
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id_pfr1=4113
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midr=1091551472
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pmu=Null
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system=system
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[system.cpu.istage2_mmu]
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type=ArmStage2MMU
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children=stage2_tlb
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eventq_index=0
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stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
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sys=system
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tlb=system.cpu.itb
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[system.cpu.istage2_mmu.stage2_tlb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=true
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size=32
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walker=system.cpu.istage2_mmu.stage2_tlb.walker
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[system.cpu.istage2_mmu.stage2_tlb.walker]
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type=ArmTableWalker
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clk_domain=system.clk_domain
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eventq_index=0
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is_stage2=true
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num_squash_per_cycle=2
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sys=system
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[system.cpu.itb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=false
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size=64
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walker=system.cpu.itb.walker
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[system.cpu.itb.walker]
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type=ArmTableWalker
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clk_domain=system.clk_domain
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eventq_index=0
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is_stage2=false
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num_squash_per_cycle=2
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sys=system
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[system.cpu.tracer]
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type=ExeTracer
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eventq_index=0
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[system.cpu.workload]
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type=LiveProcess
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cmd=tests/test-progs/hello/bin/arm/linux/hello
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cwd=
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drivers=
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egid=100
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env=
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errout=cerr
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euid=100
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eventq_index=0
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executable=
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gid=100
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input=cin
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kvmInSE=false
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max_stack_size=67108864
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output=cout
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pid=100
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ppid=99
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simpoint=0
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system=system
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uid=100
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useArchPT=false
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[system.dvfs_handler]
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type=DVFSHandler
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domains=
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enable=false
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eventq_index=0
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sys_clk_domain=system.clk_domain
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transition_latency=100000000
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[system.l2bus]
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type=CoherentXBar
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clk_domain=system.clk_domain
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eventq_index=0
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forward_latency=0
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frontend_latency=1
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response_latency=1
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snoop_filter=Null
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snoop_response_latency=1
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system=system
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use_default_range=false
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width=32
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master=system.l2cache.cpu_side
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slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
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[system.l2cache]
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type=Cache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=8
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clk_domain=system.clk_domain
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=20
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is_read_only=false
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max_miss_count=0
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mshrs=20
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prefetch_on_access=false
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prefetcher=Null
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response_latency=20
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sequential_access=false
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size=262144
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system=system
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tags=system.l2cache.tags
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tgts_per_mshr=12
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write_buffers=8
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cpu_side=system.l2bus.master[0]
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mem_side=system.membus.slave[0]
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[system.l2cache.tags]
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type=LRU
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assoc=8
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block_size=64
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clk_domain=system.clk_domain
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eventq_index=0
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hit_latency=20
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sequential_access=false
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size=262144
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[system.mem_ctrl]
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type=DRAMCtrl
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IDD0=0.075000
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IDD02=0.000000
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IDD2N=0.050000
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IDD2N2=0.000000
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IDD2P0=0.000000
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IDD2P02=0.000000
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IDD2P1=0.000000
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IDD2P12=0.000000
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IDD3N=0.057000
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IDD3N2=0.000000
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IDD3P0=0.000000
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IDD3P02=0.000000
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IDD3P1=0.000000
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IDD3P12=0.000000
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IDD4R=0.187000
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IDD4R2=0.000000
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IDD4W=0.165000
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IDD4W2=0.000000
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IDD5=0.220000
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IDD52=0.000000
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IDD6=0.000000
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IDD62=0.000000
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VDD=1.500000
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VDD2=0.000000
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activation_limit=4
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addr_mapping=RoRaBaCoCh
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bank_groups_per_rank=0
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banks_per_rank=8
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burst_length=8
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channels=1
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clk_domain=system.clk_domain
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conf_table_reported=true
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device_bus_width=8
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device_rowbuffer_size=1024
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|
|
device_size=536870912
|
||
|
|
devices_per_rank=8
|
||
|
|
dll=true
|
||
|
|
eventq_index=0
|
||
|
|
in_addr_map=true
|
||
|
|
max_accesses_per_row=16
|
||
|
|
mem_sched_policy=frfcfs
|
||
|
|
min_writes_per_switch=16
|
||
|
|
null=false
|
||
|
|
page_policy=open_adaptive
|
||
|
|
range=0:536870911
|
||
|
|
ranks_per_channel=2
|
||
|
|
read_buffer_size=32
|
||
|
|
static_backend_latency=10000
|
||
|
|
static_frontend_latency=10000
|
||
|
|
tBURST=5000
|
||
|
|
tCCD_L=0
|
||
|
|
tCK=1250
|
||
|
|
tCL=13750
|
||
|
|
tCS=2500
|
||
|
|
tRAS=35000
|
||
|
|
tRCD=13750
|
||
|
|
tREFI=7800000
|
||
|
|
tRFC=260000
|
||
|
|
tRP=13750
|
||
|
|
tRRD=6000
|
||
|
|
tRRD_L=0
|
||
|
|
tRTP=7500
|
||
|
|
tRTW=2500
|
||
|
|
tWR=15000
|
||
|
|
tWTR=7500
|
||
|
|
tXAW=30000
|
||
|
|
tXP=0
|
||
|
|
tXPDLL=0
|
||
|
|
tXS=0
|
||
|
|
tXSDLL=0
|
||
|
|
write_buffer_size=64
|
||
|
|
write_high_thresh_perc=85
|
||
|
|
write_low_thresh_perc=50
|
||
|
|
port=system.membus.master[0]
|
||
|
|
|
||
|
|
[system.membus]
|
||
|
|
type=CoherentXBar
|
||
|
|
clk_domain=system.clk_domain
|
||
|
|
eventq_index=0
|
||
|
|
forward_latency=4
|
||
|
|
frontend_latency=3
|
||
|
|
response_latency=2
|
||
|
|
snoop_filter=Null
|
||
|
|
snoop_response_latency=4
|
||
|
|
system=system
|
||
|
|
use_default_range=false
|
||
|
|
width=16
|
||
|
|
master=system.mem_ctrl.port
|
||
|
|
slave=system.l2cache.mem_side system.system_port
|
||
|
|
|