234 lines
25 KiB
Text
234 lines
25 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1188041 # Simulator instruction rate (inst/s)
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host_mem_usage 205272 # Number of bytes of host memory used
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host_seconds 1420.24 # Real time elapsed on the host
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host_tick_rate 1757384537 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1687299939 # Number of instructions simulated
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sim_seconds 2.495902 # Number of seconds simulated
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sim_ticks 2495902189000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 482384248 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 24911.078403 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21911.078403 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 475158152 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 180009844000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.014980 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 7226096 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 158331556000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.014980 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 7226096 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 172586108 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 55999.839740 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.839740 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 170339765 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 125794848000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.013016 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 2246343 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 119055819000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.013016 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 2246343 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 70.854389 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 654970356 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 32283.627480 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 29283.627480 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 645497917 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 305804692000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.014462 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 9472439 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 277387375000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.014462 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 9472439 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.997080 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4084.040360 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 654970356 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 32283.627480 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 29283.627480 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 645497917 # number of overall hits
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system.cpu.dcache.overall_miss_latency 305804692000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.014462 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 9472439 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 277387375000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.014462 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 9472439 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 9111149 # number of replacements
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system.cpu.dcache.sampled_refs 9115245 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4084.040360 # Cycle average of tags in use
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system.cpu.dcache.total_refs 645855111 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 25923946000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 2243257 # number of writebacks
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.icache.ReadReq_accesses 1544565415 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 54551.724138 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1544564777 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 34804000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 638 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 32890000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 638 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 2420947.926332 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 1544565415 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 54551.724138 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency
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system.cpu.icache.demand_hits 1544564777 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 34804000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
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system.cpu.icache.demand_misses 638 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 32890000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 638 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.251129 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 514.312841 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 1544565415 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 54551.724138 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 1544564777 # number of overall hits
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system.cpu.icache.overall_miss_latency 34804000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
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system.cpu.icache.overall_misses 638 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 32890000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 638 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 7 # number of replacements
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system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 514.312841 # Cycle average of tags in use
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system.cpu.icache.total_refs 1544564777 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.l2cache.ReadExReq_accesses 1889149 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 98235748000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 1889149 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 75565960000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 1889149 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 7226734 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 5348868 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 97649032000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.259850 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 1877866 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 75114640000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259850 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 1877866 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 357194 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 51947.591505 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 18555368000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 357194 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14287760000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 357194 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 2243257 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 2243257 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 2.405017 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 9115883 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 5348868 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 195884780000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.413236 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 3767015 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 150680600000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.413236 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 3767015 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.occ_%::0 0.425307 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_%::1 0.349424 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_blocks::0 13936.465557 # Average occupied blocks per context
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system.cpu.l2cache.occ_blocks::1 11449.922093 # Average occupied blocks per context
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system.cpu.l2cache.overall_accesses 9115883 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 5348868 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 195884780000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.413236 # miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.overall_misses 3767015 # number of overall misses
|
||
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||
|
|
system.cpu.l2cache.overall_mshr_miss_latency 150680600000 # number of overall MSHR miss cycles
|
||
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.413236 # mshr miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.overall_mshr_misses 3767015 # number of overall MSHR misses
|
||
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||
|
|
system.cpu.l2cache.replacements 2752487 # number of replacements
|
||
|
|
system.cpu.l2cache.sampled_refs 2779653 # Sample count of references to valid blocks.
|
||
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||
|
|
system.cpu.l2cache.tagsinuse 25386.387650 # Cycle average of tags in use
|
||
|
|
system.cpu.l2cache.total_refs 6685114 # Total number of references to valid blocks.
|
||
|
|
system.cpu.l2cache.warmup_cycle 562275129000 # Cycle when the warmup percentage was hit.
|
||
|
|
system.cpu.l2cache.writebacks 1196151 # number of writebacks
|
||
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||
|
|
system.cpu.numCycles 4991804378 # number of cpu cycles simulated
|
||
|
|
system.cpu.num_insts 1687299939 # Number of instructions executed
|
||
|
|
system.cpu.num_refs 660773876 # Number of memory references
|
||
|
|
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
||
|
|
|
||
|
|
---------- End Simulation Statistics ----------
|