1573 lines
180 KiB
Text
1573 lines
180 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.401421 # Number of seconds simulated
|
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|
sim_ticks 2401421439000 # Number of ticks simulated
|
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final_tick 2401421439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
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|
sim_freq 1000000000000 # Frequency of simulated ticks
|
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|
host_inst_rate 170882 # Simulator instruction rate (inst/s)
|
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|
host_op_rate 219406 # Simulator op (including micro ops) rate (op/s)
|
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host_tick_rate 6786575645 # Simulator tick rate (ticks/s)
|
||
|
host_mem_usage 393972 # Number of bytes of host memory used
|
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|
host_seconds 353.85 # Real time elapsed on the host
|
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sim_insts 60466509 # Number of instructions simulated
|
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|
sim_ops 77636591 # Number of ops (including micro ops) simulated
|
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|
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
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|
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
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|
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 478816 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 7027600 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 73664 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 716876 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.dtb.walker 1216 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 218496 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 1332556 # Number of bytes read from this memory
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system.physmem.bytes_read::total 124668680 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 478816 # Number of instructions bytes read from this memory
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||
|
system.physmem.bytes_inst_read::cpu1.inst 73664 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 218496 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 770976 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3748032 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 1052216 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 199484 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu2.data 1764144 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6763876 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 13684 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 109840 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 1151 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 11204 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.dtb.walker 19 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 3414 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 20824 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 14512526 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 58563 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 263054 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 49871 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu2.data 441036 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 812524 # Number of write requests responded to by this memory
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|
system.physmem.bw_read::realview.clcd 47812962 # Total read bandwidth from this memory (bytes/s)
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|
system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
|
||
|
system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
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|
system.physmem.bw_read::cpu0.inst 199389 # Total read bandwidth from this memory (bytes/s)
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|
system.physmem.bw_read::cpu0.data 2926433 # Total read bandwidth from this memory (bytes/s)
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|
system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
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||
|
system.physmem.bw_read::cpu1.inst 30675 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 298522 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.dtb.walker 506 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 90986 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 554903 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51914536 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 199389 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 30675 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 90986 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 321050 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1560756 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 438164 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 83069 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu2.data 734625 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2816613 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1560756 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47812962 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
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||
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system.physmem.bw_total::cpu0.inst 199389 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 3364597 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 30675 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 381591 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.dtb.walker 506 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 90986 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 1289528 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 54731150 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 12619527 # Total number of read requests seen
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system.physmem.writeReqs 508095 # Total number of write requests seen
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system.physmem.cpureqs 56153 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 807649728 # Total number of bytes read from memory
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system.physmem.bytesWritten 32518080 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 103006296 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 3063660 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 2356 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 788374 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 788516 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 788173 # Track reads on a per bank basis
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||
|
system.physmem.perBankRdReqs::3 788282 # Track reads on a per bank basis
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||
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system.physmem.perBankRdReqs::4 788267 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 788268 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 788411 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 789077 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 789904 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 789864 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 789609 # Track reads on a per bank basis
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|
system.physmem.perBankRdReqs::11 789636 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 788668 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 788108 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 788208 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 788160 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 30462 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 31339 # Track writes on a per bank basis
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||
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system.physmem.perBankWrReqs::2 31367 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 31519 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 31434 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 31463 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 31715 # Track writes on a per bank basis
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||
|
system.physmem.perBankWrReqs::7 32144 # Track writes on a per bank basis
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||
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system.physmem.perBankWrReqs::8 32667 # Track writes on a per bank basis
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||
|
system.physmem.perBankWrReqs::9 32642 # Track writes on a per bank basis
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||
|
system.physmem.perBankWrReqs::10 32415 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 32370 # Track writes on a per bank basis
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||
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system.physmem.perBankWrReqs::12 31797 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 31479 # Track writes on a per bank basis
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||
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system.physmem.perBankWrReqs::14 31921 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 31361 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 317403 # Number of times wr buffer was full causing retry
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system.physmem.totGap 2400386249000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 6 # Categorize read packet sizes
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system.physmem.readPktSize::3 12582912 # Categorize read packet sizes
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||
|
system.physmem.readPktSize::4 0 # Categorize read packet sizes
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||
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||
|
system.physmem.readPktSize::6 36609 # Categorize read packet sizes
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||
|
system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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||
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system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||
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system.physmem.writePktSize::2 808310 # categorize write packet sizes
|
||
|
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||
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system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||
|
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||
|
system.physmem.writePktSize::6 17188 # categorize write packet sizes
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||
|
system.physmem.writePktSize::7 0 # categorize write packet sizes
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||
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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||
|
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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||
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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||
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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||
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||
|
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||
|
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||
|
system.physmem.neitherpktsize::6 2356 # categorize neither packet sizes
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||
|
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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||
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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|
system.physmem.rdQLenPdf::0 817282 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 792530 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 787018 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 816081 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::4 2309777 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2310026 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 4565188 # What read queue length does an incoming req see
|
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|
system.physmem.rdQLenPdf::7 24972 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 24597 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::9 24594 # What read queue length does an incoming req see
|
||
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system.physmem.rdQLenPdf::10 24587 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::11 47867 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::12 24582 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::13 47847 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::14 1291 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::15 1284 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||
|
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::0 3518 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::1 3552 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::2 3620 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::3 3760 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::4 3937 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::5 4056 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::6 4161 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::7 4250 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::8 4415 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::9 22096 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::10 22090 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::11 22088 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::12 22084 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::13 22079 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::14 22076 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::15 22070 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::16 22068 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::17 22064 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::18 22061 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::19 22055 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::20 22051 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::21 22047 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::22 22044 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::23 18625 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::24 18585 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::25 18515 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::26 18369 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::27 18188 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::28 18065 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::29 17957 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::30 17859 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::31 17690 # What write queue length does an incoming req see
|
||
|
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||
|
system.physmem.totQLat 234691241923 # Total cycles spent in queuing delays
|
||
|
system.physmem.totMemAccLat 297448055923 # Sum of mem lat for all requests
|
||
|
system.physmem.totBusLat 50478100000 # Total cycles spent in databus access
|
||
|
system.physmem.totBankLat 12278714000 # Total cycles spent in bank access
|
||
|
system.physmem.avgQLat 18597.47 # Average queueing delay per request
|
||
|
system.physmem.avgBankLat 972.99 # Average bank access latency per request
|
||
|
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
||
|
system.physmem.avgMemAccLat 23570.46 # Average memory access latency
|
||
|
system.physmem.avgRdBW 336.32 # Average achieved read bandwidth in MB/s
|
||
|
system.physmem.avgWrBW 13.54 # Average achieved write bandwidth in MB/s
|
||
|
system.physmem.avgConsumedRdBW 42.89 # Average consumed read bandwidth in MB/s
|
||
|
system.physmem.avgConsumedWrBW 1.28 # Average consumed write bandwidth in MB/s
|
||
|
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
||
|
system.physmem.busUtil 2.19 # Data bus utilization in percentage
|
||
|
system.physmem.avgRdQLen 0.12 # Average read queue length over time
|
||
|
system.physmem.avgWrQLen 0.40 # Average write queue length over time
|
||
|
system.physmem.readRowHits 12589945 # Number of row buffer hits during reads
|
||
|
system.physmem.writeRowHits 499132 # Number of row buffer hits during writes
|
||
|
system.physmem.readRowHitRate 99.77 # Row buffer hit rate for reads
|
||
|
system.physmem.writeRowHitRate 98.24 # Row buffer hit rate for writes
|
||
|
system.physmem.avgGap 182850.04 # Average gap between requests
|
||
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||
|
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
|
||
|
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
||
|
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
||
|
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
||
|
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
||
|
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
||
|
system.l2c.replacements 63371 # number of replacements
|
||
|
system.l2c.tagsinuse 50440.930838 # Cycle average of tags in use
|
||
|
system.l2c.total_refs 1764263 # Total number of references to valid blocks.
|
||
|
system.l2c.sampled_refs 128761 # Sample count of references to valid blocks.
|
||
|
system.l2c.avg_refs 13.701843 # Average number of references to valid blocks.
|
||
|
system.l2c.warmup_cycle 2374519462500 # Cycle when the warmup percentage was hit.
|
||
|
system.l2c.occ_blocks::writebacks 36775.045658 # Average occupied blocks per requestor
|
||
|
system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
|
||
|
system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
|
||
|
system.l2c.occ_blocks::cpu0.inst 4782.596749 # Average occupied blocks per requestor
|
||
|
system.l2c.occ_blocks::cpu0.data 3401.388842 # Average occupied blocks per requestor
|
||
|
system.l2c.occ_blocks::cpu1.dtb.walker 0.993264 # Average occupied blocks per requestor
|
||
|
system.l2c.occ_blocks::cpu1.inst 624.225892 # Average occupied blocks per requestor
|
||
|
system.l2c.occ_blocks::cpu1.data 1084.430901 # Average occupied blocks per requestor
|
||
|
system.l2c.occ_blocks::cpu2.dtb.walker 16.710319 # Average occupied blocks per requestor
|
||
|
system.l2c.occ_blocks::cpu2.itb.walker 0.970933 # Average occupied blocks per requestor
|
||
|
system.l2c.occ_blocks::cpu2.inst 2110.368967 # Average occupied blocks per requestor
|
||
|
system.l2c.occ_blocks::cpu2.data 1644.199171 # Average occupied blocks per requestor
|
||
|
system.l2c.occ_percent::writebacks 0.561143 # Average percentage of cache occupancy
|
||
|
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||
|
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
||
|
system.l2c.occ_percent::cpu0.inst 0.072977 # Average percentage of cache occupancy
|
||
|
system.l2c.occ_percent::cpu0.data 0.051901 # Average percentage of cache occupancy
|
||
|
system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
|
||
|
system.l2c.occ_percent::cpu1.inst 0.009525 # Average percentage of cache occupancy
|
||
|
system.l2c.occ_percent::cpu1.data 0.016547 # Average percentage of cache occupancy
|
||
|
system.l2c.occ_percent::cpu2.dtb.walker 0.000255 # Average percentage of cache occupancy
|
||
|
system.l2c.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy
|
||
|
system.l2c.occ_percent::cpu2.inst 0.032202 # Average percentage of cache occupancy
|
||
|
system.l2c.occ_percent::cpu2.data 0.025088 # Average percentage of cache occupancy
|
||
|
system.l2c.occ_percent::total 0.769668 # Average percentage of cache occupancy
|
||
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 8850 # number of ReadReq hits
|
||
|
system.l2c.ReadReq_hits::cpu0.itb.walker 3418 # number of ReadReq hits
|
||
|
system.l2c.ReadReq_hits::cpu0.inst 467065 # number of ReadReq hits
|
||
|
system.l2c.ReadReq_hits::cpu0.data 185990 # number of ReadReq hits
|
||
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 2576 # number of ReadReq hits
|
||
|
system.l2c.ReadReq_hits::cpu1.itb.walker 1139 # number of ReadReq hits
|
||
|
system.l2c.ReadReq_hits::cpu1.inst 127160 # number of ReadReq hits
|
||
|
system.l2c.ReadReq_hits::cpu1.data 58153 # number of ReadReq hits
|
||
|
system.l2c.ReadReq_hits::cpu2.dtb.walker 32653 # number of ReadReq hits
|
||
|
system.l2c.ReadReq_hits::cpu2.itb.walker 4529 # number of ReadReq hits
|
||
|
system.l2c.ReadReq_hits::cpu2.inst 285923 # number of ReadReq hits
|
||
|
system.l2c.ReadReq_hits::cpu2.data 129158 # number of ReadReq hits
|
||
|
system.l2c.ReadReq_hits::total 1306614 # number of ReadReq hits
|
||
|
system.l2c.Writeback_hits::writebacks 597611 # number of Writeback hits
|
||
|
system.l2c.Writeback_hits::total 597611 # number of Writeback hits
|
||
|
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
|
||
|
system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
|
||
|
system.l2c.UpgradeReq_hits::cpu2.data 14 # number of UpgradeReq hits
|
||
|
system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
|
||
|
system.l2c.SCUpgradeReq_hits::cpu2.data 6 # number of SCUpgradeReq hits
|
||
|
system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits
|
||
|
system.l2c.ReadExReq_hits::cpu0.data 62389 # number of ReadExReq hits
|
||
|
system.l2c.ReadExReq_hits::cpu1.data 18579 # number of ReadExReq hits
|
||
|
system.l2c.ReadExReq_hits::cpu2.data 32685 # number of ReadExReq hits
|
||
|
system.l2c.ReadExReq_hits::total 113653 # number of ReadExReq hits
|
||
|
system.l2c.demand_hits::cpu0.dtb.walker 8850 # number of demand (read+write) hits
|
||
|
system.l2c.demand_hits::cpu0.itb.walker 3418 # number of demand (read+write) hits
|
||
|
system.l2c.demand_hits::cpu0.inst 467065 # number of demand (read+write) hits
|
||
|
system.l2c.demand_hits::cpu0.data 248379 # number of demand (read+write) hits
|
||
|
system.l2c.demand_hits::cpu1.dtb.walker 2576 # number of demand (read+write) hits
|
||
|
system.l2c.demand_hits::cpu1.itb.walker 1139 # number of demand (read+write) hits
|
||
|
system.l2c.demand_hits::cpu1.inst 127160 # number of demand (read+write) hits
|
||
|
system.l2c.demand_hits::cpu1.data 76732 # number of demand (read+write) hits
|
||
|
system.l2c.demand_hits::cpu2.dtb.walker 32653 # number of demand (read+write) hits
|
||
|
system.l2c.demand_hits::cpu2.itb.walker 4529 # number of demand (read+write) hits
|
||
|
system.l2c.demand_hits::cpu2.inst 285923 # number of demand (read+write) hits
|
||
|
system.l2c.demand_hits::cpu2.data 161843 # number of demand (read+write) hits
|
||
|
system.l2c.demand_hits::total 1420267 # number of demand (read+write) hits
|
||
|
system.l2c.overall_hits::cpu0.dtb.walker 8850 # number of overall hits
|
||
|
system.l2c.overall_hits::cpu0.itb.walker 3418 # number of overall hits
|
||
|
system.l2c.overall_hits::cpu0.inst 467065 # number of overall hits
|
||
|
system.l2c.overall_hits::cpu0.data 248379 # number of overall hits
|
||
|
system.l2c.overall_hits::cpu1.dtb.walker 2576 # number of overall hits
|
||
|
system.l2c.overall_hits::cpu1.itb.walker 1139 # number of overall hits
|
||
|
system.l2c.overall_hits::cpu1.inst 127160 # number of overall hits
|
||
|
system.l2c.overall_hits::cpu1.data 76732 # number of overall hits
|
||
|
system.l2c.overall_hits::cpu2.dtb.walker 32653 # number of overall hits
|
||
|
system.l2c.overall_hits::cpu2.itb.walker 4529 # number of overall hits
|
||
|
system.l2c.overall_hits::cpu2.inst 285923 # number of overall hits
|
||
|
system.l2c.overall_hits::cpu2.data 161843 # number of overall hits
|
||
|
system.l2c.overall_hits::total 1420267 # number of overall hits
|
||
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
|
||
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
||
|
system.l2c.ReadReq_misses::cpu0.inst 7068 # number of ReadReq misses
|
||
|
system.l2c.ReadReq_misses::cpu0.data 5964 # number of ReadReq misses
|
||
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
|
||
|
system.l2c.ReadReq_misses::cpu1.inst 1151 # number of ReadReq misses
|
||
|
system.l2c.ReadReq_misses::cpu1.data 1562 # number of ReadReq misses
|
||
|
system.l2c.ReadReq_misses::cpu2.dtb.walker 19 # number of ReadReq misses
|
||
|
system.l2c.ReadReq_misses::cpu2.itb.walker 2 # number of ReadReq misses
|
||
|
system.l2c.ReadReq_misses::cpu2.inst 3416 # number of ReadReq misses
|
||
|
system.l2c.ReadReq_misses::cpu2.data 2619 # number of ReadReq misses
|
||
|
system.l2c.ReadReq_misses::total 21805 # number of ReadReq misses
|
||
|
system.l2c.UpgradeReq_misses::cpu0.data 1429 # number of UpgradeReq misses
|
||
|
system.l2c.UpgradeReq_misses::cpu1.data 489 # number of UpgradeReq misses
|
||
|
system.l2c.UpgradeReq_misses::cpu2.data 987 # number of UpgradeReq misses
|
||
|
system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses
|
||
|
system.l2c.ReadExReq_misses::cpu0.data 104629 # number of ReadExReq misses
|
||
|
system.l2c.ReadExReq_misses::cpu1.data 9911 # number of ReadExReq misses
|
||
|
system.l2c.ReadExReq_misses::cpu2.data 18825 # number of ReadExReq misses
|
||
|
system.l2c.ReadExReq_misses::total 133365 # number of ReadExReq misses
|
||
|
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
|
||
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
||
|
system.l2c.demand_misses::cpu0.inst 7068 # number of demand (read+write) misses
|
||
|
system.l2c.demand_misses::cpu0.data 110593 # number of demand (read+write) misses
|
||
|
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
|
||
|
system.l2c.demand_misses::cpu1.inst 1151 # number of demand (read+write) misses
|
||
|
system.l2c.demand_misses::cpu1.data 11473 # number of demand (read+write) misses
|
||
|
system.l2c.demand_misses::cpu2.dtb.walker 19 # number of demand (read+write) misses
|
||
|
system.l2c.demand_misses::cpu2.itb.walker 2 # number of demand (read+write) misses
|
||
|
system.l2c.demand_misses::cpu2.inst 3416 # number of demand (read+write) misses
|
||
|
system.l2c.demand_misses::cpu2.data 21444 # number of demand (read+write) misses
|
||
|
system.l2c.demand_misses::total 155170 # number of demand (read+write) misses
|
||
|
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
|
||
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
||
|
system.l2c.overall_misses::cpu0.inst 7068 # number of overall misses
|
||
|
system.l2c.overall_misses::cpu0.data 110593 # number of overall misses
|
||
|
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
|
||
|
system.l2c.overall_misses::cpu1.inst 1151 # number of overall misses
|
||
|
system.l2c.overall_misses::cpu1.data 11473 # number of overall misses
|
||
|
system.l2c.overall_misses::cpu2.dtb.walker 19 # number of overall misses
|
||
|
system.l2c.overall_misses::cpu2.itb.walker 2 # number of overall misses
|
||
|
system.l2c.overall_misses::cpu2.inst 3416 # number of overall misses
|
||
|
system.l2c.overall_misses::cpu2.data 21444 # number of overall misses
|
||
|
system.l2c.overall_misses::total 155170 # number of overall misses
|
||
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles
|
||
|
system.l2c.ReadReq_miss_latency::cpu1.inst 59181000 # number of ReadReq miss cycles
|
||
|
system.l2c.ReadReq_miss_latency::cpu1.data 81935500 # number of ReadReq miss cycles
|
||
|
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 1348500 # number of ReadReq miss cycles
|
||
|
system.l2c.ReadReq_miss_latency::cpu2.itb.walker 137000 # number of ReadReq miss cycles
|
||
|
system.l2c.ReadReq_miss_latency::cpu2.inst 197768500 # number of ReadReq miss cycles
|
||
|
system.l2c.ReadReq_miss_latency::cpu2.data 150939499 # number of ReadReq miss cycles
|
||
|
system.l2c.ReadReq_miss_latency::total 491378999 # number of ReadReq miss cycles
|
||
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 91500 # number of UpgradeReq miss cycles
|
||
|
system.l2c.UpgradeReq_miss_latency::cpu2.data 137000 # number of UpgradeReq miss cycles
|
||
|
system.l2c.UpgradeReq_miss_latency::total 228500 # number of UpgradeReq miss cycles
|
||
|
system.l2c.ReadExReq_miss_latency::cpu1.data 442251500 # number of ReadExReq miss cycles
|
||
|
system.l2c.ReadExReq_miss_latency::cpu2.data 1015620500 # number of ReadExReq miss cycles
|
||
|
system.l2c.ReadExReq_miss_latency::total 1457872000 # number of ReadExReq miss cycles
|
||
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles
|
||
|
system.l2c.demand_miss_latency::cpu1.inst 59181000 # number of demand (read+write) miss cycles
|
||
|
system.l2c.demand_miss_latency::cpu1.data 524187000 # number of demand (read+write) miss cycles
|
||
|
system.l2c.demand_miss_latency::cpu2.dtb.walker 1348500 # number of demand (read+write) miss cycles
|
||
|
system.l2c.demand_miss_latency::cpu2.itb.walker 137000 # number of demand (read+write) miss cycles
|
||
|
system.l2c.demand_miss_latency::cpu2.inst 197768500 # number of demand (read+write) miss cycles
|
||
|
system.l2c.demand_miss_latency::cpu2.data 1166559999 # number of demand (read+write) miss cycles
|
||
|
system.l2c.demand_miss_latency::total 1949250999 # number of demand (read+write) miss cycles
|
||
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles
|
||
|
system.l2c.overall_miss_latency::cpu1.inst 59181000 # number of overall miss cycles
|
||
|
system.l2c.overall_miss_latency::cpu1.data 524187000 # number of overall miss cycles
|
||
|
system.l2c.overall_miss_latency::cpu2.dtb.walker 1348500 # number of overall miss cycles
|
||
|
system.l2c.overall_miss_latency::cpu2.itb.walker 137000 # number of overall miss cycles
|
||
|
system.l2c.overall_miss_latency::cpu2.inst 197768500 # number of overall miss cycles
|
||
|
system.l2c.overall_miss_latency::cpu2.data 1166559999 # number of overall miss cycles
|
||
|
system.l2c.overall_miss_latency::total 1949250999 # number of overall miss cycles
|
||
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 8851 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 3420 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.ReadReq_accesses::cpu0.inst 474133 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.ReadReq_accesses::cpu0.data 191954 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 2577 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 1139 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.ReadReq_accesses::cpu1.inst 128311 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.ReadReq_accesses::cpu1.data 59715 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.ReadReq_accesses::cpu2.dtb.walker 32672 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.ReadReq_accesses::cpu2.itb.walker 4531 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.ReadReq_accesses::cpu2.inst 289339 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.ReadReq_accesses::cpu2.data 131777 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.ReadReq_accesses::total 1328419 # number of ReadReq accesses(hits+misses)
|
||
|
system.l2c.Writeback_accesses::writebacks 597611 # number of Writeback accesses(hits+misses)
|
||
|
system.l2c.Writeback_accesses::total 597611 # number of Writeback accesses(hits+misses)
|
||
|
system.l2c.UpgradeReq_accesses::cpu0.data 1442 # number of UpgradeReq accesses(hits+misses)
|
||
|
system.l2c.UpgradeReq_accesses::cpu1.data 493 # number of UpgradeReq accesses(hits+misses)
|
||
|
system.l2c.UpgradeReq_accesses::cpu2.data 1001 # number of UpgradeReq accesses(hits+misses)
|
||
|
system.l2c.UpgradeReq_accesses::total 2936 # number of UpgradeReq accesses(hits+misses)
|
||
|
system.l2c.SCUpgradeReq_accesses::cpu2.data 6 # number of SCUpgradeReq accesses(hits+misses)
|
||
|
system.l2c.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses)
|
||
|
system.l2c.ReadExReq_accesses::cpu0.data 167018 # number of ReadExReq accesses(hits+misses)
|
||
|
system.l2c.ReadExReq_accesses::cpu1.data 28490 # number of ReadExReq accesses(hits+misses)
|
||
|
system.l2c.ReadExReq_accesses::cpu2.data 51510 # number of ReadExReq accesses(hits+misses)
|
||
|
system.l2c.ReadExReq_accesses::total 247018 # number of ReadExReq accesses(hits+misses)
|
||
|
system.l2c.demand_accesses::cpu0.dtb.walker 8851 # number of demand (read+write) accesses
|
||
|
system.l2c.demand_accesses::cpu0.itb.walker 3420 # number of demand (read+write) accesses
|
||
|
system.l2c.demand_accesses::cpu0.inst 474133 # number of demand (read+write) accesses
|
||
|
system.l2c.demand_accesses::cpu0.data 358972 # number of demand (read+write) accesses
|
||
|
system.l2c.demand_accesses::cpu1.dtb.walker 2577 # number of demand (read+write) accesses
|
||
|
system.l2c.demand_accesses::cpu1.itb.walker 1139 # number of demand (read+write) accesses
|
||
|
system.l2c.demand_accesses::cpu1.inst 128311 # number of demand (read+write) accesses
|
||
|
system.l2c.demand_accesses::cpu1.data 88205 # number of demand (read+write) accesses
|
||
|
system.l2c.demand_accesses::cpu2.dtb.walker 32672 # number of demand (read+write) accesses
|
||
|
system.l2c.demand_accesses::cpu2.itb.walker 4531 # number of demand (read+write) accesses
|
||
|
system.l2c.demand_accesses::cpu2.inst 289339 # number of demand (read+write) accesses
|
||
|
system.l2c.demand_accesses::cpu2.data 183287 # number of demand (read+write) accesses
|
||
|
system.l2c.demand_accesses::total 1575437 # number of demand (read+write) accesses
|
||
|
system.l2c.overall_accesses::cpu0.dtb.walker 8851 # number of overall (read+write) accesses
|
||
|
system.l2c.overall_accesses::cpu0.itb.walker 3420 # number of overall (read+write) accesses
|
||
|
system.l2c.overall_accesses::cpu0.inst 474133 # number of overall (read+write) accesses
|
||
|
system.l2c.overall_accesses::cpu0.data 358972 # number of overall (read+write) accesses
|
||
|
system.l2c.overall_accesses::cpu1.dtb.walker 2577 # number of overall (read+write) accesses
|
||
|
system.l2c.overall_accesses::cpu1.itb.walker 1139 # number of overall (read+write) accesses
|
||
|
system.l2c.overall_accesses::cpu1.inst 128311 # number of overall (read+write) accesses
|
||
|
system.l2c.overall_accesses::cpu1.data 88205 # number of overall (read+write) accesses
|
||
|
system.l2c.overall_accesses::cpu2.dtb.walker 32672 # number of overall (read+write) accesses
|
||
|
system.l2c.overall_accesses::cpu2.itb.walker 4531 # number of overall (read+write) accesses
|
||
|
system.l2c.overall_accesses::cpu2.inst 289339 # number of overall (read+write) accesses
|
||
|
system.l2c.overall_accesses::cpu2.data 183287 # number of overall (read+write) accesses
|
||
|
system.l2c.overall_accesses::total 1575437 # number of overall (read+write) accesses
|
||
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000585 # miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014907 # miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.031070 # miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000388 # miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.008970 # miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.026158 # miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000582 # miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000441 # miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_miss_rate::cpu2.inst 0.011806 # miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_miss_rate::cpu2.data 0.019874 # miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses
|
||
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990985 # miss rate for UpgradeReq accesses
|
||
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991886 # miss rate for UpgradeReq accesses
|
||
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.986014 # miss rate for UpgradeReq accesses
|
||
|
system.l2c.UpgradeReq_miss_rate::total 0.989441 # miss rate for UpgradeReq accesses
|
||
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.626453 # miss rate for ReadExReq accesses
|
||
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.347876 # miss rate for ReadExReq accesses
|
||
|
system.l2c.ReadExReq_miss_rate::cpu2.data 0.365463 # miss rate for ReadExReq accesses
|
||
|
system.l2c.ReadExReq_miss_rate::total 0.539900 # miss rate for ReadExReq accesses
|
||
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for demand accesses
|
||
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000585 # miss rate for demand accesses
|
||
|
system.l2c.demand_miss_rate::cpu0.inst 0.014907 # miss rate for demand accesses
|
||
|
system.l2c.demand_miss_rate::cpu0.data 0.308083 # miss rate for demand accesses
|
||
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000388 # miss rate for demand accesses
|
||
|
system.l2c.demand_miss_rate::cpu1.inst 0.008970 # miss rate for demand accesses
|
||
|
system.l2c.demand_miss_rate::cpu1.data 0.130072 # miss rate for demand accesses
|
||
|
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000582 # miss rate for demand accesses
|
||
|
system.l2c.demand_miss_rate::cpu2.itb.walker 0.000441 # miss rate for demand accesses
|
||
|
system.l2c.demand_miss_rate::cpu2.inst 0.011806 # miss rate for demand accesses
|
||
|
system.l2c.demand_miss_rate::cpu2.data 0.116997 # miss rate for demand accesses
|
||
|
system.l2c.demand_miss_rate::total 0.098493 # miss rate for demand accesses
|
||
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for overall accesses
|
||
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000585 # miss rate for overall accesses
|
||
|
system.l2c.overall_miss_rate::cpu0.inst 0.014907 # miss rate for overall accesses
|
||
|
system.l2c.overall_miss_rate::cpu0.data 0.308083 # miss rate for overall accesses
|
||
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000388 # miss rate for overall accesses
|
||
|
system.l2c.overall_miss_rate::cpu1.inst 0.008970 # miss rate for overall accesses
|
||
|
system.l2c.overall_miss_rate::cpu1.data 0.130072 # miss rate for overall accesses
|
||
|
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000582 # miss rate for overall accesses
|
||
|
system.l2c.overall_miss_rate::cpu2.itb.walker 0.000441 # miss rate for overall accesses
|
||
|
system.l2c.overall_miss_rate::cpu2.inst 0.011806 # miss rate for overall accesses
|
||
|
system.l2c.overall_miss_rate::cpu2.data 0.116997 # miss rate for overall accesses
|
||
|
system.l2c.overall_miss_rate::total 0.098493 # miss rate for overall accesses
|
||
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69000 # average ReadReq miss latency
|
||
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51417.028671 # average ReadReq miss latency
|
||
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52455.505762 # average ReadReq miss latency
|
||
|
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 70973.684211 # average ReadReq miss latency
|
||
|
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 68500 # average ReadReq miss latency
|
||
|
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 57894.759953 # average ReadReq miss latency
|
||
|
system.l2c.ReadReq_avg_miss_latency::cpu2.data 57632.492936 # average ReadReq miss latency
|
||
|
system.l2c.ReadReq_avg_miss_latency::total 22535.152442 # average ReadReq miss latency
|
||
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 187.116564 # average UpgradeReq miss latency
|
||
|
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 138.804458 # average UpgradeReq miss latency
|
||
|
system.l2c.UpgradeReq_avg_miss_latency::total 78.657487 # average UpgradeReq miss latency
|
||
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44622.288366 # average ReadExReq miss latency
|
||
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53950.624170 # average ReadExReq miss latency
|
||
|
system.l2c.ReadExReq_avg_miss_latency::total 10931.443782 # average ReadExReq miss latency
|
||
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency
|
||
|
system.l2c.demand_avg_miss_latency::cpu1.inst 51417.028671 # average overall miss latency
|
||
|
system.l2c.demand_avg_miss_latency::cpu1.data 45688.747494 # average overall miss latency
|
||
|
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 70973.684211 # average overall miss latency
|
||
|
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 68500 # average overall miss latency
|
||
|
system.l2c.demand_avg_miss_latency::cpu2.inst 57894.759953 # average overall miss latency
|
||
|
system.l2c.demand_avg_miss_latency::cpu2.data 54400.298405 # average overall miss latency
|
||
|
system.l2c.demand_avg_miss_latency::total 12562.035181 # average overall miss latency
|
||
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency
|
||
|
system.l2c.overall_avg_miss_latency::cpu1.inst 51417.028671 # average overall miss latency
|
||
|
system.l2c.overall_avg_miss_latency::cpu1.data 45688.747494 # average overall miss latency
|
||
|
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 70973.684211 # average overall miss latency
|
||
|
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 68500 # average overall miss latency
|
||
|
system.l2c.overall_avg_miss_latency::cpu2.inst 57894.759953 # average overall miss latency
|
||
|
system.l2c.overall_avg_miss_latency::cpu2.data 54400.298405 # average overall miss latency
|
||
|
system.l2c.overall_avg_miss_latency::total 12562.035181 # average overall miss latency
|
||
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||
|
system.l2c.fast_writes 0 # number of fast writes performed
|
||
|
system.l2c.cache_copies 0 # number of cache copies performed
|
||
|
system.l2c.writebacks::writebacks 58563 # number of writebacks
|
||
|
system.l2c.writebacks::total 58563 # number of writebacks
|
||
|
system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits
|
||
|
system.l2c.ReadReq_mshr_hits::cpu2.data 15 # number of ReadReq MSHR hits
|
||
|
system.l2c.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
|
||
|
system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits
|
||
|
system.l2c.demand_mshr_hits::cpu2.data 15 # number of demand (read+write) MSHR hits
|
||
|
system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
|
||
|
system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits
|
||
|
system.l2c.overall_mshr_hits::cpu2.data 15 # number of overall MSHR hits
|
||
|
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|
||
|
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|
||
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 1151 # number of ReadReq MSHR misses
|
||
|
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|
||
|
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|
||
|
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|
||
|
system.l2c.ReadReq_mshr_misses::cpu2.inst 3414 # number of ReadReq MSHR misses
|
||
|
system.l2c.ReadReq_mshr_misses::cpu2.data 2604 # number of ReadReq MSHR misses
|
||
|
system.l2c.ReadReq_mshr_misses::total 8753 # number of ReadReq MSHR misses
|
||
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 489 # number of UpgradeReq MSHR misses
|
||
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 987 # number of UpgradeReq MSHR misses
|
||
|
system.l2c.UpgradeReq_mshr_misses::total 1476 # number of UpgradeReq MSHR misses
|
||
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 9911 # number of ReadExReq MSHR misses
|
||
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 18825 # number of ReadExReq MSHR misses
|
||
|
system.l2c.ReadExReq_mshr_misses::total 28736 # number of ReadExReq MSHR misses
|
||
|
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|
||
|
system.l2c.demand_mshr_misses::cpu1.inst 1151 # number of demand (read+write) MSHR misses
|
||
|
system.l2c.demand_mshr_misses::cpu1.data 11473 # number of demand (read+write) MSHR misses
|
||
|
system.l2c.demand_mshr_misses::cpu2.dtb.walker 19 # number of demand (read+write) MSHR misses
|
||
|
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|
||
|
system.l2c.demand_mshr_misses::cpu2.inst 3414 # number of demand (read+write) MSHR misses
|
||
|
system.l2c.demand_mshr_misses::cpu2.data 21429 # number of demand (read+write) MSHR misses
|
||
|
system.l2c.demand_mshr_misses::total 37489 # number of demand (read+write) MSHR misses
|
||
|
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|
||
|
system.l2c.overall_mshr_misses::cpu1.inst 1151 # number of overall MSHR misses
|
||
|
system.l2c.overall_mshr_misses::cpu1.data 11473 # number of overall MSHR misses
|
||
|
system.l2c.overall_mshr_misses::cpu2.dtb.walker 19 # number of overall MSHR misses
|
||
|
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|
||
|
system.l2c.overall_mshr_misses::cpu2.inst 3414 # number of overall MSHR misses
|
||
|
system.l2c.overall_mshr_misses::cpu2.data 21429 # number of overall MSHR misses
|
||
|
system.l2c.overall_mshr_misses::total 37489 # number of overall MSHR misses
|
||
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56002 # number of ReadReq MSHR miss cycles
|
||
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 44565780 # number of ReadReq MSHR miss cycles
|
||
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 61910606 # number of ReadReq MSHR miss cycles
|
||
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1106535 # number of ReadReq MSHR miss cycles
|
||
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 112004 # number of ReadReq MSHR miss cycles
|
||
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 154485385 # number of ReadReq MSHR miss cycles
|
||
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 117079807 # number of ReadReq MSHR miss cycles
|
||
|
system.l2c.ReadReq_mshr_miss_latency::total 379316119 # number of ReadReq MSHR miss cycles
|
||
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4947956 # number of UpgradeReq MSHR miss cycles
|
||
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9870987 # number of UpgradeReq MSHR miss cycles
|
||
|
system.l2c.UpgradeReq_mshr_miss_latency::total 14818943 # number of UpgradeReq MSHR miss cycles
|
||
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 315063958 # number of ReadExReq MSHR miss cycles
|
||
|
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|
||
|
system.l2c.ReadExReq_mshr_miss_latency::total 1095777176 # number of ReadExReq MSHR miss cycles
|
||
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56002 # number of demand (read+write) MSHR miss cycles
|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
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|
||
|
system.l2c.demand_mshr_miss_latency::cpu2.data 897793025 # number of demand (read+write) MSHR miss cycles
|
||
|
system.l2c.demand_mshr_miss_latency::total 1475093295 # number of demand (read+write) MSHR miss cycles
|
||
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56002 # number of overall MSHR miss cycles
|
||
|
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|
||
|
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|
||
|
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|
||
|
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 112004 # number of overall MSHR miss cycles
|
||
|
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|
||
|
system.l2c.overall_mshr_miss_latency::cpu2.data 897793025 # number of overall MSHR miss cycles
|
||
|
system.l2c.overall_mshr_miss_latency::total 1475093295 # number of overall MSHR miss cycles
|
||
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25233133000 # number of ReadReq MSHR uncacheable cycles
|
||
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26572368004 # number of ReadReq MSHR uncacheable cycles
|
||
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 51805501004 # number of ReadReq MSHR uncacheable cycles
|
||
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 640106868 # number of WriteReq MSHR uncacheable cycles
|
||
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 7144945536 # number of WriteReq MSHR uncacheable cycles
|
||
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 7785052404 # number of WriteReq MSHR uncacheable cycles
|
||
|
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76004 # number of LoadLockedReq MSHR uncacheable cycles
|
||
|
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76004 # number of LoadLockedReq MSHR uncacheable cycles
|
||
|
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles
|
||
|
system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles
|
||
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25873239868 # number of overall MSHR uncacheable cycles
|
||
|
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 33717313540 # number of overall MSHR uncacheable cycles
|
||
|
system.l2c.overall_mshr_uncacheable_latency::total 59590553408 # number of overall MSHR uncacheable cycles
|
||
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000388 # mshr miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008970 # mshr miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026158 # mshr miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000582 # mshr miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000441 # mshr miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011799 # mshr miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.019761 # mshr miss rate for ReadReq accesses
|
||
|
system.l2c.ReadReq_mshr_miss_rate::total 0.006589 # mshr miss rate for ReadReq accesses
|
||
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991886 # mshr miss rate for UpgradeReq accesses
|
||
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.986014 # mshr miss rate for UpgradeReq accesses
|
||
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.502725 # mshr miss rate for UpgradeReq accesses
|
||
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.347876 # mshr miss rate for ReadExReq accesses
|
||
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365463 # mshr miss rate for ReadExReq accesses
|
||
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.116332 # mshr miss rate for ReadExReq accesses
|
||
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000388 # mshr miss rate for demand accesses
|
||
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008970 # mshr miss rate for demand accesses
|
||
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.130072 # mshr miss rate for demand accesses
|
||
|
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000582 # mshr miss rate for demand accesses
|
||
|
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000441 # mshr miss rate for demand accesses
|
||
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011799 # mshr miss rate for demand accesses
|
||
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.116915 # mshr miss rate for demand accesses
|
||
|
system.l2c.demand_mshr_miss_rate::total 0.023796 # mshr miss rate for demand accesses
|
||
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000388 # mshr miss rate for overall accesses
|
||
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008970 # mshr miss rate for overall accesses
|
||
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.130072 # mshr miss rate for overall accesses
|
||
|
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000582 # mshr miss rate for overall accesses
|
||
|
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000441 # mshr miss rate for overall accesses
|
||
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011799 # mshr miss rate for overall accesses
|
||
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.116915 # mshr miss rate for overall accesses
|
||
|
system.l2c.overall_mshr_miss_rate::total 0.023796 # mshr miss rate for overall accesses
|
||
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average ReadReq mshr miss latency
|
||
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38719.183319 # average ReadReq mshr miss latency
|
||
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 39635.471191 # average ReadReq mshr miss latency
|
||
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211 # average ReadReq mshr miss latency
|
||
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 56002 # average ReadReq mshr miss latency
|
||
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 45250.552138 # average ReadReq mshr miss latency
|
||
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 44961.523425 # average ReadReq mshr miss latency
|
||
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 43335.555695 # average ReadReq mshr miss latency
|
||
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10118.519427 # average UpgradeReq mshr miss latency
|
||
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
|
||
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10039.934282 # average UpgradeReq mshr miss latency
|
||
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 31789.320755 # average ReadExReq mshr miss latency
|
||
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41472.149695 # average ReadExReq mshr miss latency
|
||
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 38132.557628 # average ReadExReq mshr miss latency
|
||
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency
|
||
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38719.183319 # average overall mshr miss latency
|
||
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 32857.540661 # average overall mshr miss latency
|
||
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211 # average overall mshr miss latency
|
||
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 56002 # average overall mshr miss latency
|
||
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 45250.552138 # average overall mshr miss latency
|
||
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41896.169910 # average overall mshr miss latency
|
||
|
system.l2c.demand_avg_mshr_miss_latency::total 39347.363093 # average overall mshr miss latency
|
||
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency
|
||
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38719.183319 # average overall mshr miss latency
|
||
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 32857.540661 # average overall mshr miss latency
|
||
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211 # average overall mshr miss latency
|
||
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 56002 # average overall mshr miss latency
|
||
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 45250.552138 # average overall mshr miss latency
|
||
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41896.169910 # average overall mshr miss latency
|
||
|
system.l2c.overall_avg_mshr_miss_latency::total 39347.363093 # average overall mshr miss latency
|
||
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
||
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
||
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
||
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
||
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||
|
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
|
||
|
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
|
||
|
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
|
||
|
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
|
||
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
||
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
||
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
||
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
||
|
system.cpu0.dtb.read_hits 7902224 # DTB read hits
|
||
|
system.cpu0.dtb.read_misses 6242 # DTB read misses
|
||
|
system.cpu0.dtb.write_hits 6537817 # DTB write hits
|
||
|
system.cpu0.dtb.write_misses 1923 # DTB write misses
|
||
|
system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed
|
||
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||
|
system.cpu0.dtb.flush_tlb_mva_asid 688 # Number of times TLB was flushed by MVA & ASID
|
||
|
system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
|
||
|
system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB
|
||
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||
|
system.cpu0.dtb.prefetch_faults 113 # Number of TLB faults due to prefetch
|
||
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||
|
system.cpu0.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions
|
||
|
system.cpu0.dtb.read_accesses 7908466 # DTB read accesses
|
||
|
system.cpu0.dtb.write_accesses 6539740 # DTB write accesses
|
||
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
||
|
system.cpu0.dtb.hits 14440041 # DTB hits
|
||
|
system.cpu0.dtb.misses 8165 # DTB misses
|
||
|
system.cpu0.dtb.accesses 14448206 # DTB accesses
|
||
|
system.cpu0.itb.inst_hits 31853127 # ITB inst hits
|
||
|
system.cpu0.itb.inst_misses 3518 # ITB inst misses
|
||
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
||
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
||
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
||
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
||
|
system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed
|
||
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||
|
system.cpu0.itb.flush_tlb_mva_asid 688 # Number of times TLB was flushed by MVA & ASID
|
||
|
system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
|
||
|
system.cpu0.itb.flush_entries 2622 # Number of entries that have been flushed from TLB
|
||
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
||
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
||
|
system.cpu0.itb.inst_accesses 31856645 # ITB inst accesses
|
||
|
system.cpu0.itb.hits 31853127 # DTB hits
|
||
|
system.cpu0.itb.misses 3518 # DTB misses
|
||
|
system.cpu0.itb.accesses 31856645 # DTB accesses
|
||
|
system.cpu0.numCycles 112931028 # number of cpu cycles simulated
|
||
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||
|
system.cpu0.committedInsts 31362077 # Number of instructions committed
|
||
|
system.cpu0.committedOps 41448320 # Number of ops (including micro ops) committed
|
||
|
system.cpu0.num_int_alu_accesses 36567470 # Number of integer alu accesses
|
||
|
system.cpu0.num_fp_alu_accesses 5105 # Number of float alu accesses
|
||
|
system.cpu0.num_func_calls 1216492 # number of times a function call or return occured
|
||
|
system.cpu0.num_conditional_control_insts 4268853 # number of instructions that are conditional controls
|
||
|
system.cpu0.num_int_insts 36567470 # number of integer instructions
|
||
|
system.cpu0.num_fp_insts 5105 # number of float instructions
|
||
|
system.cpu0.num_int_register_reads 186633277 # number of times the integer registers were read
|
||
|
system.cpu0.num_int_register_writes 38778240 # number of times the integer registers were written
|
||
|
system.cpu0.num_fp_register_reads 3615 # number of times the floating registers were read
|
||
|
system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written
|
||
|
system.cpu0.num_mem_refs 15097186 # number of memory refs
|
||
|
system.cpu0.num_load_insts 8269911 # Number of load instructions
|
||
|
system.cpu0.num_store_insts 6827275 # Number of store instructions
|
||
|
system.cpu0.num_idle_cycles 13401980962.617596 # Number of idle cycles
|
||
|
system.cpu0.num_busy_cycles -13289049934.617596 # Number of busy cycles
|
||
|
system.cpu0.not_idle_fraction -117.674037 # Percentage of non-idle cycles
|
||
|
system.cpu0.idle_fraction 118.674037 # Percentage of idle cycles
|
||
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||
|
system.cpu0.kern.inst.quiesce 84468 # number of quiesce instructions executed
|
||
|
system.cpu0.icache.replacements 892780 # number of replacements
|
||
|
system.cpu0.icache.tagsinuse 511.591234 # Cycle average of tags in use
|
||
|
system.cpu0.icache.total_refs 43441886 # Total number of references to valid blocks.
|
||
|
system.cpu0.icache.sampled_refs 893292 # Sample count of references to valid blocks.
|
||
|
system.cpu0.icache.avg_refs 48.631227 # Average number of references to valid blocks.
|
||
|
system.cpu0.icache.warmup_cycle 8001805000 # Cycle when the warmup percentage was hit.
|
||
|
system.cpu0.icache.occ_blocks::cpu0.inst 491.376976 # Average occupied blocks per requestor
|
||
|
system.cpu0.icache.occ_blocks::cpu1.inst 7.109245 # Average occupied blocks per requestor
|
||
|
system.cpu0.icache.occ_blocks::cpu2.inst 13.105014 # Average occupied blocks per requestor
|
||
|
system.cpu0.icache.occ_percent::cpu0.inst 0.959721 # Average percentage of cache occupancy
|
||
|
system.cpu0.icache.occ_percent::cpu1.inst 0.013885 # Average percentage of cache occupancy
|
||
|
system.cpu0.icache.occ_percent::cpu2.inst 0.025596 # Average percentage of cache occupancy
|
||
|
system.cpu0.icache.occ_percent::total 0.999202 # Average percentage of cache occupancy
|
||
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 31380980 # number of ReadReq hits
|
||
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 8436238 # number of ReadReq hits
|
||
|
system.cpu0.icache.ReadReq_hits::cpu2.inst 3624668 # number of ReadReq hits
|
||
|
system.cpu0.icache.ReadReq_hits::total 43441886 # number of ReadReq hits
|
||
|
system.cpu0.icache.demand_hits::cpu0.inst 31380980 # number of demand (read+write) hits
|
||
|
system.cpu0.icache.demand_hits::cpu1.inst 8436238 # number of demand (read+write) hits
|
||
|
system.cpu0.icache.demand_hits::cpu2.inst 3624668 # number of demand (read+write) hits
|
||
|
system.cpu0.icache.demand_hits::total 43441886 # number of demand (read+write) hits
|
||
|
system.cpu0.icache.overall_hits::cpu0.inst 31380980 # number of overall hits
|
||
|
system.cpu0.icache.overall_hits::cpu1.inst 8436238 # number of overall hits
|
||
|
system.cpu0.icache.overall_hits::cpu2.inst 3624668 # number of overall hits
|
||
|
system.cpu0.icache.overall_hits::total 43441886 # number of overall hits
|
||
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 474853 # number of ReadReq misses
|
||
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 128587 # number of ReadReq misses
|
||
|
system.cpu0.icache.ReadReq_misses::cpu2.inst 314740 # number of ReadReq misses
|
||
|
system.cpu0.icache.ReadReq_misses::total 918180 # number of ReadReq misses
|
||
|
system.cpu0.icache.demand_misses::cpu0.inst 474853 # number of demand (read+write) misses
|
||
|
system.cpu0.icache.demand_misses::cpu1.inst 128587 # number of demand (read+write) misses
|
||
|
system.cpu0.icache.demand_misses::cpu2.inst 314740 # number of demand (read+write) misses
|
||
|
system.cpu0.icache.demand_misses::total 918180 # number of demand (read+write) misses
|
||
|
system.cpu0.icache.overall_misses::cpu0.inst 474853 # number of overall misses
|
||
|
system.cpu0.icache.overall_misses::cpu1.inst 128587 # number of overall misses
|
||
|
system.cpu0.icache.overall_misses::cpu2.inst 314740 # number of overall misses
|
||
|
system.cpu0.icache.overall_misses::total 918180 # number of overall misses
|
||
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1722310000 # number of ReadReq miss cycles
|
||
|
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4209726988 # number of ReadReq miss cycles
|
||
|
system.cpu0.icache.ReadReq_miss_latency::total 5932036988 # number of ReadReq miss cycles
|
||
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 1722310000 # number of demand (read+write) miss cycles
|
||
|
system.cpu0.icache.demand_miss_latency::cpu2.inst 4209726988 # number of demand (read+write) miss cycles
|
||
|
system.cpu0.icache.demand_miss_latency::total 5932036988 # number of demand (read+write) miss cycles
|
||
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 1722310000 # number of overall miss cycles
|
||
|
system.cpu0.icache.overall_miss_latency::cpu2.inst 4209726988 # number of overall miss cycles
|
||
|
system.cpu0.icache.overall_miss_latency::total 5932036988 # number of overall miss cycles
|
||
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 31855833 # number of ReadReq accesses(hits+misses)
|
||
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 8564825 # number of ReadReq accesses(hits+misses)
|
||
|
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3939408 # number of ReadReq accesses(hits+misses)
|
||
|
system.cpu0.icache.ReadReq_accesses::total 44360066 # number of ReadReq accesses(hits+misses)
|
||
|
system.cpu0.icache.demand_accesses::cpu0.inst 31855833 # number of demand (read+write) accesses
|
||
|
system.cpu0.icache.demand_accesses::cpu1.inst 8564825 # number of demand (read+write) accesses
|
||
|
system.cpu0.icache.demand_accesses::cpu2.inst 3939408 # number of demand (read+write) accesses
|
||
|
system.cpu0.icache.demand_accesses::total 44360066 # number of demand (read+write) accesses
|
||
|
system.cpu0.icache.overall_accesses::cpu0.inst 31855833 # number of overall (read+write) accesses
|
||
|
system.cpu0.icache.overall_accesses::cpu1.inst 8564825 # number of overall (read+write) accesses
|
||
|
system.cpu0.icache.overall_accesses::cpu2.inst 3939408 # number of overall (read+write) accesses
|
||
|
system.cpu0.icache.overall_accesses::total 44360066 # number of overall (read+write) accesses
|
||
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014906 # miss rate for ReadReq accesses
|
||
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015013 # miss rate for ReadReq accesses
|
||
|
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.079895 # miss rate for ReadReq accesses
|
||
|
system.cpu0.icache.ReadReq_miss_rate::total 0.020698 # miss rate for ReadReq accesses
|
||
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014906 # miss rate for demand accesses
|
||
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015013 # miss rate for demand accesses
|
||
|
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.079895 # miss rate for demand accesses
|
||
|
system.cpu0.icache.demand_miss_rate::total 0.020698 # miss rate for demand accesses
|
||
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014906 # miss rate for overall accesses
|
||
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015013 # miss rate for overall accesses
|
||
|
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.079895 # miss rate for overall accesses
|
||
|
system.cpu0.icache.overall_miss_rate::total 0.020698 # miss rate for overall accesses
|
||
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13394.122267 # average ReadReq miss latency
|
||
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13375.252551 # average ReadReq miss latency
|
||
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 6460.647137 # average ReadReq miss latency
|
||
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13394.122267 # average overall miss latency
|
||
|
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13375.252551 # average overall miss latency
|
||
|
system.cpu0.icache.demand_avg_miss_latency::total 6460.647137 # average overall miss latency
|
||
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13394.122267 # average overall miss latency
|
||
|
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13375.252551 # average overall miss latency
|
||
|
system.cpu0.icache.overall_avg_miss_latency::total 6460.647137 # average overall miss latency
|
||
|
system.cpu0.icache.blocked_cycles::no_mshrs 3469 # number of cycles access was blocked
|
||
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||
|
system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked
|
||
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.394191 # average number of cycles each access was blocked
|
||
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||
|
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24876 # number of ReadReq MSHR hits
|
||
|
system.cpu0.icache.ReadReq_mshr_hits::total 24876 # number of ReadReq MSHR hits
|
||
|
system.cpu0.icache.demand_mshr_hits::cpu2.inst 24876 # number of demand (read+write) MSHR hits
|
||
|
system.cpu0.icache.demand_mshr_hits::total 24876 # number of demand (read+write) MSHR hits
|
||
|
system.cpu0.icache.overall_mshr_hits::cpu2.inst 24876 # number of overall MSHR hits
|
||
|
system.cpu0.icache.overall_mshr_hits::total 24876 # number of overall MSHR hits
|
||
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128587 # number of ReadReq MSHR misses
|
||
|
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 289864 # number of ReadReq MSHR misses
|
||
|
system.cpu0.icache.ReadReq_mshr_misses::total 418451 # number of ReadReq MSHR misses
|
||
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 128587 # number of demand (read+write) MSHR misses
|
||
|
system.cpu0.icache.demand_mshr_misses::cpu2.inst 289864 # number of demand (read+write) MSHR misses
|
||
|
system.cpu0.icache.demand_mshr_misses::total 418451 # number of demand (read+write) MSHR misses
|
||
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 128587 # number of overall MSHR misses
|
||
|
system.cpu0.icache.overall_mshr_misses::cpu2.inst 289864 # number of overall MSHR misses
|
||
|
system.cpu0.icache.overall_mshr_misses::total 418451 # number of overall MSHR misses
|
||
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1465136000 # number of ReadReq MSHR miss cycles
|
||
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3427061488 # number of ReadReq MSHR miss cycles
|
||
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4892197488 # number of ReadReq MSHR miss cycles
|
||
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1465136000 # number of demand (read+write) MSHR miss cycles
|
||
|
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3427061488 # number of demand (read+write) MSHR miss cycles
|
||
|
system.cpu0.icache.demand_mshr_miss_latency::total 4892197488 # number of demand (read+write) MSHR miss cycles
|
||
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1465136000 # number of overall MSHR miss cycles
|
||
|
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3427061488 # number of overall MSHR miss cycles
|
||
|
system.cpu0.icache.overall_mshr_miss_latency::total 4892197488 # number of overall MSHR miss cycles
|
||
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015013 # mshr miss rate for ReadReq accesses
|
||
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.073581 # mshr miss rate for ReadReq accesses
|
||
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009433 # mshr miss rate for ReadReq accesses
|
||
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015013 # mshr miss rate for demand accesses
|
||
|
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.073581 # mshr miss rate for demand accesses
|
||
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.009433 # mshr miss rate for demand accesses
|
||
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015013 # mshr miss rate for overall accesses
|
||
|
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.073581 # mshr miss rate for overall accesses
|
||
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.009433 # mshr miss rate for overall accesses
|
||
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11394.122267 # average ReadReq mshr miss latency
|
||
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11822.997985 # average ReadReq mshr miss latency
|
||
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11691.207544 # average ReadReq mshr miss latency
|
||
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11394.122267 # average overall mshr miss latency
|
||
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11822.997985 # average overall mshr miss latency
|
||
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11691.207544 # average overall mshr miss latency
|
||
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11394.122267 # average overall mshr miss latency
|
||
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11822.997985 # average overall mshr miss latency
|
||
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11691.207544 # average overall mshr miss latency
|
||
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||
|
system.cpu0.dcache.replacements 629952 # number of replacements
|
||
|
system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use
|
||
|
system.cpu0.dcache.total_refs 23322161 # Total number of references to valid blocks.
|
||
|
system.cpu0.dcache.sampled_refs 630464 # Sample count of references to valid blocks.
|
||
|
system.cpu0.dcache.avg_refs 36.992058 # Average number of references to valid blocks.
|
||
|
system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
||
|
system.cpu0.dcache.occ_blocks::cpu0.data 497.280136 # Average occupied blocks per requestor
|
||
|
system.cpu0.dcache.occ_blocks::cpu1.data 8.191597 # Average occupied blocks per requestor
|
||
|
system.cpu0.dcache.occ_blocks::cpu2.data 6.525382 # Average occupied blocks per requestor
|
||
|
system.cpu0.dcache.occ_percent::cpu0.data 0.971250 # Average percentage of cache occupancy
|
||
|
system.cpu0.dcache.occ_percent::cpu1.data 0.015999 # Average percentage of cache occupancy
|
||
|
system.cpu0.dcache.occ_percent::cpu2.data 0.012745 # Average percentage of cache occupancy
|
||
|
system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6763167 # number of ReadReq hits
|
||
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 1877822 # number of ReadReq hits
|
||
|
system.cpu0.dcache.ReadReq_hits::cpu2.data 4718068 # number of ReadReq hits
|
||
|
system.cpu0.dcache.ReadReq_hits::total 13359057 # number of ReadReq hits
|
||
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 5963557 # number of WriteReq hits
|
||
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 1365617 # number of WriteReq hits
|
||
|
system.cpu0.dcache.WriteReq_hits::cpu2.data 2102817 # number of WriteReq hits
|
||
|
system.cpu0.dcache.WriteReq_hits::total 9431991 # number of WriteReq hits
|
||
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135570 # number of LoadLockedReq hits
|
||
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 32797 # number of LoadLockedReq hits
|
||
|
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 91307 # number of LoadLockedReq hits
|
||
|
system.cpu0.dcache.LoadLockedReq_hits::total 259674 # number of LoadLockedReq hits
|
||
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142092 # number of StoreCondReq hits
|
||
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34425 # number of StoreCondReq hits
|
||
|
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 91924 # number of StoreCondReq hits
|
||
|
system.cpu0.dcache.StoreCondReq_hits::total 268441 # number of StoreCondReq hits
|
||
|
system.cpu0.dcache.demand_hits::cpu0.data 12726724 # number of demand (read+write) hits
|
||
|
system.cpu0.dcache.demand_hits::cpu1.data 3243439 # number of demand (read+write) hits
|
||
|
system.cpu0.dcache.demand_hits::cpu2.data 6820885 # number of demand (read+write) hits
|
||
|
system.cpu0.dcache.demand_hits::total 22791048 # number of demand (read+write) hits
|
||
|
system.cpu0.dcache.overall_hits::cpu0.data 12726724 # number of overall hits
|
||
|
system.cpu0.dcache.overall_hits::cpu1.data 3243439 # number of overall hits
|
||
|
system.cpu0.dcache.overall_hits::cpu2.data 6820885 # number of overall hits
|
||
|
system.cpu0.dcache.overall_hits::total 22791048 # number of overall hits
|
||
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 185432 # number of ReadReq misses
|
||
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 58086 # number of ReadReq misses
|
||
|
system.cpu0.dcache.ReadReq_misses::cpu2.data 273913 # number of ReadReq misses
|
||
|
system.cpu0.dcache.ReadReq_misses::total 517431 # number of ReadReq misses
|
||
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 168460 # number of WriteReq misses
|
||
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 28983 # number of WriteReq misses
|
||
|
system.cpu0.dcache.WriteReq_misses::cpu2.data 595876 # number of WriteReq misses
|
||
|
system.cpu0.dcache.WriteReq_misses::total 793319 # number of WriteReq misses
|
||
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6522 # number of LoadLockedReq misses
|
||
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1629 # number of LoadLockedReq misses
|
||
|
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3810 # number of LoadLockedReq misses
|
||
|
system.cpu0.dcache.LoadLockedReq_misses::total 11961 # number of LoadLockedReq misses
|
||
|
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 6 # number of StoreCondReq misses
|
||
|
system.cpu0.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses
|
||
|
system.cpu0.dcache.demand_misses::cpu0.data 353892 # number of demand (read+write) misses
|
||
|
system.cpu0.dcache.demand_misses::cpu1.data 87069 # number of demand (read+write) misses
|
||
|
system.cpu0.dcache.demand_misses::cpu2.data 869789 # number of demand (read+write) misses
|
||
|
system.cpu0.dcache.demand_misses::total 1310750 # number of demand (read+write) misses
|
||
|
system.cpu0.dcache.overall_misses::cpu0.data 353892 # number of overall misses
|
||
|
system.cpu0.dcache.overall_misses::cpu1.data 87069 # number of overall misses
|
||
|
system.cpu0.dcache.overall_misses::cpu2.data 869789 # number of overall misses
|
||
|
system.cpu0.dcache.overall_misses::total 1310750 # number of overall misses
|
||
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 824588500 # number of ReadReq miss cycles
|
||
|
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3876286000 # number of ReadReq miss cycles
|
||
|
system.cpu0.dcache.ReadReq_miss_latency::total 4700874500 # number of ReadReq miss cycles
|
||
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 726126000 # number of WriteReq miss cycles
|
||
|
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19133055918 # number of WriteReq miss cycles
|
||
|
system.cpu0.dcache.WriteReq_miss_latency::total 19859181918 # number of WriteReq miss cycles
|
||
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 21335000 # number of LoadLockedReq miss cycles
|
||
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 51226000 # number of LoadLockedReq miss cycles
|
||
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 72561000 # number of LoadLockedReq miss cycles
|
||
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 78000 # number of StoreCondReq miss cycles
|
||
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 78000 # number of StoreCondReq miss cycles
|
||
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 1550714500 # number of demand (read+write) miss cycles
|
||
|
system.cpu0.dcache.demand_miss_latency::cpu2.data 23009341918 # number of demand (read+write) miss cycles
|
||
|
system.cpu0.dcache.demand_miss_latency::total 24560056418 # number of demand (read+write) miss cycles
|
||
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 1550714500 # number of overall miss cycles
|
||
|
system.cpu0.dcache.overall_miss_latency::cpu2.data 23009341918 # number of overall miss cycles
|
||
|
system.cpu0.dcache.overall_miss_latency::total 24560056418 # number of overall miss cycles
|
||
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6948599 # number of ReadReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1935908 # number of ReadReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4991981 # number of ReadReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.ReadReq_accesses::total 13876488 # number of ReadReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 6132017 # number of WriteReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1394600 # number of WriteReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2698693 # number of WriteReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.WriteReq_accesses::total 10225310 # number of WriteReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 142092 # number of LoadLockedReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34426 # number of LoadLockedReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 95117 # number of LoadLockedReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.LoadLockedReq_accesses::total 271635 # number of LoadLockedReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 142092 # number of StoreCondReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34425 # number of StoreCondReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 91930 # number of StoreCondReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.StoreCondReq_accesses::total 268447 # number of StoreCondReq accesses(hits+misses)
|
||
|
system.cpu0.dcache.demand_accesses::cpu0.data 13080616 # number of demand (read+write) accesses
|
||
|
system.cpu0.dcache.demand_accesses::cpu1.data 3330508 # number of demand (read+write) accesses
|
||
|
system.cpu0.dcache.demand_accesses::cpu2.data 7690674 # number of demand (read+write) accesses
|
||
|
system.cpu0.dcache.demand_accesses::total 24101798 # number of demand (read+write) accesses
|
||
|
system.cpu0.dcache.overall_accesses::cpu0.data 13080616 # number of overall (read+write) accesses
|
||
|
system.cpu0.dcache.overall_accesses::cpu1.data 3330508 # number of overall (read+write) accesses
|
||
|
system.cpu0.dcache.overall_accesses::cpu2.data 7690674 # number of overall (read+write) accesses
|
||
|
system.cpu0.dcache.overall_accesses::total 24101798 # number of overall (read+write) accesses
|
||
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026686 # miss rate for ReadReq accesses
|
||
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030005 # miss rate for ReadReq accesses
|
||
|
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.054871 # miss rate for ReadReq accesses
|
||
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.037288 # miss rate for ReadReq accesses
|
||
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027472 # miss rate for WriteReq accesses
|
||
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020782 # miss rate for WriteReq accesses
|
||
|
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220802 # miss rate for WriteReq accesses
|
||
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.077584 # miss rate for WriteReq accesses
|
||
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045900 # miss rate for LoadLockedReq accesses
|
||
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047319 # miss rate for LoadLockedReq accesses
|
||
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.040056 # miss rate for LoadLockedReq accesses
|
||
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.044033 # miss rate for LoadLockedReq accesses
|
||
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000065 # miss rate for StoreCondReq accesses
|
||
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000022 # miss rate for StoreCondReq accesses
|
||
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027055 # miss rate for demand accesses
|
||
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026143 # miss rate for demand accesses
|
||
|
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.113097 # miss rate for demand accesses
|
||
|
system.cpu0.dcache.demand_miss_rate::total 0.054384 # miss rate for demand accesses
|
||
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027055 # miss rate for overall accesses
|
||
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026143 # miss rate for overall accesses
|
||
|
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.113097 # miss rate for overall accesses
|
||
|
system.cpu0.dcache.overall_miss_rate::total 0.054384 # miss rate for overall accesses
|
||
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14195.993871 # average ReadReq miss latency
|
||
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14151.522564 # average ReadReq miss latency
|
||
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 9085.026796 # average ReadReq miss latency
|
||
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 25053.514129 # average WriteReq miss latency
|
||
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32109.123237 # average WriteReq miss latency
|
||
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 25033.034527 # average WriteReq miss latency
|
||
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13096.992020 # average LoadLockedReq miss latency
|
||
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13445.144357 # average LoadLockedReq miss latency
|
||
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6066.466015 # average LoadLockedReq miss latency
|
||
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
|
||
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
|
||
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17810.179283 # average overall miss latency
|
||
|
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26453.935285 # average overall miss latency
|
||
|
system.cpu0.dcache.demand_avg_miss_latency::total 18737.407147 # average overall miss latency
|
||
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17810.179283 # average overall miss latency
|
||
|
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 26453.935285 # average overall miss latency
|
||
|
system.cpu0.dcache.overall_avg_miss_latency::total 18737.407147 # average overall miss latency
|
||
|
system.cpu0.dcache.blocked_cycles::no_mshrs 6963 # number of cycles access was blocked
|
||
|
system.cpu0.dcache.blocked_cycles::no_targets 952 # number of cycles access was blocked
|
||
|
system.cpu0.dcache.blocked::no_mshrs 771 # number of cycles access was blocked
|
||
|
system.cpu0.dcache.blocked::no_targets 46 # number of cycles access was blocked
|
||
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.031128 # average number of cycles each access was blocked
|
||
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 20.695652 # average number of cycles each access was blocked
|
||
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||
|
system.cpu0.dcache.writebacks::writebacks 597611 # number of writebacks
|
||
|
system.cpu0.dcache.writebacks::total 597611 # number of writebacks
|
||
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145491 # number of ReadReq MSHR hits
|
||
|
system.cpu0.dcache.ReadReq_mshr_hits::total 145491 # number of ReadReq MSHR hits
|
||
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 543392 # number of WriteReq MSHR hits
|
||
|
system.cpu0.dcache.WriteReq_mshr_hits::total 543392 # number of WriteReq MSHR hits
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 428 # number of LoadLockedReq MSHR hits
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 428 # number of LoadLockedReq MSHR hits
|
||
|
system.cpu0.dcache.demand_mshr_hits::cpu2.data 688883 # number of demand (read+write) MSHR hits
|
||
|
system.cpu0.dcache.demand_mshr_hits::total 688883 # number of demand (read+write) MSHR hits
|
||
|
system.cpu0.dcache.overall_mshr_hits::cpu2.data 688883 # number of overall MSHR hits
|
||
|
system.cpu0.dcache.overall_mshr_hits::total 688883 # number of overall MSHR hits
|
||
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 58086 # number of ReadReq MSHR misses
|
||
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 128422 # number of ReadReq MSHR misses
|
||
|
system.cpu0.dcache.ReadReq_mshr_misses::total 186508 # number of ReadReq MSHR misses
|
||
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28983 # number of WriteReq MSHR misses
|
||
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52484 # number of WriteReq MSHR misses
|
||
|
system.cpu0.dcache.WriteReq_mshr_misses::total 81467 # number of WriteReq MSHR misses
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1629 # number of LoadLockedReq MSHR misses
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3382 # number of LoadLockedReq MSHR misses
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5011 # number of LoadLockedReq MSHR misses
|
||
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 6 # number of StoreCondReq MSHR misses
|
||
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses
|
||
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 87069 # number of demand (read+write) MSHR misses
|
||
|
system.cpu0.dcache.demand_mshr_misses::cpu2.data 180906 # number of demand (read+write) MSHR misses
|
||
|
system.cpu0.dcache.demand_mshr_misses::total 267975 # number of demand (read+write) MSHR misses
|
||
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 87069 # number of overall MSHR misses
|
||
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 180906 # number of overall MSHR misses
|
||
|
system.cpu0.dcache.overall_mshr_misses::total 267975 # number of overall MSHR misses
|
||
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 708416500 # number of ReadReq MSHR miss cycles
|
||
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1664999000 # number of ReadReq MSHR miss cycles
|
||
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2373415500 # number of ReadReq MSHR miss cycles
|
||
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 668160000 # number of WriteReq MSHR miss cycles
|
||
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1456004992 # number of WriteReq MSHR miss cycles
|
||
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2124164992 # number of WriteReq MSHR miss cycles
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 18077000 # number of LoadLockedReq MSHR miss cycles
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 39418000 # number of LoadLockedReq MSHR miss cycles
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57495000 # number of LoadLockedReq MSHR miss cycles
|
||
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 66000 # number of StoreCondReq MSHR miss cycles
|
||
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66000 # number of StoreCondReq MSHR miss cycles
|
||
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1376576500 # number of demand (read+write) MSHR miss cycles
|
||
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3121003992 # number of demand (read+write) MSHR miss cycles
|
||
|
system.cpu0.dcache.demand_mshr_miss_latency::total 4497580492 # number of demand (read+write) MSHR miss cycles
|
||
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1376576500 # number of overall MSHR miss cycles
|
||
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3121003992 # number of overall MSHR miss cycles
|
||
|
system.cpu0.dcache.overall_mshr_miss_latency::total 4497580492 # number of overall MSHR miss cycles
|
||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27568021500 # number of ReadReq MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29009742000 # number of ReadReq MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56577763500 # number of ReadReq MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1272962000 # number of WriteReq MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 12893978360 # number of WriteReq MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14166940360 # number of WriteReq MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28840983500 # number of overall MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41903720360 # number of overall MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70744703860 # number of overall MSHR uncacheable cycles
|
||
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030005 # mshr miss rate for ReadReq accesses
|
||
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.025726 # mshr miss rate for ReadReq accesses
|
||
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013441 # mshr miss rate for ReadReq accesses
|
||
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.020782 # mshr miss rate for WriteReq accesses
|
||
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019448 # mshr miss rate for WriteReq accesses
|
||
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007967 # mshr miss rate for WriteReq accesses
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047319 # mshr miss rate for LoadLockedReq accesses
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.035556 # mshr miss rate for LoadLockedReq accesses
|
||
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018448 # mshr miss rate for LoadLockedReq accesses
|
||
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000065 # mshr miss rate for StoreCondReq accesses
|
||
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000022 # mshr miss rate for StoreCondReq accesses
|
||
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026143 # mshr miss rate for demand accesses
|
||
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023523 # mshr miss rate for demand accesses
|
||
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.011118 # mshr miss rate for demand accesses
|
||
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026143 # mshr miss rate for overall accesses
|
||
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.023523 # mshr miss rate for overall accesses
|
||
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.011118 # mshr miss rate for overall accesses
|
||
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12195.993871 # average ReadReq mshr miss latency
|
||
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12965.060504 # average ReadReq mshr miss latency
|
||
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12725.542604 # average ReadReq mshr miss latency
|
||
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23053.514129 # average WriteReq mshr miss latency
|
||
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27741.883088 # average WriteReq mshr miss latency
|
||
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26073.931678 # average WriteReq mshr miss latency
|
||
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11096.992020 # average LoadLockedReq mshr miss latency
|
||
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11655.233590 # average LoadLockedReq mshr miss latency
|
||
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11473.757733 # average LoadLockedReq mshr miss latency
|
||
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
|
||
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
|
||
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15810.179283 # average overall mshr miss latency
|
||
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17252.075619 # average overall mshr miss latency
|
||
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16783.582394 # average overall mshr miss latency
|
||
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15810.179283 # average overall mshr miss latency
|
||
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17252.075619 # average overall mshr miss latency
|
||
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16783.582394 # average overall mshr miss latency
|
||
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
||
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
||
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
||
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
||
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
|
||
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
|
||
|
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
|
||
|
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
|
||
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
||
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
||
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
||
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
||
|
system.cpu1.dtb.read_hits 2149941 # DTB read hits
|
||
|
system.cpu1.dtb.read_misses 2094 # DTB read misses
|
||
|
system.cpu1.dtb.write_hits 1479770 # DTB write hits
|
||
|
system.cpu1.dtb.write_misses 382 # DTB write misses
|
||
|
system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed
|
||
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||
|
system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID
|
||
|
system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
|
||
|
system.cpu1.dtb.flush_entries 1681 # Number of entries that have been flushed from TLB
|
||
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||
|
system.cpu1.dtb.prefetch_faults 46 # Number of TLB faults due to prefetch
|
||
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||
|
system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions
|
||
|
system.cpu1.dtb.read_accesses 2152035 # DTB read accesses
|
||
|
system.cpu1.dtb.write_accesses 1480152 # DTB write accesses
|
||
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
||
|
system.cpu1.dtb.hits 3629711 # DTB hits
|
||
|
system.cpu1.dtb.misses 2476 # DTB misses
|
||
|
system.cpu1.dtb.accesses 3632187 # DTB accesses
|
||
|
system.cpu1.itb.inst_hits 8564825 # ITB inst hits
|
||
|
system.cpu1.itb.inst_misses 1128 # ITB inst misses
|
||
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
||
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
||
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
||
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
||
|
system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed
|
||
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||
|
system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID
|
||
|
system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
|
||
|
system.cpu1.itb.flush_entries 827 # Number of entries that have been flushed from TLB
|
||
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
||
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
||
|
system.cpu1.itb.inst_accesses 8565953 # ITB inst accesses
|
||
|
system.cpu1.itb.hits 8564825 # DTB hits
|
||
|
system.cpu1.itb.misses 1128 # DTB misses
|
||
|
system.cpu1.itb.accesses 8565953 # DTB accesses
|
||
|
system.cpu1.numCycles 573618226 # number of cpu cycles simulated
|
||
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||
|
system.cpu1.committedInsts 8360582 # Number of instructions committed
|
||
|
system.cpu1.committedOps 10552123 # Number of ops (including micro ops) committed
|
||
|
system.cpu1.num_int_alu_accesses 9474069 # Number of integer alu accesses
|
||
|
system.cpu1.num_fp_alu_accesses 2062 # Number of float alu accesses
|
||
|
system.cpu1.num_func_calls 304948 # number of times a function call or return occured
|
||
|
system.cpu1.num_conditional_control_insts 1122653 # number of instructions that are conditional controls
|
||
|
system.cpu1.num_int_insts 9474069 # number of integer instructions
|
||
|
system.cpu1.num_fp_insts 2062 # number of float instructions
|
||
|
system.cpu1.num_int_register_reads 54388368 # number of times the integer registers were read
|
||
|
system.cpu1.num_int_register_writes 10296894 # number of times the integer registers were written
|
||
|
system.cpu1.num_fp_register_reads 1613 # number of times the floating registers were read
|
||
|
system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written
|
||
|
system.cpu1.num_mem_refs 3801129 # number of memory refs
|
||
|
system.cpu1.num_load_insts 2242444 # Number of load instructions
|
||
|
system.cpu1.num_store_insts 1558685 # Number of store instructions
|
||
|
system.cpu1.num_idle_cycles -28470862.464355 # Number of idle cycles
|
||
|
system.cpu1.num_busy_cycles 602089088.464355 # Number of busy cycles
|
||
|
system.cpu1.not_idle_fraction 1.049634 # Percentage of non-idle cycles
|
||
|
system.cpu1.idle_fraction -0.049634 # Percentage of idle cycles
|
||
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||
|
system.cpu2.dtb.inst_hits 0 # ITB inst hits
|
||
|
system.cpu2.dtb.inst_misses 0 # ITB inst misses
|
||
|
system.cpu2.dtb.read_hits 11072336 # DTB read hits
|
||
|
system.cpu2.dtb.read_misses 27162 # DTB read misses
|
||
|
system.cpu2.dtb.write_hits 3379244 # DTB write hits
|
||
|
system.cpu2.dtb.write_misses 7485 # DTB write misses
|
||
|
system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed
|
||
|
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||
|
system.cpu2.dtb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID
|
||
|
system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
|
||
|
system.cpu2.dtb.flush_entries 3059 # Number of entries that have been flushed from TLB
|
||
|
system.cpu2.dtb.align_faults 671 # Number of TLB faults due to alignment restrictions
|
||
|
system.cpu2.dtb.prefetch_faults 210 # Number of TLB faults due to prefetch
|
||
|
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||
|
system.cpu2.dtb.perms_faults 417 # Number of TLB faults due to permissions restrictions
|
||
|
system.cpu2.dtb.read_accesses 11099498 # DTB read accesses
|
||
|
system.cpu2.dtb.write_accesses 3386729 # DTB write accesses
|
||
|
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
|
||
|
system.cpu2.dtb.hits 14451580 # DTB hits
|
||
|
system.cpu2.dtb.misses 34647 # DTB misses
|
||
|
system.cpu2.dtb.accesses 14486227 # DTB accesses
|
||
|
system.cpu2.itb.inst_hits 3940913 # ITB inst hits
|
||
|
system.cpu2.itb.inst_misses 4663 # ITB inst misses
|
||
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
||
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
||
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
||
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
||
|
system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed
|
||
|
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||
|
system.cpu2.itb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID
|
||
|
system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
|
||
|
system.cpu2.itb.flush_entries 1673 # Number of entries that have been flushed from TLB
|
||
|
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||
|
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||
|
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||
|
system.cpu2.itb.perms_faults 1015 # Number of TLB faults due to permissions restrictions
|
||
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
||
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
||
|
system.cpu2.itb.inst_accesses 3945576 # ITB inst accesses
|
||
|
system.cpu2.itb.hits 3940913 # DTB hits
|
||
|
system.cpu2.itb.misses 4663 # DTB misses
|
||
|
system.cpu2.itb.accesses 3945576 # DTB accesses
|
||
|
system.cpu2.numCycles 88228970 # number of cpu cycles simulated
|
||
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
||
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||
|
system.cpu2.BPredUnit.lookups 4678533 # Number of BP lookups
|
||
|
system.cpu2.BPredUnit.condPredicted 3809806 # Number of conditional branches predicted
|
||
|
system.cpu2.BPredUnit.condIncorrect 231267 # Number of conditional branches incorrect
|
||
|
system.cpu2.BPredUnit.BTBLookups 3069092 # Number of BTB lookups
|
||
|
system.cpu2.BPredUnit.BTBHits 2498136 # Number of BTB hits
|
||
|
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||
|
system.cpu2.BPredUnit.usedRAS 412114 # Number of times the RAS was used to get a target.
|
||
|
system.cpu2.BPredUnit.RASInCorrect 22380 # Number of incorrect RAS predictions.
|
||
|
system.cpu2.fetch.icacheStallCycles 9360105 # Number of cycles fetch is stalled on an Icache miss
|
||
|
system.cpu2.fetch.Insts 31976282 # Number of instructions fetch has processed
|
||
|
system.cpu2.fetch.Branches 4678533 # Number of branches that fetch encountered
|
||
|
system.cpu2.fetch.predictedBranches 2910250 # Number of branches that fetch has predicted taken
|
||
|
system.cpu2.fetch.Cycles 6786917 # Number of cycles fetch has run and was not squashing or blocked
|
||
|
system.cpu2.fetch.SquashCycles 1728503 # Number of cycles fetch has spent squashing
|
||
|
system.cpu2.fetch.TlbCycles 53808 # Number of cycles fetch has spent waiting for tlb
|
||
|
system.cpu2.fetch.BlockedCycles 19342330 # Number of cycles fetch has spent blocked
|
||
|
system.cpu2.fetch.MiscStallCycles 594 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||
|
system.cpu2.fetch.PendingDrainCycles 913 # Number of cycles fetch has spent waiting on pipes to drain
|
||
|
system.cpu2.fetch.PendingTrapStallCycles 36859 # Number of stall cycles due to pending traps
|
||
|
system.cpu2.fetch.PendingQuiesceStallCycles 59251 # Number of stall cycles due to pending quiesce instructions
|
||
|
system.cpu2.fetch.IcacheWaitRetryStallCycles 389 # Number of stall cycles due to full MSHR
|
||
|
system.cpu2.fetch.CacheLines 3939412 # Number of cache lines fetched
|
||
|
system.cpu2.fetch.IcacheSquashes 244088 # Number of outstanding Icache misses that were squashed
|
||
|
system.cpu2.fetch.ItlbSquashes 2174 # Number of outstanding ITLB misses that were squashed
|
||
|
system.cpu2.fetch.rateDist::samples 36830548 # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::mean 1.047719 # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::stdev 2.434253 # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::0 30048718 81.59% 81.59% # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::1 408687 1.11% 82.70% # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::2 492187 1.34% 84.03% # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::3 812698 2.21% 86.24% # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::4 611463 1.66% 87.90% # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::5 330922 0.90% 88.80% # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::6 1062958 2.89% 91.68% # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::7 224607 0.61% 92.29% # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::8 2838308 7.71% 100.00% # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.rateDist::total 36830548 # Number of instructions fetched each cycle (Total)
|
||
|
system.cpu2.fetch.branchRate 0.053027 # Number of branch fetches per cycle
|
||
|
system.cpu2.fetch.rate 0.362424 # Number of inst fetches per cycle
|
||
|
system.cpu2.decode.IdleCycles 9885763 # Number of cycles decode is idle
|
||
|
system.cpu2.decode.BlockedCycles 19327017 # Number of cycles decode is blocked
|
||
|
system.cpu2.decode.RunCycles 6180149 # Number of cycles decode is running
|
||
|
system.cpu2.decode.UnblockCycles 300885 # Number of cycles decode is unblocking
|
||
|
system.cpu2.decode.SquashCycles 1135792 # Number of cycles decode is squashing
|
||
|
system.cpu2.decode.BranchResolved 597498 # Number of times decode resolved a branch
|
||
|
system.cpu2.decode.BranchMispred 54848 # Number of times decode detected a branch misprediction
|
||
|
system.cpu2.decode.DecodedInsts 36565818 # Number of instructions handled by decode
|
||
|
system.cpu2.decode.SquashedInsts 186819 # Number of squashed instructions handled by decode
|
||
|
system.cpu2.rename.SquashCycles 1135792 # Number of cycles rename is squashing
|
||
|
system.cpu2.rename.IdleCycles 10385247 # Number of cycles rename is idle
|
||
|
system.cpu2.rename.BlockCycles 6621320 # Number of cycles rename is blocking
|
||
|
system.cpu2.rename.serializeStallCycles 11277395 # count of cycles rename stalled for serializing inst
|
||
|
system.cpu2.rename.RunCycles 5962558 # Number of cycles rename is running
|
||
|
system.cpu2.rename.UnblockCycles 1447335 # Number of cycles rename is unblocking
|
||
|
system.cpu2.rename.RenamedInsts 34838937 # Number of instructions processed by rename
|
||
|
system.cpu2.rename.ROBFullEvents 2719 # Number of times rename has blocked due to ROB full
|
||
|
system.cpu2.rename.IQFullEvents 250879 # Number of times rename has blocked due to IQ full
|
||
|
system.cpu2.rename.LSQFullEvents 912957 # Number of times rename has blocked due to LSQ full
|
||
|
system.cpu2.rename.FullRegisterEvents 22201 # Number of times there has been no free registers
|
||
|
system.cpu2.rename.RenamedOperands 37227895 # Number of destination operands rename has renamed
|
||
|
system.cpu2.rename.RenameLookups 159446068 # Number of register rename lookups that rename has made
|
||
|
system.cpu2.rename.int_rename_lookups 159418988 # Number of integer rename lookups
|
||
|
system.cpu2.rename.fp_rename_lookups 27080 # Number of floating rename lookups
|
||
|
system.cpu2.rename.CommittedMaps 26794485 # Number of HB maps that are committed
|
||
|
system.cpu2.rename.UndoneMaps 10433409 # Number of HB maps that are undone due to squashing
|
||
|
system.cpu2.rename.serializingInsts 254044 # count of serializing insts renamed
|
||
|
system.cpu2.rename.tempSerializingInsts 230219 # count of temporary serializing insts renamed
|
||
|
system.cpu2.rename.skidInsts 3142941 # count of insts added to the skid buffer
|
||
|
system.cpu2.memDep0.insertedLoads 6628278 # Number of loads inserted to the mem dependence unit.
|
||
|
system.cpu2.memDep0.insertedStores 3915406 # Number of stores inserted to the mem dependence unit.
|
||
|
system.cpu2.memDep0.conflictingLoads 518992 # Number of conflicting loads.
|
||
|
system.cpu2.memDep0.conflictingStores 767543 # Number of conflicting stores.
|
||
|
system.cpu2.iq.iqInstsAdded 32164019 # Number of instructions added to the IQ (excludes non-spec)
|
||
|
system.cpu2.iq.iqNonSpecInstsAdded 534132 # Number of non-speculative instructions added to the IQ
|
||
|
system.cpu2.iq.iqInstsIssued 35030885 # Number of instructions issued
|
||
|
system.cpu2.iq.iqSquashedInstsIssued 59969 # Number of squashed instructions issued
|
||
|
system.cpu2.iq.iqSquashedInstsExamined 6868407 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||
|
system.cpu2.iq.iqSquashedOperandsExamined 17749072 # Number of squashed operands that are examined and possibly removed from graph
|
||
|
system.cpu2.iq.iqSquashedNonSpecRemoved 150741 # Number of squashed non-spec instructions that were removed
|
||
|
system.cpu2.iq.issued_per_cycle::samples 36830548 # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::mean 0.951137 # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::stdev 1.612264 # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::0 24216483 65.75% 65.75% # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::1 3835065 10.41% 76.16% # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::2 2287291 6.21% 82.37% # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::3 1980355 5.38% 87.75% # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::4 2800040 7.60% 95.35% # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::5 1007857 2.74% 98.09% # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::6 517219 1.40% 99.49% # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::7 152490 0.41% 99.91% # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::8 33748 0.09% 100.00% # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||
|
system.cpu2.iq.issued_per_cycle::total 36830548 # Number of insts issued each cycle
|
||
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::IntAlu 17662 1.14% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::MemRead 1415792 91.50% 92.64% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::MemWrite 113850 7.36% 100.00% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||
|
system.cpu2.iq.FU_type_0::No_OpClass 60995 0.17% 0.17% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::IntAlu 19871242 56.72% 56.90% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::IntMult 29695 0.08% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 372 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.98% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::MemRead 11515486 32.87% 89.86% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::MemWrite 3553080 10.14% 100.00% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||
|
system.cpu2.iq.FU_type_0::total 35030885 # Type of FU issued
|
||
|
system.cpu2.iq.rate 0.397045 # Inst issue rate
|
||
|
system.cpu2.iq.fu_busy_cnt 1547304 # FU busy when requested
|
||
|
system.cpu2.iq.fu_busy_rate 0.044170 # FU busy rate (busy events/executed inst)
|
||
|
system.cpu2.iq.int_inst_queue_reads 108527324 # Number of integer instruction queue reads
|
||
|
system.cpu2.iq.int_inst_queue_writes 39572230 # Number of integer instruction queue writes
|
||
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 28399462 # Number of integer instruction queue wakeup accesses
|
||
|
system.cpu2.iq.fp_inst_queue_reads 6790 # Number of floating instruction queue reads
|
||
|
system.cpu2.iq.fp_inst_queue_writes 3711 # Number of floating instruction queue writes
|
||
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 3127 # Number of floating instruction queue wakeup accesses
|
||
|
system.cpu2.iq.int_alu_accesses 36513628 # Number of integer alu accesses
|
||
|
system.cpu2.iq.fp_alu_accesses 3566 # Number of floating point alu accesses
|
||
|
system.cpu2.iew.lsq.thread0.forwLoads 191014 # Number of loads that had data forwarded from stores
|
||
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||
|
system.cpu2.iew.lsq.thread0.squashedLoads 1467031 # Number of loads squashed
|
||
|
system.cpu2.iew.lsq.thread0.ignoredResponses 2011 # Number of memory responses ignored because the instruction is squashed
|
||
|
system.cpu2.iew.lsq.thread0.memOrderViolation 9738 # Number of memory ordering violations
|
||
|
system.cpu2.iew.lsq.thread0.squashedStores 545094 # Number of stores squashed
|
||
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 5365251 # Number of loads that were rescheduled
|
||
|
system.cpu2.iew.lsq.thread0.cacheBlocked 332989 # Number of times an access to memory failed due to the cache being blocked
|
||
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||
|
system.cpu2.iew.iewSquashCycles 1135792 # Number of cycles IEW is squashing
|
||
|
system.cpu2.iew.iewBlockCycles 4899150 # Number of cycles IEW is blocking
|
||
|
system.cpu2.iew.iewUnblockCycles 89921 # Number of cycles IEW is unblocking
|
||
|
system.cpu2.iew.iewDispatchedInsts 32779082 # Number of instructions dispatched to IQ
|
||
|
system.cpu2.iew.iewDispSquashedInsts 64376 # Number of squashed instructions skipped by dispatch
|
||
|
system.cpu2.iew.iewDispLoadInsts 6628278 # Number of dispatched load instructions
|
||
|
system.cpu2.iew.iewDispStoreInsts 3915406 # Number of dispatched store instructions
|
||
|
system.cpu2.iew.iewDispNonSpecInsts 386018 # Number of dispatched non-speculative instructions
|
||
|
system.cpu2.iew.iewIQFullEvents 31359 # Number of times the IQ has become full, causing a stall
|
||
|
system.cpu2.iew.iewLSQFullEvents 2570 # Number of times the LSQ has become full, causing a stall
|
||
|
system.cpu2.iew.memOrderViolationEvents 9738 # Number of memory order violations
|
||
|
system.cpu2.iew.predictedTakenIncorrect 111294 # Number of branches that were predicted taken incorrectly
|
||
|
system.cpu2.iew.predictedNotTakenIncorrect 92702 # Number of branches that were predicted not taken incorrectly
|
||
|
system.cpu2.iew.branchMispredicts 203996 # Number of branch mispredicts detected at execute
|
||
|
system.cpu2.iew.iewExecutedInsts 34250844 # Number of executed instructions
|
||
|
system.cpu2.iew.iewExecLoadInsts 11286425 # Number of load instructions executed
|
||
|
system.cpu2.iew.iewExecSquashedInsts 780041 # Number of squashed instructions skipped in execute
|
||
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
||
|
system.cpu2.iew.exec_nop 80931 # number of nop insts executed
|
||
|
system.cpu2.iew.exec_refs 14805022 # number of memory reference insts executed
|
||
|
system.cpu2.iew.exec_branches 3673391 # Number of branches executed
|
||
|
system.cpu2.iew.exec_stores 3518597 # Number of stores executed
|
||
|
system.cpu2.iew.exec_rate 0.388204 # Inst execution rate
|
||
|
system.cpu2.iew.wb_sent 33866957 # cumulative count of insts sent to commit
|
||
|
system.cpu2.iew.wb_count 28402589 # cumulative count of insts written-back
|
||
|
system.cpu2.iew.wb_producers 16335424 # num instructions producing a value
|
||
|
system.cpu2.iew.wb_consumers 29431571 # num instructions consuming a value
|
||
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||
|
system.cpu2.iew.wb_rate 0.321919 # insts written-back per cycle
|
||
|
system.cpu2.iew.wb_fanout 0.555031 # average fanout of values written-back
|
||
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||
|
system.cpu2.commit.commitSquashedInsts 6831747 # The number of squashed insts skipped by commit
|
||
|
system.cpu2.commit.commitNonSpecStalls 383391 # The number of times commit has been forced to stall to communicate backwards
|
||
|
system.cpu2.commit.branchMispredicts 177223 # The number of times a branch was mispredicted
|
||
|
system.cpu2.commit.committed_per_cycle::samples 35694573 # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::mean 0.719725 # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::stdev 1.780912 # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::0 26969912 75.56% 75.56% # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::1 4228252 11.85% 87.40% # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::2 1198360 3.36% 90.76% # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::3 616402 1.73% 92.49% # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::4 527161 1.48% 93.96% # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::5 311066 0.87% 94.84% # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::6 434912 1.22% 96.05% # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::7 325428 0.91% 96.97% # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::8 1083080 3.03% 100.00% # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committed_per_cycle::total 35694573 # Number of insts commited each cycle
|
||
|
system.cpu2.commit.committedInsts 20797962 # Number of instructions committed
|
||
|
system.cpu2.commit.committedOps 25690260 # Number of ops (including micro ops) committed
|
||
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
||
|
system.cpu2.commit.refs 8531559 # Number of memory references committed
|
||
|
system.cpu2.commit.loads 5161247 # Number of loads committed
|
||
|
system.cpu2.commit.membars 98356 # Number of memory barriers committed
|
||
|
system.cpu2.commit.branches 3158165 # Number of branches committed
|
||
|
system.cpu2.commit.fp_insts 3087 # Number of committed floating point instructions.
|
||
|
system.cpu2.commit.int_insts 22900752 # Number of committed integer instructions.
|
||
|
system.cpu2.commit.function_calls 287889 # Number of function calls committed.
|
||
|
system.cpu2.commit.bw_lim_events 1083080 # number cycles where commit BW limit reached
|
||
|
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||
|
system.cpu2.rob.rob_reads 66589270 # The number of ROB reads
|
||
|
system.cpu2.rob.rob_writes 66235051 # The number of ROB writes
|
||
|
system.cpu2.timesIdled 359715 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||
|
system.cpu2.idleCycles 51398422 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||
|
system.cpu2.quiesceCycles 3569788363 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
||
|
system.cpu2.committedInsts 20743850 # Number of Instructions Simulated
|
||
|
system.cpu2.committedOps 25636148 # Number of Ops (including micro ops) Simulated
|
||
|
system.cpu2.committedInsts_total 20743850 # Number of Instructions Simulated
|
||
|
system.cpu2.cpi 4.253259 # CPI: Cycles Per Instruction
|
||
|
system.cpu2.cpi_total 4.253259 # CPI: Total CPI of All Threads
|
||
|
system.cpu2.ipc 0.235114 # IPC: Instructions Per Cycle
|
||
|
system.cpu2.ipc_total 0.235114 # IPC: Total IPC of All Threads
|
||
|
system.cpu2.int_regfile_reads 159046643 # number of integer regfile reads
|
||
|
system.cpu2.int_regfile_writes 30194860 # number of integer regfile writes
|
||
|
system.cpu2.fp_regfile_reads 22317 # number of floating regfile reads
|
||
|
system.cpu2.fp_regfile_writes 20822 # number of floating regfile writes
|
||
|
system.cpu2.misc_regfile_reads 41979427 # number of misc regfile reads
|
||
|
system.cpu2.misc_regfile_writes 278833 # number of misc regfile writes
|
||
|
system.iocache.replacements 0 # number of replacements
|
||
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||
|
system.iocache.fast_writes 0 # number of fast writes performed
|
||
|
system.iocache.cache_copies 0 # number of cache copies performed
|
||
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 925539770424 # number of ReadReq MSHR uncacheable cycles
|
||
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 925539770424 # number of ReadReq MSHR uncacheable cycles
|
||
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 925539770424 # number of overall MSHR uncacheable cycles
|
||
|
system.iocache.overall_mshr_uncacheable_latency::total 925539770424 # number of overall MSHR uncacheable cycles
|
||
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
||
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
||
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||
|
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
|
||
|
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||
|
|
||
|
---------- End Simulation Statistics ----------
|