2009-05-11 19:38:43 +02:00
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2009-05-11 19:38:45 +02:00
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#include "mem/gems_common/PrioHeap.hh"
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2010-03-24 06:49:43 +01:00
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#include "mem/ruby/profiler/AccessTraceForAddress.hh"
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#include "mem/ruby/profiler/CacheProfiler.hh"
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#include "mem/ruby/profiler/Profiler.hh"
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#include "mem/ruby/system/System.hh"
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2009-05-11 19:38:43 +02:00
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2010-04-02 20:20:32 +02:00
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using namespace std;
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2010-01-30 05:29:22 +01:00
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CacheProfiler::CacheProfiler(const string& description)
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2010-06-11 08:17:07 +02:00
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: m_requestTypeVec(int(CacheRequestType_NUM))
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2009-05-11 19:38:43 +02:00
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{
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2010-03-24 06:49:43 +01:00
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m_description = description;
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2009-05-11 19:38:43 +02:00
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2010-03-24 06:49:43 +01:00
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clearStats();
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2009-05-11 19:38:43 +02:00
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}
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CacheProfiler::~CacheProfiler()
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{
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}
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2010-03-24 06:49:43 +01:00
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void
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CacheProfiler::printStats(ostream& out) const
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2009-05-11 19:38:43 +02:00
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{
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2010-03-24 06:49:43 +01:00
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out << "Cache Stats: " << m_description << endl;
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string description = " " + m_description;
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out << description << "_total_misses: " << m_misses << endl;
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out << description << "_total_demand_misses: " << m_demand_misses << endl;
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out << description << "_total_prefetches: " << m_prefetches << endl;
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out << description << "_total_sw_prefetches: " << m_sw_prefetches << endl;
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out << description << "_total_hw_prefetches: " << m_hw_prefetches << endl;
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2009-05-11 19:38:43 +02:00
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out << endl;
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2010-03-24 06:49:43 +01:00
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int requests = 0;
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for (int i = 0; i < int(CacheRequestType_NUM); i++) {
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2010-06-11 08:17:07 +02:00
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requests += m_requestTypeVec[i];
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2009-05-11 19:38:43 +02:00
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}
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2010-03-24 06:49:43 +01:00
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assert(m_misses == requests);
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if (requests > 0) {
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for (int i = 0; i < int(CacheRequestType_NUM); i++) {
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2010-06-11 08:17:07 +02:00
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if (m_requestTypeVec[i] > 0) {
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2010-03-24 06:49:43 +01:00
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out << description << "_request_type_"
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<< CacheRequestType_to_string(CacheRequestType(i))
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<< ": "
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<< 100.0 * (double)m_requestTypeVec[i] /
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2010-03-24 06:49:43 +01:00
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(double)requests
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<< "%" << endl;
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}
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}
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out << endl;
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for (int i = 0; i < AccessModeType_NUM; i++){
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if (m_accessModeTypeHistogram[i] > 0) {
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out << description << "_access_mode_type_"
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<< (AccessModeType) i << ": "
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<< m_accessModeTypeHistogram[i] << " "
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<< 100.0 * m_accessModeTypeHistogram[i] / requests
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<< "%" << endl;
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}
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}
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}
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2009-05-11 19:38:43 +02:00
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2010-03-24 06:49:43 +01:00
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out << description << "_request_size: " << m_requestSize << endl;
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out << endl;
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2009-05-11 19:38:43 +02:00
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}
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2010-03-24 06:49:43 +01:00
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void
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CacheProfiler::clearStats()
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2009-05-11 19:38:43 +02:00
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{
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2010-03-24 06:49:43 +01:00
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for (int i = 0; i < int(CacheRequestType_NUM); i++) {
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2010-06-11 08:17:07 +02:00
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m_requestTypeVec[i] = 0;
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2010-03-24 06:49:43 +01:00
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}
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m_requestSize.clear();
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m_misses = 0;
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m_demand_misses = 0;
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m_prefetches = 0;
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m_sw_prefetches = 0;
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m_hw_prefetches = 0;
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for (int i = 0; i < AccessModeType_NUM; i++) {
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m_accessModeTypeHistogram[i] = 0;
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}
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2009-05-11 19:38:43 +02:00
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}
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2010-03-24 06:49:43 +01:00
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void
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CacheProfiler::addStatSample(CacheRequestType requestType,
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AccessModeType type, int msgSize,
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PrefetchBit pfBit)
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2009-05-11 19:38:43 +02:00
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{
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2010-03-24 06:49:43 +01:00
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m_misses++;
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2010-06-11 08:17:07 +02:00
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m_requestTypeVec[requestType]++;
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2010-03-24 06:49:43 +01:00
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m_accessModeTypeHistogram[type]++;
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m_requestSize.add(msgSize);
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if (pfBit == PrefetchBit_No) {
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m_demand_misses++;
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} else if (pfBit == PrefetchBit_Yes) {
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m_prefetches++;
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m_sw_prefetches++;
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} else {
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// must be L1_HW || L2_HW prefetch
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m_prefetches++;
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m_hw_prefetches++;
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}
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2009-05-11 19:38:43 +02:00
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}
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