72 lines
3 KiB
XML
72 lines
3 KiB
XML
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<?xml version="1.0" ?>
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<component id="root" name="root">
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<component id="system" name="system" type="System">
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<param name="core_tech_node" value="40"/>
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<param name="target_core_clockrate" value="1000"/>
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<param name="temperature" value="360"/>
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<param name="interconnect_projection_type" value="0"/>
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<param name="device_type" value="0"/>
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<param name="machine_bits" value="64"/>
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<param name="virtual_address_width" value="64"/>
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<param name="physical_address_width" value="52"/>
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<param name="virtual_memory_page_size" value="4096"/>
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<param name="wire_is_mat_type" value="2"/>
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<param name="wire_os_mat_type" value="2"/>
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<param name="delay_wt" value="100"/>
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<param name="area_wt" value="0"/>
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<param name="dynamic_power_wt" value="100"/>
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<param name="leakage_power_wt" value="0"/>
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<param name="cycle_time_wt" value="0"/>
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<param name="delay_dev" value="10000"/>
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<param name="area_dev" value="10000"/>
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<param name="dynamic_power_dev" value="10000"/>
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<param name="leakage_power_dev" value="10000"/>
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<param name="cycle_time_dev" value="10000"/>
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<param name="ed" value="2"/>
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<param name="burst_len" value="1"/>
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<param name="int_prefetch_w" value="1"/>
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<param name="page_sz_bits" value="0"/>
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<param name="rpters_in_htree" value="1"/>
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<param name="ver_htree_wires_over_array" value="0"/>
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<param name="nuca" value="0"/>
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<param name="nuca_bank_count" value="0"/>
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<param name="force_cache_config" value="0"/>
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<param name="wt" value="0"/>
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<param name="force_wiretype" value="0"/>
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<param name="print_detail" value="1"/>
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<param name="add_ecc_b_" value="1"/>
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<stat name="total_cycles" value="1856694"/>
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<component id="system.mc" name="mc" type="MemoryController">
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<param name="mc_clock" value="800"/>
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<param name="tech_type" value="0"/>
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<param name="mc_type" value="0"/>
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<param name="num_mcs" value="1"/>
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<param name="type" value="0"/>
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<param name="LVDS" value="1"/>
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<param name="withPHY" value="0"/>
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<param name="llc_line_length" value="64"/>
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<param name="memory_channels_per_mc" value="2"/>
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<param name="req_window_size_per_channel" value="128"/>
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<param name="IO_buffer_size_per_channel" value="128"/>
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<param name="databus_width" value="128"/>
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<param name="addressbus_width" value="51"/>
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<param name="opcode_width" value="16"/>
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<param name="peak_transfer_rate" value="6400"/>
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<param name="number_ranks" value="2"/>
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<param name="reorder_buffer_assoc" value="0"/>
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<param name="reorder_buffer_nbanks" value="1"/>
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<param name="read_buffer_assoc" value="1"/>
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<param name="read_buffer_nbanks" value="1"/>
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<param name="read_buffer_tag_width" value="0"/>
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<param name="write_buffer_assoc" value="1"/>
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<param name="write_buffer_nbanks" value="1"/>
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<param name="write_buffer_tag_width" value="0"/>
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<param name="wire_mat_type" value="2"/>
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<param name="wire_type" value="0"/>
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<stat name="memory_reads" value="5454"/>
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<stat name="memory_writes" value="2424"/>
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<stat name="duty_cycle" value="0.5"/>
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</component>
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</component>
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</component>
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