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gem5/src/sim/ClockedObject.py

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pwr: Add power states to ClockedObject Add 4 power states to the ClockedObject, provides necessary access functions to check and update the power state. Default power state is UNDEFINED, it is responsibility of the respective simulation model to provide the startup state and any other logic for state change. Add number of transition stat. Add distribution of time spent in clock gated state. Add power state residency stat. Add dump call back function to allow stats update of distribution and residency stats. Change-Id: Id086090a2ed720c9fcb37812a3c98f0f724907c6
2016-06-06 18:16:43 +02:00
# Copyright (c) 2012, 2015-2016 ARM Limited
Clock: Move the clock and related functions to ClockedObject This patch moves the clock of the CPU, bus, and numerous devices to the new class ClockedObject, that sits in between the SimObject and MemObject in the class hierarchy. Although there are currently a fair amount of MemObjects that do not make use of the clock, they potentially should do so, e.g. the caches should at some point have the same clock as the CPU, potentially with a 1:n ratio. This patch does not introduce any new clock objects or object hierarchies (clusters, clock domains etc), but is still a step in the direction of having a more structured approach clock domains. The most contentious part of this patch is the serialisation of clocks that some of the modules (but not all) did previously. This serialisation should not be needed as the clock is set through the parameters even when restoring from the checkpoint. In other words, the state is "stored" in the Python code that creates the modules. The nextCycle methods are also simplified and the clock phase parameter of the CPU is removed (this could be part of a clock object once they are introduced).
2012-08-21 11:49:01 +02:00
# All rights reserved.
#
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# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
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# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
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# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# Authors: Andreas Hansson
from m5.SimObject import SimObject
from m5.params import *
Clock: Inherit the clock from parent by default This patch changes the default 1 Tick clock period to a proxy that resolves the parents clock. As a result of this, the caches and L1-to-L2 bus, for example, will automatically use the clock period of the CPU unless explicitly overridden. To ensure backwards compatibility, the System class overrides the proxy and specifies a 1 Tick clock. We could change this to something more reasonable in a follow-on patch, perhaps 1 GHz or something similar. With this patch applied, all clocked objects should have a reasonable clock period set, and could start specifying delays in Cycles instead of absolute time.
2012-10-15 14:07:07 +02:00
from m5.proxy import *
Clock: Move the clock and related functions to ClockedObject This patch moves the clock of the CPU, bus, and numerous devices to the new class ClockedObject, that sits in between the SimObject and MemObject in the class hierarchy. Although there are currently a fair amount of MemObjects that do not make use of the clock, they potentially should do so, e.g. the caches should at some point have the same clock as the CPU, potentially with a 1:n ratio. This patch does not introduce any new clock objects or object hierarchies (clusters, clock domains etc), but is still a step in the direction of having a more structured approach clock domains. The most contentious part of this patch is the serialisation of clocks that some of the modules (but not all) did previously. This serialisation should not be needed as the clock is set through the parameters even when restoring from the checkpoint. In other words, the state is "stored" in the Python code that creates the modules. The nextCycle methods are also simplified and the clock phase parameter of the CPU is removed (this could be part of a clock object once they are introduced).
2012-08-21 11:49:01 +02:00
pwr: Add power states to ClockedObject Add 4 power states to the ClockedObject, provides necessary access functions to check and update the power state. Default power state is UNDEFINED, it is responsibility of the respective simulation model to provide the startup state and any other logic for state change. Add number of transition stat. Add distribution of time spent in clock gated state. Add power state residency stat. Add dump call back function to allow stats update of distribution and residency stats. Change-Id: Id086090a2ed720c9fcb37812a3c98f0f724907c6
2016-06-06 18:16:43 +02:00
# Enumerate set of allowed power states that can be used by a clocked object.
# The list is kept generic to express a base minimal set.
# State definition :-
# Undefined: Invalid state, no power state derived information is available.
# On: The logic block is actively running and consuming dynamic and leakage
# energy depending on the amount of processing required.
# Clk_gated: The clock circuity within the block is gated to save dynamic
# energy, the power supply to the block is still on and leakage
# energy is being consumed by the block.
# Sram_retention: The SRAMs within the logic blocks are pulled into retention
# state to reduce leakage energy further.
# Off: The logic block is power gated and is not consuming any energy.
class PwrState(Enum): vals = ['UNDEFINED',
'ON',
'CLK_GATED',
'SRAM_RETENTION',
'OFF']
Clock: Move the clock and related functions to ClockedObject This patch moves the clock of the CPU, bus, and numerous devices to the new class ClockedObject, that sits in between the SimObject and MemObject in the class hierarchy. Although there are currently a fair amount of MemObjects that do not make use of the clock, they potentially should do so, e.g. the caches should at some point have the same clock as the CPU, potentially with a 1:n ratio. This patch does not introduce any new clock objects or object hierarchies (clusters, clock domains etc), but is still a step in the direction of having a more structured approach clock domains. The most contentious part of this patch is the serialisation of clocks that some of the modules (but not all) did previously. This serialisation should not be needed as the clock is set through the parameters even when restoring from the checkpoint. In other words, the state is "stored" in the Python code that creates the modules. The nextCycle methods are also simplified and the clock phase parameter of the CPU is removed (this could be part of a clock object once they are introduced).
2012-08-21 11:49:01 +02:00
class ClockedObject(SimObject):
type = 'ClockedObject'
abstract = True
sim: Include object header files in SWIG interfaces When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it.
2012-11-02 17:32:01 +01:00
cxx_header = "sim/clocked_object.hh"
Clock: Move the clock and related functions to ClockedObject This patch moves the clock of the CPU, bus, and numerous devices to the new class ClockedObject, that sits in between the SimObject and MemObject in the class hierarchy. Although there are currently a fair amount of MemObjects that do not make use of the clock, they potentially should do so, e.g. the caches should at some point have the same clock as the CPU, potentially with a 1:n ratio. This patch does not introduce any new clock objects or object hierarchies (clusters, clock domains etc), but is still a step in the direction of having a more structured approach clock domains. The most contentious part of this patch is the serialisation of clocks that some of the modules (but not all) did previously. This serialisation should not be needed as the clock is set through the parameters even when restoring from the checkpoint. In other words, the state is "stored" in the Python code that creates the modules. The nextCycle methods are also simplified and the clock phase parameter of the CPU is removed (this could be part of a clock object once they are introduced).
2012-08-21 11:49:01 +02:00
sim: Add the notion of clock domains to all ClockedObjects This patch adds the notion of source- and derived-clock domains to the ClockedObjects. As such, all clock information is moved to the clock domain, and the ClockedObjects are grouped into domains. The clock domains are either source domains, with a specific clock period, or derived domains that have a parent domain and a divider (potentially chained). For piece of logic that runs at a derived clock (a ratio of the clock its parent is running at) the necessary derived clock domain is created from its corresponding parent clock domain. For now, the derived clock domain only supports a divider, thus ensuring a lower speed compared to its parent. Multiplier functionality implies a PLL logic that has not been modelled yet (create a separate clock instead). The clock domains should be used as a mechanism to provide a controllable clock source that affects clock for every clocked object lying beneath it. The clock of the domain can (in a future patch) be controlled by a handler responsible for dynamic frequency scaling of the respective clock domains. All the config scripts have been retro-fitted with clock domains. For the System a default SrcClockDomain is created. For CPUs that run at a different speed than the system, there is a seperate clock domain created. This domain incorporates the CPU and the associated caches. As before, Ruby runs under its own clock domain. The clock period of all domains are pre-computed, such that no virtual functions or multiplications are needed when calling clockPeriod. Instead, the clock period is pre-computed when any changes occur. For this to be possible, each clock domain tracks its children.
2013-06-27 11:49:49 +02:00
# The clock domain this clocked object belongs to, inheriting the
# parent's clock domain by default
clk_domain = Param.ClockDomain(Parent.clk_domain, "Clock domain")
pwr: Add power states to ClockedObject Add 4 power states to the ClockedObject, provides necessary access functions to check and update the power state. Default power state is UNDEFINED, it is responsibility of the respective simulation model to provide the startup state and any other logic for state change. Add number of transition stat. Add distribution of time spent in clock gated state. Add power state residency stat. Add dump call back function to allow stats update of distribution and residency stats. Change-Id: Id086090a2ed720c9fcb37812a3c98f0f724907c6
2016-06-06 18:16:43 +02:00
sim: Adding support for power models This patch adds some basic support for power models in gem5. The power interface is defined so it can interact with thermal models as well. It implements a simple power evaluator that can be used for simple power models that express power in the form of a math expression. These expressions can use stats within the same SimObject (or down its hierarchy) and some magic variables such as "temp" for temperature. In future patches we will extend this functionality to allow slightly more complex expressions. The model allows it to be extended to use other kinds of models. Change-Id: I76752f9638b6815e229fd74cdcb7721a305cbc4b
2016-06-06 18:16:44 +02:00
# Power model for this ClockedObject
power_model = Param.PowerModel(NULL, "Power model")
pwr: Add power states to ClockedObject Add 4 power states to the ClockedObject, provides necessary access functions to check and update the power state. Default power state is UNDEFINED, it is responsibility of the respective simulation model to provide the startup state and any other logic for state change. Add number of transition stat. Add distribution of time spent in clock gated state. Add power state residency stat. Add dump call back function to allow stats update of distribution and residency stats. Change-Id: Id086090a2ed720c9fcb37812a3c98f0f724907c6
2016-06-06 18:16:43 +02:00
# Provide initial power state, should ideally get redefined in startup
# routine
default_p_state = Param.PwrState("UNDEFINED", "Default Power State")
p_state_clk_gate_min = Param.Latency('1ns',"Min value of the distribution")
p_state_clk_gate_max = Param.Latency('1s',"Max value of the distribution")
p_state_clk_gate_bins = Param.Unsigned('20',
"# bins in clk gated distribution")
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