122 lines
7.7 KiB
Text
122 lines
7.7 KiB
Text
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Change Log:
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DRAMPower v4.0 - * DRAMPower can now be compiled as a library. This enables a user
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to access the tool through an API and log commands and their
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corresponding time stamps, removing the need to store large
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command traces on disk. In addition, cycle counting variables
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have been changed to int64 to support longer simulations.
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The library can be compiled without Xerces to remove an optional
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dependency and reduce the size of the binary.
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* Improved robustness. The latest build is automatically checked
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out on a test server, compiled, and tested to verify that the
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output matches an expected reference. The code is also compiled
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with a large number of warning flags enabled and treats all
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warnings as errors.
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* Bug fix: Fixed bug in io/termination energy calculation.
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* Bug fix: Fixed bug in calculation of auto precharge cycle.
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DRAMPower v3.1 - * Added IO and Termination Power measures from Micron's DRAM Power
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Calculator, for all supported DRAM generations. In the case of
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Wide IO DRAMs, these measures are already included in the provided
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current specifications. This feature enables support for multi-rank
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DRAM DIMMs (DDR2/3/4) and stacking of multiple Wide IO DRAM dies
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(equivalent to ranks). To indicate use of multi-rank DRAMs or
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multiple Wide IO DRAM dies/layers, the 'nbrOfRanks' parameter in
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the memory specification XMLs can be employed. Note: The DRAM
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command scheduler does not support multi-rank/multi-die DRAMs yet.
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Only the power estimation component of DRAMPower has been updated
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to support them. The current measures for dual-rank DRAMs only
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reflect those for the active rank and not the idle rank. The
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default state of the idle rank is assumed to be the same as the
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current memory state, for background power estimation. Hence,
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rank information in the command trace is not required.
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* Added warning messages: New warning messages are provided, to
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identify if the memory or bank state is inconsistent in the
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user-defined traces. Towards this, a state check is performed on
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every memory command issued.
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* Improved run-time options: Users can now point directly to the
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memory specification XML, instead of just the memory ID. Also,
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users can optionally include IO and termination power estimates
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(for both single and dual rank DRAMs) using '-r' flag in the
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command line options.
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* Bug fixes: (1) Refresh handler in the DRAM Command Scheduler was
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kept ON in the Self-Refresh mode, when it can be turned OFF. This
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bug has now been fixed. (2) Precharge All (PREA) always considered
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precharging of all banks. It has now been modified to consider
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precharging of the open/active banks alone.
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DRAMPower v3.0 - * Added support for LPDDR3 and DDR4 memories, besides the already
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supported DDR2/DDR3, LPDDR/LPDDR2 and WIDE IO DRAM memories.
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* Added DRAM Command Scheduler: To support users of DRAMPower
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without access to DRAM controllers, we have added a simple DRAM
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command scheduler that dynamically schedules DRAM commands as if
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it were a memory controller. The scheduler assumes closed-page
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policy, employs ASAP scheduling for DRAM commands (i.e. schedules
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commands as soon as timing constraints are met), performs FCFS
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scheduling on DRAM transactions and supports all the different
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DRAM generations supported by the power model. The generated DRAM
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command schedule is also analyzable for real-time applications.
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Users can also select speculative usage of power-down or
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self-refresh modes (if needed) for idle periods between
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transactions. It should be noted that using this command scheduler
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is optional and it can be (de-)selected during run-time and users
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can switch back to the previously used DRAM command interface as
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in the earlier versions.
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* Improved run-time options: Users can specify the memory and the
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trace file to be used by DRAMPower using command line options.
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Additionally, if the DRAM command scheduler is being used, the
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users can specify the degree of bank interleaving required, the
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request size and power-down or self-refresh options. Also, for
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DDR4 memories the bank group interleaving can be specified using
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command line options.
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* Bug fixes: (1) For command traces ending with a RD/WR/RDA/WRA
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command, the tool did not consider completion of operations when
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estimating the total trace energy. The missing cycles are now
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taken into account.
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(2) The IDD5 (REF current) specification for WIDE IO SDR memory
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specifications only included 2 banks for refreshes instead of all
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four. We would like to thank David Roberts from AMD for spotting
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the issue in our DATE'13 article. These measures have been updated.
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(3) When estimating precharge cycle for commands with
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auto-precharge, (RDA/WRA), the command analysis tool employed the
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last activation cycle in the entire DRAM instead of the particular
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DRAM bank. This bug has been fixed in this release.
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DRAMPower v2.1 - * Added support for variation-aware power estimation, for a
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selection of DDR3 memories manufactured using 50nm process
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technology, based on the Monte-Carlo analysis presented in our
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DAC'13 article.
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DRAMPower v2.0 - * Added support for LPDDR/LPDDR2 and WIDE IO DRAM memories, besides
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the already supported DDR2/DDR3 memories.
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* Faster analysis: The trace analysis component in DRAMPower v2.0
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triggers the evaluation only during memory state transitions
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(between active, precharged, active and precharged power-down,
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refresh, self-refresh and power-up states) and not on every clock
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cycle, as was the case till the last version. This optimization
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speeds up the power simulations using DRAMPower by several times
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over cycle-accurate analysis, resulting in fast power analysis,
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without affecting the accuracy of the trace analysis or the
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reported power and energy estimates.
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* Verification effort: Our power model was verified by the
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Microelectronic System Design group at TU Kaiserslautern using
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circuit-level SPICE simulations of a DRAM cross-section. As a
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result of this verification effort, a couple of power equations
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have been modified for Refresh and Self-refresh operations. The
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difference between the power and energy estimates reported by our
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updated model and the equivalent circuit-level simulations is
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< 2% for all memory operations of any granularity for all memories
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supported by DRAMPower.
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DRAMPower v1.2 - * Supports different power-down and self-refresh modes in DDR2 and
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DDR3 DRAM memories.
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* Bug fix: Refresh power consumption equation in DRAMPower v1,
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incorrectly subtracted IDD2n (precharge background current)
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instead of IDD3n (active background current) from IDD5 (total
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refresh current). This error has been rectified in this version.
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DRAMPower v1.0 - * Performs cycle-accurate memory command trace analysis and estimates
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power and energy consumption numbers for the trace.
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* It supports the basic memory operations like read, write, refresh,
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activate and (auto) precharge in DDR2 and DDR3 memories.
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