
---------- Begin Simulation Statistics ----------
sim_seconds                                  2.854926                       # Number of seconds simulated
sim_ticks                                2854925996500                       # Number of ticks simulated
final_tick                               2854925996500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 259837                       # Simulator instruction rate (inst/s)
host_op_rate                                   314167                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6622138542                       # Simulator tick rate (ticks/s)
host_mem_usage                                 588096                       # Number of bytes of host memory used
host_seconds                                   431.12                       # Real time elapsed on the host
sim_insts                                   112020669                       # Number of instructions simulated
sim_ops                                     135443008                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker         7040                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1667200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9190572                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10865900                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1667200                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1667200                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7979712                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7997236                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker          110                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26050                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             144124                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                170301                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          124683                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               129064                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           2466                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               583973                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3219198                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              336                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3806018                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          583973                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             583973                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2795068                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6138                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2801206                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2795068                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2466                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              583973                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3225336                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             336                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6607224                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        170301                       # Number of read requests accepted
system.physmem.writeReqs                       129064                       # Number of write requests accepted
system.physmem.readBursts                      170301                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     129064                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10890496                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8768                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8010048                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10865900                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7997236                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      137                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10638                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10529                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10665                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10242                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13390                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10196                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10392                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10920                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10199                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10416                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10277                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9652                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10777                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11476                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10256                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10139                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7926                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7916                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8341                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7830                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7635                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7427                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7524                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8090                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7812                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7846                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7622                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7450                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8154                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8593                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7575                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7416                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          56                       # Number of times write queue was full causing retry
system.physmem.totGap                    2854925546000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  169744                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 124683                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    160221                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      9636                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       294                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1833                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2641                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5947                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6539                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6191                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6635                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6984                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7561                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7557                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9006                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7531                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7083                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6851                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      453                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      463                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      366                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      270                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      254                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      268                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      256                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      235                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      231                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      214                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      138                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        60414                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      312.849340                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     185.889118                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     328.883375                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          21657     35.85%     35.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14616     24.19%     60.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6864     11.36%     71.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3516      5.82%     77.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2636      4.36%     81.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1611      2.67%     84.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1067      1.77%     86.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          953      1.58%     87.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7494     12.40%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          60414                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6196                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.463041                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      582.417033                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6195     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6196                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6196                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.199645                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.300177                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       15.412164                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5485     88.52%     88.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              67      1.08%     89.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              43      0.69%     90.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              35      0.56%     90.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             272      4.39%     95.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              29      0.47%     95.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43               8      0.13%     95.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              11      0.18%     96.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              11      0.18%     96.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               3      0.05%     96.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               4      0.06%     96.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               7      0.11%     96.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             138      2.23%     98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               3      0.05%     98.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               2      0.03%     98.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               7      0.11%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               6      0.10%     98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.02%     98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.02%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            13      0.21%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             2      0.03%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.05%     99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            12      0.19%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             6      0.10%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             4      0.06%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.05%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             2      0.03%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.02%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.02%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             3      0.05%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.02%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.02%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             4      0.06%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             4      0.06%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6196                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4595967000                       # Total ticks spent queuing
system.physmem.totMemAccLat                7786542000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    850820000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       27009.04                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  45759.04                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.81                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.81                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.80                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.01                       # Average write queue length when enqueuing
system.physmem.readRowHits                     140583                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     94323                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.62                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.35                       # Row buffer hit rate for writes
system.physmem.avgGap                      9536604.30                       # Average gap between requests
system.physmem.pageHitRate                      79.54                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  218405460                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  116085255                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 620980080                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                327236580                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           6016710960.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             4587085260                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              376629120                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       12457025670                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        8414413920                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       671932680540                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             705069857835                       # Total energy per rank (pJ)
system.physmem_0.averagePower              246.966071                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           2843548486750                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      708499000                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2558586000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   2794649429000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  21912527500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      7778804250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  27318150750                       # Time in different power states
system.physmem_1.actEnergy                  212957640                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  113185875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 593990880                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                326082960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           6113824080.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             4455367380                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              374460480                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       12365716800                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        8661645120                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       671979444945                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             705199696980                       # Total energy per rank (pJ)
system.physmem_1.averagePower              247.011550                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           2844173514000                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      705782750                       # Time in different power states
system.physmem_1.memoryStateTime::REF      2600572000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   2794499397250                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN  22556418250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      7446062750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  27117763500                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          179                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             179                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                31074836                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16867509                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           2481345                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18655029                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                10408802                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             55.796225                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 7856601                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1514233                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         3068747                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            2872226                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses           196521                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       109392                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                     68070                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                68070                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1        44787                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23283                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples        68070                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0           68070    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total        68070                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7877                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 10134.378571                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean  8445.879455                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  9567.630419                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535         7869     99.90%     99.90% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071            6      0.08%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7877                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    276581000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       276581000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    276581000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6513     82.68%     82.68% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1364     17.32%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7877                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        68070                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total        68070                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7877                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7877                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        75947                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24743648                       # DTB read hits
system.cpu.dtb.read_misses                      61017                       # DTB read misses
system.cpu.dtb.write_hits                    19435570                       # DTB write hits
system.cpu.dtb.write_misses                      7053                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4279                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1461                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1806                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       755                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24804665                       # DTB read accesses
system.cpu.dtb.write_accesses                19442623                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44179218                       # DTB hits
system.cpu.dtb.misses                           68070                       # DTB misses
system.cpu.dtb.accesses                      44247288                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                      5855                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 5855                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          322                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         5533                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         5855                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            5855    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         5855                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3194                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 10424.389480                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean  8603.860466                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  6932.586443                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191         1846     57.80%     57.80% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383          798     24.98%     82.78% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575          544     17.03%     99.81% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::24576-32767            5      0.16%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::90112-98303            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3194                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    276141500                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       276141500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    276141500                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2884     90.29%     90.29% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           310      9.71%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3194                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5855                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         5855                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3194                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3194                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         9049                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                     57481594                       # ITB inst hits
system.cpu.itb.inst_misses                       5855                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2915                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      8308                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 57487449                       # ITB inst accesses
system.cpu.itb.hits                          57481594                       # DTB hits
system.cpu.itb.misses                            5855                       # DTB misses
system.cpu.itb.accesses                      57487449                       # DTB accesses
system.cpu.numPwrStateTransitions                6066                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples          3033                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     887934091.386746                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    17437787888.707882                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows         2968     97.86%     97.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10           59      1.95%     99.80% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.03%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.03%     99.90% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 499966196768                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total            3033                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    161821897324                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 2693104099176                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        323646748                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   112020669                       # Number of instructions committed
system.cpu.committedOps                     135443008                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       7814596                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      3033                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   5386269471                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.889170                       # CPI: cycles per instruction
system.cpu.ipc                               0.346120                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                2337      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu                90804901     67.04%     67.04% # Class of committed instruction
system.cpu.op_class_0::IntMult                 113201      0.08%     67.13% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatMisc                    0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc             8481      0.01%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.13% # Class of committed instruction
system.cpu.op_class_0::MemRead               24247912     17.90%     85.04% # Class of committed instruction
system.cpu.op_class_0::MemWrite              20254880     14.95%     99.99% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead              2708      0.00%     99.99% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite             8588      0.01%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                135443008                       # Class of committed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
system.cpu.tickCycles                       217947056                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       105699692                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements            844723                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.945160                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42637807                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            845235                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             50.444914                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         330588500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.945160                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999893                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999893                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          360                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         176206878                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        176206878                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     23101260                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23101260                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18273431                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18273431                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       356861                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        356861                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443340                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443340                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460050                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460050                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41374691                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41374691                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     41731552                       # number of overall hits
system.cpu.dcache.overall_hits::total        41731552                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       465078                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        465078                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       548776                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       548776                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       169103                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       169103                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22503                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22503                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      1013854                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1013854                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1182957                       # number of overall misses
system.cpu.dcache.overall_misses::total       1182957                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   7334484000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   7334484000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  26875060480                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  26875060480                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    306737000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    306737000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       171000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       171000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  34209544480                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  34209544480                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  34209544480                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  34209544480                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23566338                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23566338                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     18822207                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18822207                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       525964                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       525964                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465843                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       465843                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460052                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460052                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42388545                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42388545                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42914509                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42914509                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.019735                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.019735                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029156                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.029156                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.321511                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.321511                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048306                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048306                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.023918                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.023918                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.027565                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.027565                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15770.438507                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15770.438507                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48972.732918                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48972.732918                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13630.938097                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13630.938097                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        85500                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        85500                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33742.081680                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 33742.081680                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28918.671160                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28918.671160                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          224                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                21                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.666667                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       702249                       # number of writebacks
system.cpu.dcache.writebacks::total            702249                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        45641                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        45641                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249535                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       249535                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14278                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        14278                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       295176                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       295176                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       295176                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       295176                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       419437                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       419437                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299241                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       299241                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121149                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       121149                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8225                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8225                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       718678                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       718678                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       839827                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       839827                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31130                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6447841000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6447841000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14303453000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  14303453000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1653166500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1653166500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    121747500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    121747500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       169000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       169000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  20751294000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  20751294000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22404460500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  22404460500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6305636000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6305636000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6305636000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6305636000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017798                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017798                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015898                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015898                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230337                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230337                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017656                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017656                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016955                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016955                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019570                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019570                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15372.608997                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15372.608997                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47799.108411                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47799.108411                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13645.729639                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13645.729639                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14802.127660                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14802.127660                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        84500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        84500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28874.258013                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28874.258013                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26677.471074                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26677.471074                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202558.175394                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202558.175394                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107395.782948                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107395.782948                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements           2891615                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.370867                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            54580851                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           2892127                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             18.872218                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       16116545500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.370867                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998771                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998771                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          193                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          60365128                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         60365128                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     54580851                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        54580851                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      54580851                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         54580851                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     54580851                       # number of overall hits
system.cpu.icache.overall_hits::total        54580851                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      2892139                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       2892139                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      2892139                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        2892139                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      2892139                       # number of overall misses
system.cpu.icache.overall_misses::total       2892139                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  39804335500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  39804335500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  39804335500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  39804335500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  39804335500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  39804335500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     57472990                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     57472990                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     57472990                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     57472990                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     57472990                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     57472990                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050322                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.050322                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.050322                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.050322                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.050322                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.050322                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13762.939990                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13762.939990                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13762.939990                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13762.939990                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13762.939990                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13762.939990                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks      2891615                       # number of writebacks
system.cpu.icache.writebacks::total           2891615                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2892139                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      2892139                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      2892139                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      2892139                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      2892139                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      2892139                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3119                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         3119                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3119                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         3119                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36912197500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  36912197500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36912197500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  36912197500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36912197500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  36912197500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    265216500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    265216500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    265216500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    265216500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050322                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050322                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050322                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.050322                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050322                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.050322                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12762.940336                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12762.940336                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12762.940336                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12762.940336                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12762.940336                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12762.940336                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements            97098                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65145.315179                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            7321379                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           162490                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            45.057413                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     271905816000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    69.248317                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.032949                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 12118.407979                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 52957.625933                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001057                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000001                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.184912                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.808069                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.994039                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           50                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65342                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           50                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2           63                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4586                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        60692                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000763                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997040                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         60089878                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        60089878                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        68391                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3372                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          71763                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks       702249                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       702249                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      2840964                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      2840964                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         2784                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         2784                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       166689                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       166689                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2869145                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      2869145                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       534458                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       534458                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        68391                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         3372                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      2869145                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       701147                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3642055                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        68391                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         3372                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      2869145                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       701147                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3642055                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          110                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          112                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       129768                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       129768                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22956                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        22956                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14347                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        14347                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker          110                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        22956                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       144115                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        167183                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker          110                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        22956                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       144115                       # number of overall misses
system.cpu.l2cache.overall_misses::total       167183                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     35753500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       193000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     35946500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       174000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       174000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       166000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       166000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12066822500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  12066822500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2380927500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2380927500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1746972000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1746972000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     35753500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       193000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2380927500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  13813794500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  16230668500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     35753500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       193000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2380927500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  13813794500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  16230668500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        68501                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3374                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        71875                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks       702249                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       702249                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      2840964                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      2840964                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2790                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2790                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       296457                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       296457                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      2892101                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      2892101                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       548805                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       548805                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        68501                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         3374                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      2892101                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       845262                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      3809238                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        68501                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         3374                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      2892101                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       845262                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      3809238                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001606                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000593                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.001558                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.002151                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.002151                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.437730                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.437730                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007937                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007937                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026142                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026142                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001606                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000593                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007937                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.170497                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.043889                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001606                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000593                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007937                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.170497                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.043889                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 325031.818182                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        96500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 320950.892857                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        29000                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        29000                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        83000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        83000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92987.658745                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92987.658745                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103717.002091                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103717.002091                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121765.665296                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121765.665296                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 325031.818182                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        96500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103717.002091                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95852.579537                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 97083.247100                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 325031.818182                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        96500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103717.002091                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95852.579537                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 97083.247100                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        88493                       # number of writebacks
system.cpu.l2cache.writebacks::total            88493                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           14                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           14                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          145                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          145                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          145                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          159                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           14                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          145                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          159                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          110                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          112                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       129768                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       129768                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22942                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22942                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14202                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14202                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          110                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        22942                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       143970                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       167024                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          110                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        22942                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143970                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       167024                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3119                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34249                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3119                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61833                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     34653500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       173000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     34826500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       114000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       114000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       146000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       146000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  10769142500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  10769142500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2149471500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2149471500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1592398000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1592398000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     34653500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       173000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2149471500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12361540500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  14545838500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     34653500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       173000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2149471500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12361540500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  14545838500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    216819500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5916431500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6133251000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    216819500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5916431500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6133251000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001606                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000593                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001558                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.002151                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.002151                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.437730                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.437730                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007933                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007933                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025878                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025878                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001606                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000593                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007933                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.170326                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.043847                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001606                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000593                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007933                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.170326                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.043847                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        86500                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 310950.892857                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        19000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        19000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        73000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        73000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82987.658745                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82987.658745                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93691.548252                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93691.548252                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 112124.911984                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112124.911984                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        86500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93691.548252                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85861.919150                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87088.313656                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        86500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93691.548252                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85861.919150                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87088.313656                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190055.621587                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179078.250460                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100766.963586                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99190.577847                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests      7507397                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      3770030                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58003                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          175                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          175                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq         136990                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3578080                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       790742                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      2891615                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       151079                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2790                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2792                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       296457                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       296457                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      2892139                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       549026                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq         4412                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8682092                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2658406                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14762                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       159854                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          11515114                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    370357376                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     99233193                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        13496                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       274004                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          469878069                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      132782                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               5798856                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      4006498                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.022233                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.147442                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3917420     97.78%     97.78% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              89078      2.22%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4006498                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     7428208500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       281377                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    4343459350                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1314433554                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      11390994                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      91384437                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             46308000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               327000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                30000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                14000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                88500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               618500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               22000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               52000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6088500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            39091500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187755828                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.033906                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         272036495000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.033906                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064619                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064619                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36458                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36458                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36458                       # number of overall misses
system.iocache.overall_misses::total            36458                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     37411877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     37411877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4363182951                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4363182951                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4400594828                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4400594828                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4400594828                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4400594828                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36458                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36458                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36458                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36458                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 159879.816239                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 159879.816239                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120450.059381                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120450.059381                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 120703.133140                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 120703.133140                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 120703.133140                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 120703.133140                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36458                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36458                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36458                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36458                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     25711877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     25711877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2549871160                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2549871160                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2575583037                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2575583037                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2575583037                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2575583037                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109879.816239                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 109879.816239                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.761263                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.761263                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70645.209200                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70645.209200                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70645.209200                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70645.209200                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests        337068                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       138136                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          489                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               34249                       # Transaction distribution
system.membus.trans_dist::ReadResp              71739                       # Transaction distribution
system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       124683                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8839                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              128                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129646                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129646                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         37490                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2074                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446846                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       554414                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 627311                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16546016                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16709801                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19026921                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              505                       # Total snoops (count)
system.membus.snoopTraffic                      32192                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            265323                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.018540                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.134893                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  260404     98.15%     98.15% # Request fanout histogram
system.membus.snoop_fanout::1                    4919      1.85%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              265323                       # Request fanout histogram
system.membus.reqLayer0.occupancy            92820000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                8000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1700500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           905922529                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          989794500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1230123                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------
