
---------- Begin Simulation Statistics ----------
sim_seconds                                 47.554910                       # Number of seconds simulated
sim_ticks                                47554910274000                       # Number of ticks simulated
final_tick                               47554910274000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 271941                       # Simulator instruction rate (inst/s)
host_op_rate                                   319891                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            14743065549                       # Simulator tick rate (ticks/s)
host_mem_usage                                 772792                       # Number of bytes of host memory used
host_seconds                                  3225.58                       # Real time elapsed on the host
sim_insts                                   877166784                       # Number of instructions simulated
sim_ops                                    1031833041                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       127616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       113728                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          7300032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         13854920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     13786176                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       105536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        93440                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3887680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          9545552                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     11958848                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        442112                       # Number of bytes read from this memory
system.physmem.bytes_read::total             61215640                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      7300032                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3887680                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        11187712                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     74339904                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          74360488                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1994                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1777                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst            114063                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            216496                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       215409                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1649                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1460                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             60745                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            149162                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       186857                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6908                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                956520                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1161561                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1164135                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2684                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2392                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              153507                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              291346                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       289900                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2219                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          1965                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               81751                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              200727                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       251475                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9297                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1287262                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         153507                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          81751                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             235259                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1563243                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1563676                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1563243                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2684                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2392                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             153507                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             291778                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       289900                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2219                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         1965                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              81751                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             200727                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       251475                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9297                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2850939                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        956520                       # Number of read requests accepted
system.physmem.writeReqs                      1164135                       # Number of write requests accepted
system.physmem.readBursts                      956520                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1164135                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 61192448                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     24832                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  74357824                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  61215640                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               74360488                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      388                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2263                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               50657                       # Per bank write bursts
system.physmem.perBankRdBursts::1               60930                       # Per bank write bursts
system.physmem.perBankRdBursts::2               49716                       # Per bank write bursts
system.physmem.perBankRdBursts::3               55090                       # Per bank write bursts
system.physmem.perBankRdBursts::4               56536                       # Per bank write bursts
system.physmem.perBankRdBursts::5               68947                       # Per bank write bursts
system.physmem.perBankRdBursts::6               58003                       # Per bank write bursts
system.physmem.perBankRdBursts::7               60908                       # Per bank write bursts
system.physmem.perBankRdBursts::8               53263                       # Per bank write bursts
system.physmem.perBankRdBursts::9              106420                       # Per bank write bursts
system.physmem.perBankRdBursts::10              50504                       # Per bank write bursts
system.physmem.perBankRdBursts::11              59458                       # Per bank write bursts
system.physmem.perBankRdBursts::12              56712                       # Per bank write bursts
system.physmem.perBankRdBursts::13              60494                       # Per bank write bursts
system.physmem.perBankRdBursts::14              55357                       # Per bank write bursts
system.physmem.perBankRdBursts::15              53137                       # Per bank write bursts
system.physmem.perBankWrBursts::0               68064                       # Per bank write bursts
system.physmem.perBankWrBursts::1               74120                       # Per bank write bursts
system.physmem.perBankWrBursts::2               68663                       # Per bank write bursts
system.physmem.perBankWrBursts::3               72095                       # Per bank write bursts
system.physmem.perBankWrBursts::4               73476                       # Per bank write bursts
system.physmem.perBankWrBursts::5               80505                       # Per bank write bursts
system.physmem.perBankWrBursts::6               71958                       # Per bank write bursts
system.physmem.perBankWrBursts::7               74882                       # Per bank write bursts
system.physmem.perBankWrBursts::8               69253                       # Per bank write bursts
system.physmem.perBankWrBursts::9               72875                       # Per bank write bursts
system.physmem.perBankWrBursts::10              68876                       # Per bank write bursts
system.physmem.perBankWrBursts::11              75926                       # Per bank write bursts
system.physmem.perBankWrBursts::12              72095                       # Per bank write bursts
system.physmem.perBankWrBursts::13              75544                       # Per bank write bursts
system.physmem.perBankWrBursts::14              71950                       # Per bank write bursts
system.physmem.perBankWrBursts::15              71559                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         408                       # Number of times write queue was full causing retry
system.physmem.totGap                    47554908178500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  956490                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1161561                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    589555                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    157739                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     46445                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     36293                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     27945                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     25583                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     23391                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     20914                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     18402                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      4361                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1587                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1163                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      874                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      609                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      336                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      287                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      249                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      205                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       84                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    24143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    31849                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    48338                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    55864                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    61058                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    64206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    66032                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    67782                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    70569                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    70728                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    73352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    74938                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    72063                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    70410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    71450                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    74135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    66609                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    62837                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     4834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2922                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2290                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1924                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1530                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1398                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1235                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      995                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      863                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      908                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      855                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      772                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      896                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      763                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      757                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      750                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      714                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      740                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      794                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      717                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                     1309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                     1089                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      933                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       917155                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      147.793592                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      99.753334                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     195.501852                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         602356     65.68%     65.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       188931     20.60%     86.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        45653      4.98%     91.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        20839      2.27%     93.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        15350      1.67%     95.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         9574      1.04%     96.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         6849      0.75%     96.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5486      0.60%     97.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        22117      2.41%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         917155                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         56545                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        16.908586                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      165.794592                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          56543    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::29696-30719            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           56545                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         56545                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.547193                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.712168                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       14.106429                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           48673     86.08%     86.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            2227      3.94%     90.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             713      1.26%     91.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             569      1.01%     92.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             930      1.64%     93.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             406      0.72%     94.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             286      0.51%     95.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47             280      0.50%     95.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             183      0.32%     95.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             127      0.22%     96.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59             115      0.20%     96.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63             143      0.25%     96.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             579      1.02%     97.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71             140      0.25%     97.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75             130      0.23%     98.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             128      0.23%     98.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             106      0.19%     98.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              75      0.13%     98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91              85      0.15%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95              94      0.17%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99              75      0.13%     99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103            62      0.11%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107            61      0.11%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            71      0.13%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115            39      0.07%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119            37      0.07%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123            45      0.08%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127            34      0.06%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            51      0.09%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135            18      0.03%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139            12      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143            17      0.03%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             4      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             3      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             3      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             3      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           56545                       # Writes before turning the bus around for reads
system.physmem.totQLat                    49127716705                       # Total ticks spent queuing
system.physmem.totMemAccLat               67055191705                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4780660000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       51381.73                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  70131.73                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.29                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.29                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.56                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.24                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.69                       # Average write queue length when enqueuing
system.physmem.readRowHits                     713884                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    486930                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.66                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  41.91                       # Row buffer hit rate for writes
system.physmem.avgGap                     22424632.10                       # Average gap between requests
system.physmem.pageHitRate                      56.70                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3312517320                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1760633325                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3290019180                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3047242860                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           39654114240.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            43514746200                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             2086179840                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       77547983010                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy       55697482080                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       11319929946090                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             11549857795695                       # Total energy per rank (pJ)
system.physmem_0.averagePower              242.874137                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           47454012976233                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE     3696049077                       # Time in different power states
system.physmem_0.memoryStateTime::REF     16847240000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   47138905885000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 145045339612                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     80353958440                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 170061801871                       # Time in different power states
system.physmem_1.actEnergy                 3235997940                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1719969900                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3536763300                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3017567160                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           38496747120.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            44079949650                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             2012350560                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       72751641060                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy       54144086400                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       11323086477345                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             11546099446905                       # Total energy per rank (pJ)
system.physmem_1.averagePower              242.795105                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           47452962329328                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE     3512995347                       # Time in different power states
system.physmem_1.memoryStateTime::REF     16356664000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   47152420144750                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 141000345458                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     82076677575                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 159543446870                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          640                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1388                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          640                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1344                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           10                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             27                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           15                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           13                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               29                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           15                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           13                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           28                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           15                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           13                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              29                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              137627857                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         96352530                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          6353129                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups           102612546                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               71378761                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            69.561436                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               16463463                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect           1088270                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        3669510                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           2436336                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses         1233174                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted       447439                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   282889                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               282889                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         9418                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        82700                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples       282889                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         282889    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       282889                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        92118                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 24516.006644                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 22528.646157                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 18042.498572                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535        90947     98.73%     98.73% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          867      0.94%     99.67% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          159      0.17%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           56      0.06%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           44      0.05%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           20      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359           17      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        92118                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1049600704                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     1049600704    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1049600704                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        82700     89.78%     89.78% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M         9418     10.22%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        92118                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       282889                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       282889                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        92118                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        92118                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       375007                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    87675894                       # DTB read hits
system.cpu0.dtb.read_misses                    234519                       # DTB read misses
system.cpu0.dtb.write_hits                   78239753                       # DTB write hits
system.cpu0.dtb.write_misses                    48370                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              40666                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   38151                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     2038                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  9397                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    11689                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                87910413                       # DTB read accesses
system.cpu0.dtb.write_accesses               78288123                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        165915647                       # DTB hits
system.cpu0.dtb.misses                         282889                       # DTB misses
system.cpu0.dtb.accesses                    166198536                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    69273                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                69273                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          583                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        61330                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        69273                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          69273    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        69273                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        61913                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 26255.972090                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24021.087370                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 22669.077424                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        60695     98.03%     98.03% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          852      1.38%     99.41% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          248      0.40%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           49      0.08%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           14      0.02%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           11      0.02%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            4      0.01%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            1      0.00%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359           39      0.06%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        61913                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1048830204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1048830204    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1048830204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        61330     99.06%     99.06% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          583      0.94%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        61913                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        69273                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        69273                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        61913                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        61913                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       131186                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   244690597                       # ITB inst hits
system.cpu0.itb.inst_misses                     69273                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              40666                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   27059                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   167788                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               244759870                       # ITB inst accesses
system.cpu0.itb.hits                        244690597                       # DTB hits
system.cpu0.itb.misses                          69273                       # DTB misses
system.cpu0.itb.accesses                    244759870                       # DTB accesses
system.cpu0.numPwrStateTransitions              27904                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples        13952                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    3372797482.084218                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   110921496988.059006                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         3863     27.69%     27.69% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10        10067     72.15%     99.84% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11           11      0.08%     99.92% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.93% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.94% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11            1      0.01%     99.94% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows            8      0.06%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 7351146409252                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total          13952                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   497639803961                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 47057270470039                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       995321471                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  452001209                       # Number of instructions committed
system.cpu0.committedOps                    531851100                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                     46239027                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     5092                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                 94115325169                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.202033                       # CPI: cycles per instruction
system.cpu0.ipc                              0.454126                       # IPC: instructions per cycle
system.cpu0.op_class_0::No_OpClass                  1      0.00%      0.00% # Class of committed instruction
system.cpu0.op_class_0::IntAlu              368287155     69.25%     69.25% # Class of committed instruction
system.cpu0.op_class_0::IntMult               1118982      0.21%     69.46% # Class of committed instruction
system.cpu0.op_class_0::IntDiv                  57276      0.01%     69.47% # Class of committed instruction
system.cpu0.op_class_0::FloatAdd                    8      0.00%     69.47% # Class of committed instruction
system.cpu0.op_class_0::FloatCmp                   13      0.00%     69.47% # Class of committed instruction
system.cpu0.op_class_0::FloatCvt                   21      0.00%     69.47% # Class of committed instruction
system.cpu0.op_class_0::FloatMult                   0      0.00%     69.47% # Class of committed instruction
system.cpu0.op_class_0::FloatMultAcc                0      0.00%     69.47% # Class of committed instruction
system.cpu0.op_class_0::FloatDiv                    0      0.00%     69.47% # Class of committed instruction
system.cpu0.op_class_0::FloatMisc               85306      0.02%     69.48% # Class of committed instruction
system.cpu0.op_class_0::FloatSqrt                   0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdAdd                     0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdAlu                     0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdCmp                     0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdCvt                     0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdMisc                    0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdMult                    0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdShift                   0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdSqrt                    0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAdd                0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCmp                0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCvt                0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMisc               0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMult               0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     69.48% # Class of committed instruction
system.cpu0.op_class_0::MemRead              84333617     15.86%     85.34% # Class of committed instruction
system.cpu0.op_class_0::MemWrite             77481840     14.57%     99.91% # Class of committed instruction
system.cpu0.op_class_0::FloatMemRead            68467      0.01%     99.92% # Class of committed instruction
system.cpu0.op_class_0::FloatMemWrite          418414      0.08%    100.00% # Class of committed instruction
system.cpu0.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
system.cpu0.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
system.cpu0.op_class_0::total               531851100                       # Class of committed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13952                       # number of quiesce instructions executed
system.cpu0.tickCycles                      729574114                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                      265747357                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements          5787900                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          490.209920                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          157471988                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5788412                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.204696                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       5354308000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   490.209920                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.957441                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.957441                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          397                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        334937152                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       334937152                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     80549957                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       80549957                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     72496805                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      72496805                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       269794                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       269794                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       177007                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       177007                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1734640                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1734640                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1715473                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1715473                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    153223769                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       153223769                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    153493563                       # number of overall hits
system.cpu0.dcache.overall_hits::total      153493563                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3263198                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3263198                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      2445366                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2445366                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       673099                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       673099                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       844507                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       844507                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       169054                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       169054                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       187078                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       187078                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      6553071                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       6553071                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      7226170                       # number of overall misses
system.cpu0.dcache.overall_misses::total      7226170                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  52395902500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  52395902500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  52490790500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  52490790500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  27335813500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  27335813500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2555333500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2555333500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4463485500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4463485500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2023000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2023000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 132222506500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 132222506500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 132222506500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 132222506500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     83813155                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     83813155                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     74942171                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     74942171                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       942893                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       942893                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1021514                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1021514                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1903694                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      1903694                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1902551                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      1902551                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    159776840                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    159776840                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    160719733                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    160719733                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.038934                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.038934                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.032630                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.032630                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.713866                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.713866                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.826721                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.826721                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088803                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088803                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098330                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098330                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.041014                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.041014                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.044961                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.044961                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16056.611490                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16056.611490                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21465.412744                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 21465.412744                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32368.960234                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32368.960234                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15115.486768                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15115.486768                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23858.954554                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23858.954554                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20177.182042                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20177.182042                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18297.729849                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18297.729849                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      5787917                       # number of writebacks
system.cpu0.dcache.writebacks::total          5787917                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       205447                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       205447                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1015907                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1015907                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           99                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total           99                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        45884                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        45884                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           37                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total           37                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1221453                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1221453                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1221453                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1221453                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3057751                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3057751                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1429459                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1429459                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       670780                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       670780                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       844408                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       844408                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       123170                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       123170                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       187041                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       187041                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      5331618                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5331618                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      6002398                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      6002398                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31212                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31212                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        30755                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        30755                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        61967                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        61967                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  44254087500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  44254087500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  29600010500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  29600010500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  15858321000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  15858321000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  26484603000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  26484603000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1676878500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1676878500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4275603000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4275603000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1773000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1773000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 100338701000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 100338701000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116197022000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 116197022000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6038825000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6038825000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6038825000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6038825000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036483                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036483                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019074                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019074                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.711406                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.711406                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.826624                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.826624                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064701                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064701                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098311                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098311                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.033369                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.033369                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.037347                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.037347                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14472.757102                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14472.757102                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20707.142003                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20707.142003                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23641.612749                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23641.612749                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31364.699292                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31364.699292                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13614.341966                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13614.341966                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22859.175261                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22859.175261                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18819.559278                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18819.559278                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19358.433413                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19358.433413                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193477.668845                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193477.668845                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97452.272984                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97452.272984                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          9773833                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.928996                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          234741496                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          9774345                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            24.016085                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      22886662000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.928996                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999861                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999861                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          368                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           45                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        498806059                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       498806059                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    234741496                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      234741496                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    234741496                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       234741496                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    234741496                       # number of overall hits
system.cpu0.icache.overall_hits::total      234741496                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      9774356                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      9774356                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      9774356                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       9774356                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      9774356                       # number of overall misses
system.cpu0.icache.overall_misses::total      9774356                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  99441985000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  99441985000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  99441985000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  99441985000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  99441985000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  99441985000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    244515852                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    244515852                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    244515852                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    244515852                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    244515852                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    244515852                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039974                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.039974                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039974                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.039974                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039974                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.039974                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10173.763366                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10173.763366                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10173.763366                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10173.763366                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10173.763366                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10173.763366                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      9773833                       # number of writebacks
system.cpu0.icache.writebacks::total          9773833                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9774356                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      9774356                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      9774356                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      9774356                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      9774356                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      9774356                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52284                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        52284                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52284                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        52284                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  94554807500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  94554807500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  94554807500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  94554807500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  94554807500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  94554807500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5161606000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5161606000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   5161606000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   5161606000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039974                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039974                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039974                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.039974                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039974                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.039974                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9673.763417                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9673.763417                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9673.763417                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9673.763417                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9673.763417                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9673.763417                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98722.477240                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98722.477240                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7608993                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7610336                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         1188                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1005416                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements         2646552                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15691.473570                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          14028250                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2662377                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            5.269070                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      5985886000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15348.189818                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    32.039011                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     8.868609                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   302.376132                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.936779                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.001956                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000541                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.018456                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.957732                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          352                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           63                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15410                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            7                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          163                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3           65                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          117                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           37                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           24                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1727                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         6563                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4041                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2911                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.021484                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003845                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.940552                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       534452534                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      534452534                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       527649                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       180298                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        707947                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      3832122                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      3832122                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks     11726658                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total     11726658                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data            1                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       904488                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       904488                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      9076171                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      9076171                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2875219                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2875219                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       241369                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       241369                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       527649                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       180298                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      9076171                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3779707                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       13563825                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       527649                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       180298                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      9076171                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3779707                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      13563825                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        21665                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        10120                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        31785                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       246294                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       246294                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       187036                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       187036                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       286789                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       286789                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       698184                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       698184                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       976175                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       976175                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       601118                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       601118                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        21665                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker        10120                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       698184                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1262964                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1992933                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        21665                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker        10120                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       698184                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1262964                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1992933                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    696360500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    404225000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   1100585500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    910928500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    910928500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    289294500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    289294500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1705497                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1705497                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  15428607998                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  15428607998                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  25059292500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  25059292500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  37051733995                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  37051733995                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    336301500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total    336301500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    696360500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    404225000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  25059292500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  52480341993                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  78640219993                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    696360500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    404225000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  25059292500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  52480341993                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  78640219993                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       549314                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       190418                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       739732                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3832122                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      3832122                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks     11726658                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total     11726658                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       246295                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       246295                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       187036                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       187036                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1191277                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1191277                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      9774355                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      9774355                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3851394                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3851394                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       842487                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       842487                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       549314                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       190418                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      9774355                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5042671                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     15556758                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       549314                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       190418                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      9774355                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5042671                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     15556758                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.039440                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.053146                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.042968                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999996                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999996                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.240741                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.240741                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.071430                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.071430                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.253460                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.253460                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.713504                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.713504                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.039440                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.053146                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.071430                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.250455                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.128107                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.039440                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.053146                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.071430                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.250455                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.128107                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32142.187861                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39943.181818                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34625.939909                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3698.541174                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3698.541174                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1546.731645                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1546.731645                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 341099.400000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 341099.400000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53797.767690                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53797.767690                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35892.103657                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35892.103657                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37956.036566                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37956.036566                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   559.460039                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   559.460039                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32142.187861                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39943.181818                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35892.103657                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41553.315845                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 39459.540282                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32142.187861                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39943.181818                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35892.103657                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41553.315845                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 39459.540282                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           45829                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks      1629804                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1629804                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker           24                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker           98                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          122                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         8277                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         8277                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           12                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          866                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          866                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            3                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total            3                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker           24                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker           98                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           12                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         9143                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         9277                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker           24                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker           98                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           12                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         9143                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         9277                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        21641                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        10022                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        31663                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       782860                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       782860                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       246294                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       246294                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       187036                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       187036                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       278512                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       278512                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       698172                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       698172                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       975309                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       975309                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       601115                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       601115                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        21641                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        10022                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       698172                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1253821                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1983656                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        21641                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        10022                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       698172                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1253821                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       782860                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2766516                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52284                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31212                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        83496                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        30755                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        30755                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52284                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        61967                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       114251                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    565944000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    342540500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    908484500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  36299233693                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  36299233693                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4539562995                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4539562995                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2868254998                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2868254998                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1441497                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1441497                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  12630779498                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  12630779498                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  20869901000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  20869901000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  31074032995                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  31074032995                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  19885865000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  19885865000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    565944000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    342540500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  20869901000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  43704812493                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  65483197993                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    565944000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    342540500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  20869901000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  43704812493                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  36299233693                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 101782431686                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4743334000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5788958500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  10532292500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4743334000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5788958500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10532292500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.039396                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.052632                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.042803                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999996                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999996                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.233793                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.233793                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.071429                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.071429                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.253235                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.253235                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.713501                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.713501                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.039396                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.052632                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.071429                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.248642                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.127511                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.039396                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.052632                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.071429                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.248642                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.177834                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28692.306478                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46367.465055                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46367.465055                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18431.480243                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18431.480243                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15335.309769                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15335.309769                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 288299.400000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 288299.400000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45350.934602                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45350.934602                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29892.205646                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29892.205646                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31860.705679                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31860.705679                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33081.631635                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33081.631635                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29892.205646                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34857.298205                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33011.367895                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29892.205646                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34857.298205                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46367.465055                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36790.834279                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185472.206203                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126141.282217                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93420.021947                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 92185.560739                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests     31945858                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     16286466                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2971                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       662323                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       662303                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops           20                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        897088                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     14618500                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        30756                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        30755                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5466694                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean     11729628                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      1381452                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1000780                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       445154                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       338634                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       499902                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           83                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1222912                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1199223                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9774356                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4899750                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       895142                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       842487                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     29427111                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18719100                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       397503                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1155819                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         49699533                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side   1254430144                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    699985190                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1523344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4394512                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1960333190                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    5744069                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic            111836388                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples     22520641                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.042476                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.201677                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          21564077     95.75%     95.75% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            956544      4.25%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                20      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      22520641                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   31868357980                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    188944290                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy  14742648604                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8252120363                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    207185798                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    606624760                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              130393488                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         92735412                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          5902942                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            97710710                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               68499677                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            70.104574                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               15029088                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            982146                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        3431599                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           2322480                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses         1109119                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted       398100                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                   266586                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               266586                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         9178                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        75276                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples       266586                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         266586    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       266586                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        84454                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23652.319606                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21901.867132                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 15135.594089                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        83574     98.96%     98.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          653      0.77%     99.73% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          133      0.16%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           39      0.05%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           30      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        84454                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples    112342944                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0      112342944    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total    112342944                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        75276     89.13%     89.13% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         9178     10.87%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        84454                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       266586                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       266586                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        84454                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        84454                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       351040                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    83602508                       # DTB read hits
system.cpu1.dtb.read_misses                    221634                       # DTB read misses
system.cpu1.dtb.write_hits                   72407946                       # DTB write hits
system.cpu1.dtb.write_misses                    44952                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              40666                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   35586                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     1113                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  7045                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10293                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                83824142                       # DTB read accesses
system.cpu1.dtb.write_accesses               72452898                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        156010454                       # DTB hits
system.cpu1.dtb.misses                         266586                       # DTB misses
system.cpu1.dtb.accesses                    156277040                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    60007                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                60007                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          568                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        49765                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        60007                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          60007    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        60007                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        50333                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 25530.089603                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23478.456634                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 19036.287161                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        49435     98.22%     98.22% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          638      1.27%     99.48% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          189      0.38%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           38      0.08%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           10      0.02%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359           14      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        50333                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples    111619444                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0      111619444    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total    111619444                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        49765     98.87%     98.87% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          568      1.13%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        50333                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        60007                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        60007                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        50333                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        50333                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       110340                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   231314016                       # ITB inst hits
system.cpu1.itb.inst_misses                     60007                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              40666                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   25531                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   167507                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               231374023                       # ITB inst accesses
system.cpu1.itb.hits                        231314016                       # DTB hits
system.cpu1.itb.misses                          60007                       # DTB misses
system.cpu1.itb.accesses                    231374023                       # DTB accesses
system.cpu1.numPwrStateTransitions               9626                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         4813                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    9788374174.243299                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   115006828751.685410                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         3303     68.63%     68.63% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         1483     30.81%     99.44% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.02%     99.46% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            1      0.02%     99.48% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            4      0.08%     99.56% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11            1      0.02%     99.58% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            1      0.02%     99.61% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.02%     99.63% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           18      0.37%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 1988779353616                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           4813                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   443465373367                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 47111444900633                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                       886937326                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  425165575                       # Number of instructions committed
system.cpu1.committedOps                    499981941                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                     45360018                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     4813                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                 94223530921                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.086099                       # CPI: cycles per instruction
system.cpu1.ipc                              0.479364                       # IPC: instructions per cycle
system.cpu1.op_class_0::No_OpClass                  0      0.00%      0.00% # Class of committed instruction
system.cpu1.op_class_0::IntAlu              346104827     69.22%     69.22% # Class of committed instruction
system.cpu1.op_class_0::IntMult               1095440      0.22%     69.44% # Class of committed instruction
system.cpu1.op_class_0::IntDiv                  59698      0.01%     69.45% # Class of committed instruction
system.cpu1.op_class_0::FloatAdd                    0      0.00%     69.45% # Class of committed instruction
system.cpu1.op_class_0::FloatCmp                    0      0.00%     69.45% # Class of committed instruction
system.cpu1.op_class_0::FloatCvt                    0      0.00%     69.45% # Class of committed instruction
system.cpu1.op_class_0::FloatMult                   0      0.00%     69.45% # Class of committed instruction
system.cpu1.op_class_0::FloatMultAcc                0      0.00%     69.45% # Class of committed instruction
system.cpu1.op_class_0::FloatDiv                    0      0.00%     69.45% # Class of committed instruction
system.cpu1.op_class_0::FloatMisc               26657      0.01%     69.46% # Class of committed instruction
system.cpu1.op_class_0::FloatSqrt                   0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdAdd                     0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdAlu                     0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdCmp                     0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdCvt                     0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdMisc                    0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdMult                    0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdShift                   0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdSqrt                    0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMisc               0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMult               0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     69.46% # Class of committed instruction
system.cpu1.op_class_0::MemRead              80537576     16.11%     85.57% # Class of committed instruction
system.cpu1.op_class_0::MemWrite             71850356     14.37%     99.94% # Class of committed instruction
system.cpu1.op_class_0::FloatMemRead            41546      0.01%     99.95% # Class of committed instruction
system.cpu1.op_class_0::FloatMemWrite          265841      0.05%    100.00% # Class of committed instruction
system.cpu1.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
system.cpu1.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
system.cpu1.op_class_0::total               499981941                       # Class of committed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    4813                       # number of quiesce instructions executed
system.cpu1.tickCycles                      688160387                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                      198776939                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements          4915770                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          461.565771                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          148821179                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          4916282                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            30.271083                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8378532705500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   461.565771                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.901496                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.901496                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          154                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          267                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        314637839                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       314637839                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data     76998524                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       76998524                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     67544283                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      67544283                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       228025                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       228025                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       143759                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       143759                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1733263                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1733263                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1698082                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1698082                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    144686566                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       144686566                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    144914591                       # number of overall hits
system.cpu1.dcache.overall_hits::total      144914591                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      2997503                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      2997503                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      2132920                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      2132920                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       598160                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       598160                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       396373                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       396373                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       156072                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       156072                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       190006                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       190006                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      5526796                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       5526796                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      6124956                       # number of overall misses
system.cpu1.dcache.overall_misses::total      6124956                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  46710580500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  46710580500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  40169374000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  40169374000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  10226397500                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  10226397500                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2373794500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2373794500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4526922000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4526922000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1761500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1761500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  97106352000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  97106352000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  97106352000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  97106352000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     79996027                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     79996027                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     69677203                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     69677203                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       826185                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       826185                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       540132                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       540132                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1889335                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1889335                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1888088                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1888088                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    150213362                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    150213362                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    151039547                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    151039547                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037471                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.037471                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030611                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.030611                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.724002                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.724002                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.733845                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.733845                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.082607                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.082607                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100634                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100634                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.036793                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.036793                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040552                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.040552                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15583.163887                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15583.163887                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18833.042965                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18833.042965                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25799.934658                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25799.934658                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15209.611590                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15209.611590                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23825.152890                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23825.152890                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17570.098842                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17570.098842                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15854.212177                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15854.212177                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks      4915771                       # number of writebacks
system.cpu1.dcache.writebacks::total          4915771                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       147995                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       147995                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       874601                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       874601                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           58                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total           58                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        38344                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        38344                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           50                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total           50                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1022654                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1022654                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1022654                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1022654                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2849508                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2849508                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1258319                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1258319                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       597912                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       597912                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       396315                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       396315                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       117728                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       117728                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       189956                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       189956                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4504142                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4504142                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5102054                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5102054                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         7183                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         7183                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         7509                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         7509                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        14692                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        14692                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  40476665500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  40476665500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  23125073000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  23125073000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13939684500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13939684500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   9826633500                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total   9826633500                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1586206000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1586206000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4335749000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4335749000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1584500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1584500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  73428372000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  73428372000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  87368056500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  87368056500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    918087500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    918087500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    918087500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    918087500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035621                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035621                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018059                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018059                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.723702                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.723702                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.733737                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.733737                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062312                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.062312                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100608                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100608                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029985                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.029985                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033780                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.033780                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14204.790967                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14204.790967                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18377.750793                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18377.750793                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23313.940011                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23313.940011                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 24795.007759                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 24795.007759                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13473.481245                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13473.481245                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22825.017372                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22825.017372                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16302.410537                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16302.410537                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17124.094825                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17124.094825                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127813.935681                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 127813.935681                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 62488.939559                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 62488.939559                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements          8832346                       # number of replacements
system.cpu1.icache.tags.tagsinuse          507.234959                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          222308626                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          8832858                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            25.168369                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8368864848000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.234959                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990693                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.990693                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           81                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        471115826                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       471115826                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst    222308626                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      222308626                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    222308626                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       222308626                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    222308626                       # number of overall hits
system.cpu1.icache.overall_hits::total      222308626                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      8832858                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      8832858                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      8832858                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       8832858                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      8832858                       # number of overall misses
system.cpu1.icache.overall_misses::total      8832858                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  91672034000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  91672034000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  91672034000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  91672034000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  91672034000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  91672034000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    231141484                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    231141484                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    231141484                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    231141484                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    231141484                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    231141484                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.038214                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.038214                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.038214                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.038214                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.038214                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.038214                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10378.524595                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10378.524595                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10378.524595                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10378.524595                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10378.524595                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10378.524595                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks      8832346                       # number of writebacks
system.cpu1.icache.writebacks::total          8832346                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      8832858                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      8832858                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      8832858                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      8832858                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      8832858                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      8832858                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           95                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           95                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           95                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           95                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  87255605000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  87255605000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  87255605000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  87255605000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  87255605000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  87255605000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9824500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9824500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9824500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      9824500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.038214                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.038214                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.038214                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.038214                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.038214                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.038214                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9878.524595                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9878.524595                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9878.524595                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  9878.524595                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9878.524595                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  9878.524595                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 103415.789474                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 103415.789474                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 103415.789474                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 103415.789474                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued      6928823                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      6928917                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           84                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       861587                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements         2157597                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13047.513497                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          12560684                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2173028                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            5.780268                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12721.719403                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    48.343114                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    32.192156                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   245.258823                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.776472                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002951                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.001965                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.014969                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.796357                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          270                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           73                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15088                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          102                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          107                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           61                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           42                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          273                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          832                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         6150                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6722                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1111                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.016479                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004456                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.920898                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       472979438                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      472979438                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       496781                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       150336                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        647117                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3051311                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3051311                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks     10695223                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total     10695223                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data            2                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total            2                       # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       813214                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       813214                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8132856                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      8132856                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2632220                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2632220                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       143613                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       143613                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       496781                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       150336                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      8132856                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3445434                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total       12225407                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       496781                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       150336                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      8132856                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3445434                       # number of overall hits
system.cpu1.l2cache.overall_hits::total      12225407                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        19778                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9507                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        29285                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       216104                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       216104                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       189953                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       189953                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       231177                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       231177                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       700002                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       700002                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       932644                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       932644                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       250983                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       250983                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        19778                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9507                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       700002                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1163821                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1893108                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        19778                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9507                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       700002                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1163821                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1893108                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    605384500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    346513000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    951897500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    912243000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    912243000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    268121000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    268121000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1526000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1526000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10578569498                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  10578569498                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  24914386500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  24914386500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  33296141988                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  33296141988                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    300579500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total    300579500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    605384500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    346513000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  24914386500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  43874711486                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  69740995486                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    605384500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    346513000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  24914386500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  43874711486                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  69740995486                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       516559                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       159843                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       676402                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3051311                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3051311                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks     10695223                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total     10695223                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       216106                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       216106                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       189953                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       189953                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1044391                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1044391                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      8832858                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      8832858                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3564864                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3564864                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       394596                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       394596                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       516559                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       159843                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      8832858                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4609255                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     14118515                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       516559                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       159843                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      8832858                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4609255                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     14118515                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.038288                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.059477                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.043295                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.999991                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999991                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.221351                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.221351                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.079250                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.079250                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.261621                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.261621                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.636051                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.636051                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.038288                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.059477                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.079250                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.252497                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.134087                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.038288                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.059477                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.079250                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.252497                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.134087                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30608.984731                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36448.196066                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32504.609869                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4221.314737                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4221.314737                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1411.512321                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1411.512321                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 508666.666667                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 508666.666667                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45759.610593                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45759.610593                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35591.879023                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35591.879023                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35700.805439                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35700.805439                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1197.609001                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1197.609001                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30608.984731                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36448.196066                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35591.879023                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37698.848436                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 36839.417237                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30608.984731                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36448.196066                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35591.879023                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37698.848436                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 36839.417237                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches           43184                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks      1062517                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1062517                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker           15                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           83                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total           98                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         6377                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         6377                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            2                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          790                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          790                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            1                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            1                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker           15                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           83                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            2                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7167                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         7267                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker           15                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           83                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            2                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         7167                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         7267                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        19763                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9424                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        29187                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       714287                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       714287                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       216104                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       216104                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       189953                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       189953                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       224800                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       224800                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       700000                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       700000                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       931854                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       931854                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       250982                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       250982                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        19763                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9424                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       700000                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1156654                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1885841                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        19763                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9424                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       700000                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1156654                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       714287                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2600128                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           95                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         7183                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         7278                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         7509                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         7509                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           95                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        14692                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        14787                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    486444500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    288576500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    775021000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  30894742332                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  30894742332                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4083186496                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4083186496                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2906568497                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2906568497                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1292000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1292000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8335690998                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8335690998                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  20714350500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  20714350500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  27592853988                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  27592853988                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6684154500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6684154500                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    486444500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    288576500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  20714350500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  35928544986                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  57417916486                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    486444500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    288576500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  20714350500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  35928544986                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  30894742332                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  88312658818                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9064500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    860524000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    869588500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9064500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    860524000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    869588500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.038259                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.058958                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.043150                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.999991                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.999991                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.215245                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.215245                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.079250                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.079250                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.261400                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.261400                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.636048                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.636048                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.038259                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.058958                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.079250                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.250942                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.133572                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.038259                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.058958                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.079250                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.250942                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.184164                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26553.636893                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43252.561410                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43252.561410                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18894.543812                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18894.543812                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15301.514043                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15301.514043                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 430666.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 430666.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37080.475970                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37080.475970                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29591.929286                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29591.929286                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29610.705098                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29610.705098                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26632.007475                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26632.007475                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29591.929286                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31062.482805                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30446.849170                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29591.929286                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31062.482805                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43252.561410                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33964.735128                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95415.789474                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119800.083531                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119481.794449                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95415.789474                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 58570.922951                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 58807.635085                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests     28307892                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     14471357                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1579                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       577788                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       577774                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops           14                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq        765944                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     13251577                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         7509                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         7509                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4119049                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean     10696803                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      1405207                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       907922                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            3                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       426575                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       338167                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       466317                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           47                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           83                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1072889                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1050772                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      8832858                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4591457                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       449471                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       394596                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     26498252                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15919614                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       339109                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1095958                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         43852933                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side   1130579136                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    615678398                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1278736                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4132472                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1751668742                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5086460                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic             75030592                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples     19865784                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.045122                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.207576                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          18969410     95.49%     95.49% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            896360      4.51%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                14      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      19865784                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   28134048478                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    171886209                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy  13252138560                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7328947477                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    179350830                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    579510776                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40272                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40272                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136595                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136595                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47628                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122510                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231144                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231144                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353734                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47648                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155640                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338592                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338592                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496318                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             42593000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               316000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               16000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25879501                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            34434000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           569469195                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92646000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147840000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115567                       # number of replacements
system.iocache.tags.tagsinuse               11.304352                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115583                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9167343261000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.387949                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.916404                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.461747                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.244775                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706522                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040505                       # Number of tag accesses
system.iocache.tags.data_accesses             1040505                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8844                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8881                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115572                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115612                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115572                       # number of overall misses
system.iocache.overall_misses::total           115612                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5196500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1979797452                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1984993952                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13211000243                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13211000243                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5565500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  15190797695                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  15196363195                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5565500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  15190797695                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  15196363195                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8844                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8881                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115572                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115612                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115572                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115612                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 223857.694708                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 223510.184889                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123781.952655                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 123781.952655                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 131440.121266                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 131442.784443                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 131440.121266                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 131442.784443                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         49739                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3574                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    13.916900                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106693                       # number of writebacks
system.iocache.writebacks::total               106693                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8844                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8881                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115572                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115612                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115572                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115612                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3346500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1537597452                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1540943952                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7865666947                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7865666947                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3565500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9403264399                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9406829899                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3565500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9403264399                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9406829899                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90445.945946                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 173857.694708                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 173510.184889                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73698.251134                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73698.251134                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 81362.824897                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 81365.514817                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 81362.824897                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 81365.514817                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1396284                       # number of replacements
system.l2c.tags.tagsinuse                65138.751942                       # Cycle average of tags in use
system.l2c.tags.total_refs                    7016729                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1457215                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     4.815164                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               8133240500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   10857.852094                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   193.720367                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   194.423316                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4494.530949                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    16342.707209                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  9582.831884                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   263.988799                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   269.731759                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4576.542600                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     8162.860696                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10199.562268                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.165678                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002956                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.002967                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.068581                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.249370                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.146222                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004028                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.004116                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.069832                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.124555                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.155633                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993938                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022         9763                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          241                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        50927                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2           80                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          414                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9269                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          241                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1371                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4645                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        44789                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.148972                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003677                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.777084                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 77350226                       # Number of tag accesses
system.l2c.tags.data_accesses                77350226                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks      2692321                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2692321                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data          204225                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          155483                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              359708                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         52320                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         51074                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total            103394                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            55531                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            51791                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               107322                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        13410                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5332                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       636242                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       595342                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       315678                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        10946                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4404                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       639193                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       560416                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       301207                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          3082170                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       138800                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       132737                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           271537                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker         13410                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          5332                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              636242                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              650873                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       315678                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         10946                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4404                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              639193                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              612207                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       301207                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3189492                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        13410                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         5332                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             636242                       # number of overall hits
system.l2c.overall_hits::cpu0.data             650873                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       315678                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        10946                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4404                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             639193                       # number of overall hits
system.l2c.overall_hits::cpu1.data             612207                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       301207                       # number of overall hits
system.l2c.overall_hits::total                3189492                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         22618                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         28127                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             50745                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          499                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          689                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1188                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          80171                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          45173                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             125344                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1994                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1777                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        61929                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       136966                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       215441                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1649                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1460                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        60807                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       104797                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       187062                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         773882                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       449504                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       106576                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         556080                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1994                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1777                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             61929                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            217137                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       215441                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1649                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1460                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             60807                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            149970                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       187062                       # number of demand (read+write) misses
system.l2c.demand_misses::total                899226                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1994                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1777                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            61929                       # number of overall misses
system.l2c.overall_misses::cpu0.data           217137                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       215441                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1649                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1460                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            60807                       # number of overall misses
system.l2c.overall_misses::cpu1.data           149970                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       187062                       # number of overall misses
system.l2c.overall_misses::total               899226                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    166509500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    180855500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    347365000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      6105500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      8200500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total     14306000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   8647457500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4904092500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  13551550000                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    211493000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    194819500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6896332000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  15165548000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  30671403248                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    166890000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    150626500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   6689940000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  12141260000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  25575724378                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  97864036626                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data     46615500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data     36764000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total     83379500                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    211493000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    194819500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   6896332000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  23813005500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  30671403248                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    166890000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    150626500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   6689940000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  17045352500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  25575724378                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    111415586626                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    211493000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    194819500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   6896332000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  23813005500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  30671403248                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    166890000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    150626500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   6689940000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  17045352500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  25575724378                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   111415586626                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2692321                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2692321                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       226843                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       183610                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          410453                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        52819                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        51763                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total        104582                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       135702                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        96964                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           232666                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        15404                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7109                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       698171                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       732308                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       531119                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        12595                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5864                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       700000                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       665213                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       488269                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3856052                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       588304                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       239313                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       827617                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        15404                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7109                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          698171                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          868010                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       531119                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        12595                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5864                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          700000                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          762177                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       488269                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4088718                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        15404                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7109                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         698171                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         868010                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       531119                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        12595                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5864                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         700000                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         762177                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       488269                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4088718                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.099708                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.153189                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.123632                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.009447                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.013311                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.011360                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.590787                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.465874                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.538729                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.129447                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.249965                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.088702                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.187033                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.405636                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.130925                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.248977                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.086867                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.157539                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.383113                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.200693                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.764068                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.445341                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.671905                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.129447                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.249965                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.088702                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.250155                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.405636                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.130925                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.248977                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.086867                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.196765                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.383113                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.219929                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.129447                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.249965                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.088702                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.250155                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.405636                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.130925                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.248977                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.086867                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.196765                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.383113                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.219929                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  7361.813600                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6429.960536                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6845.304956                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12235.470942                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11902.031930                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 12042.087542                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 107862.662309                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108562.470945                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 108114.867884                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 106064.694082                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 109633.933596                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 111358.684946                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 110724.909832                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 101206.791995                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103168.835616                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110019.241206                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115855.034018                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 126458.603025                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   103.704305                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   344.955712                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total   149.941555                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 106064.694082                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 109633.933596                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 111358.684946                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 109668.115061                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 101206.791995                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103168.835616                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 110019.241206                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 113658.415016                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 123901.651672                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 106064.694082                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 109633.933596                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 111358.684946                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 109668.115061                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 101206.791995                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103168.835616                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 110019.241206                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 113658.415016                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 123901.651672                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               622                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       12                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     51.833333                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1054868                       # number of writebacks
system.l2c.writebacks::total                  1054868                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          139                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           25                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          132                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           14                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          311                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            139                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             25                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            132                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             14                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                311                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           139                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            25                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           132                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            14                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               311                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        56418                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        56418                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        22618                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        28127                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        50745                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          499                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          689                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1188                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        80171                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        45173                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        125344                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1994                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1777                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        61790                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       136941                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       215440                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1649                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1460                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        60675                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       104783                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       187062                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       773571                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       449504                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       106576                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       556080                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1994                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1777                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        61790                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       217112                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       215440                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1649                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1460                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        60675                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       149956                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       187062                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           898915                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1994                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1777                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        61790                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       217112                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       215440                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1649                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1460                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        60675                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       149956                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       187062                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          898915                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        52284                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31212                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           95                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         7181                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        90772                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        30755                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         7509                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38264                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        52284                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        61967                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           95                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        14690                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       129036                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    461841000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    578903500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   1040744500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     11863000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     16565000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     28428000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7845723550                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4452337552                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  12298061102                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    191553000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    177048502                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   6267361033                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  13793559696                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  28516814074                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    150400000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    136026500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   6069566554                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  11092033207                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  23704989123                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  90099351689                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   9394175000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2170818500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  11564993500                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    191553000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    177048502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   6267361033                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  21639283246                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  28516814074                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    150400000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    136026500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   6069566554                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  15544370759                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  23704989123                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 102397412791                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    191553000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    177048502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   6267361033                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  21639283246                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  28516814074                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    150400000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    136026500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   6069566554                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  15544370759                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  23704989123                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 102397412791                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3645369500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5226952503                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7066500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    731143001                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   9610531504                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3645369500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5226952503                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7066500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    731143001                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   9610531504                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.099708                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.153189                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.123632                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.009447                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.013311                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.011360                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.590787                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.465874                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.538729                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.129447                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.249965                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.088503                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.186999                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.405634                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.130925                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.248977                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.086679                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.157518                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383113                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.200612                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.764068                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.445341                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.671905                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.129447                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.249965                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.088503                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.250126                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.405634                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.130925                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.248977                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.086679                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.196747                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383113                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.219853                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.129447                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.249965                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.088503                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.250126                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.405634                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.130925                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.248977                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.086679                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.196747                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383113                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.219853                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20419.179415                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20581.771963                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20509.301409                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23773.547094                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24042.089985                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23929.292929                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97862.363573                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98561.918668                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 98114.477773                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 101430.021573                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100726.295967                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100034.059398                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105857.183007                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116471.987302                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20898.979764                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20368.736864                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20797.355596                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 101430.021573                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99668.757351                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100034.059398                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103659.545193                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 113912.230624                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 101430.021573                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99668.757351                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100034.059398                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103659.545193                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 113912.230624                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167466.118897                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74384.210526                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 101816.320986                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105875.506808                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84350.581810                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74384.210526                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 49771.477263                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 74479.459252                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests       3616665                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      2148581                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         2925                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               90772                       # Transaction distribution
system.membus.trans_dist::ReadResp             873224                       # Transaction distribution
system.membus.trans_dist::WriteReq              38264                       # Transaction distribution
system.membus.trans_dist::WriteResp             38264                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1161561                       # Transaction distribution
system.membus.trans_dist::CleanEvict           250705                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           347946                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         273520                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              24                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
system.membus.trans_dist::ReadExReq            139972                       # Transaction distribution
system.membus.trans_dist::ReadExResp           124377                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        782452                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        660097                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122510                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           54                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25584                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4392225                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4540373                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238087                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       238087                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4778460                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155640                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1388                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51168                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    128305664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    128513860                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7270464                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7270464                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               135784324                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           584171                       # Total snoops (count)
system.membus.snoopTraffic                     172608                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2333030                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.013166                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.113984                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 2302314     98.68%     98.68% # Request fanout histogram
system.membus.snoop_fanout::1                   30716      1.32%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2333030                       # Request fanout histogram
system.membus.reqLayer0.occupancy           103320999                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               34812                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21353996                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8035790677                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         5121349382                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           45284261                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     12127091                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      6563266                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      2068389                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         180040                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       163507                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        16533                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              90774                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4717359                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38264                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38264                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      3747189                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2956256                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          703976                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        376914                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1080890                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           83                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           83                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           286236                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          286236                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4627139                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       855379                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       827617                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9817286                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8000729                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17818015                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    243574806                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    194096942                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              437671748                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2816292                       # Total snoops (count)
system.toL2Bus.snoopTraffic                 120259472                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples          8375094                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.374182                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.487973                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                5257818     62.78%     62.78% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                3100743     37.02%     99.80% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  16533      0.20%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            8375094                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         9230074402                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2547405                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4495965489                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3978820805                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
