
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000059                       # Number of seconds simulated
sim_ticks                                    58513000                       # Number of ticks simulated
final_tick                                   58513000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 297973                       # Simulator instruction rate (inst/s)
host_op_rate                                   537391                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3045372421                       # Simulator tick rate (ticks/s)
host_mem_usage                                 656016                       # Number of bytes of host memory used
host_seconds                                     0.02                       # Real time elapsed on the host
sim_insts                                        5712                       # Number of instructions simulated
sim_ops                                         10314                       # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.mem_ctrl.bytes_read::cpu.inst            14656                       # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data             8640                       # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total               23296                       # Number of bytes read from this memory
system.mem_ctrl.bytes_inst_read::cpu.inst        14656                       # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_inst_read::total          14656                       # Number of instructions bytes read from this memory
system.mem_ctrl.num_reads::cpu.inst               229                       # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::cpu.data               135                       # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::total                  364                       # Number of read requests responded to by this memory
system.mem_ctrl.bw_read::cpu.inst           250474254                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::cpu.data           147659494                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::total              398133748                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::cpu.inst      250474254                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::total         250474254                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.inst          250474254                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.data          147659494                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::total             398133748                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.readReqs                          364                       # Number of read requests accepted
system.mem_ctrl.writeReqs                           0                       # Number of write requests accepted
system.mem_ctrl.readBursts                        364                       # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrl.writeBursts                         0                       # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrl.bytesReadDRAM                   23296                       # Total number of bytes read from DRAM
system.mem_ctrl.bytesReadWrQ                        0                       # Total number of bytes read from write queue
system.mem_ctrl.bytesWritten                        0                       # Total number of bytes written to DRAM
system.mem_ctrl.bytesReadSys                    23296                       # Total read bytes from the system interface side
system.mem_ctrl.bytesWrittenSys                     0                       # Total written bytes from the system interface side
system.mem_ctrl.servicedByWrQ                       0                       # Number of DRAM read bursts serviced by the write queue
system.mem_ctrl.mergedWrBursts                      0                       # Number of DRAM write bursts merged with an existing one
system.mem_ctrl.neitherReadNorWriteReqs             0                       # Number of requests that are neither read nor write
system.mem_ctrl.perBankRdBursts::0                 30                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::1                  1                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::2                  5                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::3                  8                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::4                 43                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::5                 40                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::6                 13                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::7                 24                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::8                 17                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::9                 71                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::10                62                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::11                14                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::12                 2                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::13                14                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::14                 4                       # Per bank write bursts
system.mem_ctrl.perBankRdBursts::15                16                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::0                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::1                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::2                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::3                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::4                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::5                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::6                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::7                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::8                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::9                  0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::10                 0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::11                 0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::12                 0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::13                 0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::14                 0                       # Per bank write bursts
system.mem_ctrl.perBankWrBursts::15                 0                       # Per bank write bursts
system.mem_ctrl.numRdRetry                          0                       # Number of times read queue was full causing retry
system.mem_ctrl.numWrRetry                          0                       # Number of times write queue was full causing retry
system.mem_ctrl.totGap                       58376000                       # Total gap between requests
system.mem_ctrl.readPktSize::0                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::1                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::2                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::3                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::4                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::5                      0                       # Read request sizes (log2)
system.mem_ctrl.readPktSize::6                    364                       # Read request sizes (log2)
system.mem_ctrl.writePktSize::0                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::1                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::2                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::3                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::4                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::5                     0                       # Write request sizes (log2)
system.mem_ctrl.writePktSize::6                     0                       # Write request sizes (log2)
system.mem_ctrl.rdQLenPdf::0                      364                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::1                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::2                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::3                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::4                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::5                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::6                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::7                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::8                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::9                        0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::10                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::11                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::12                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::13                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::14                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::15                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::16                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::17                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::18                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::19                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::20                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::21                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::22                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::23                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::24                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::25                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::26                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::27                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::28                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::29                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::30                       0                       # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::31                       0                       # What read queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::0                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::1                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::2                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::3                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::4                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::5                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::6                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::7                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::8                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::9                        0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::10                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::11                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::12                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::13                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::14                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::15                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::16                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::17                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::18                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::19                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::20                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::21                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::22                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::23                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::24                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::25                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::26                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::27                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::28                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::29                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::30                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::31                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::32                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::33                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::34                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::35                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::36                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::37                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::38                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::39                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::40                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::41                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::42                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::43                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::44                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::45                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::46                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::47                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::48                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::49                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::50                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::51                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::52                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::53                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::54                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::55                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::56                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::57                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::58                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::59                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::60                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::61                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::62                       0                       # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::63                       0                       # What write queue length does an incoming req see
system.mem_ctrl.bytesPerActivate::samples          108                       # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::mean     199.703704                       # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::gmean    135.091179                       # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::stdev    199.282229                       # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::0-127            52     48.15%     48.15% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::128-255           21     19.44%     67.59% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::256-383           15     13.89%     81.48% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::384-511            8      7.41%     88.89% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::512-639            7      6.48%     95.37% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::640-767            2      1.85%     97.22% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::768-895            1      0.93%     98.15% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::896-1023            1      0.93%     99.07% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151            1      0.93%    100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total           108                       # Bytes accessed per row activation
system.mem_ctrl.totQLat                       5858750                       # Total ticks spent queuing
system.mem_ctrl.totMemAccLat                 12683750                       # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat                     1820000                       # Total ticks spent in databus transfers
system.mem_ctrl.avgQLat                      16095.47                       # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat                     5000.00                       # Average bus latency per DRAM burst
system.mem_ctrl.avgMemAccLat                 34845.47                       # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW                        398.13                       # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgWrBW                          0.00                       # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys                     398.13                       # Average system read bandwidth in MiByte/s
system.mem_ctrl.avgWrBWSys                       0.00                       # Average system write bandwidth in MiByte/s
system.mem_ctrl.peakBW                       12800.00                       # Theoretical peak bandwidth in MiByte/s
system.mem_ctrl.busUtil                          3.11                       # Data bus utilization in percentage
system.mem_ctrl.busUtilRead                      3.11                       # Data bus utilization in percentage for reads
system.mem_ctrl.busUtilWrite                     0.00                       # Data bus utilization in percentage for writes
system.mem_ctrl.avgRdQLen                        1.00                       # Average read queue length when enqueuing
system.mem_ctrl.avgWrQLen                        0.00                       # Average write queue length when enqueuing
system.mem_ctrl.readRowHits                       248                       # Number of row buffer hits during reads
system.mem_ctrl.writeRowHits                        0                       # Number of row buffer hits during writes
system.mem_ctrl.readRowHitRate                  68.13                       # Row buffer hit rate for reads
system.mem_ctrl.writeRowHitRate                   nan                       # Row buffer hit rate for writes
system.mem_ctrl.avgGap                      160373.63                       # Average gap between requests
system.mem_ctrl.pageHitRate                     68.13                       # Row buffer hit rate, read and write combined
system.mem_ctrl_0.actEnergy                    292740                       # Energy for activate commands per rank (pJ)
system.mem_ctrl_0.preEnergy                    136620                       # Energy for precharge commands per rank (pJ)
system.mem_ctrl_0.readEnergy                  1170960                       # Energy for read commands per rank (pJ)
system.mem_ctrl_0.writeEnergy                       0                       # Energy for write commands per rank (pJ)
system.mem_ctrl_0.refreshEnergy          4302480.000000                       # Energy for refresh commands per rank (pJ)
system.mem_ctrl_0.actBackEnergy               2975970                       # Energy for active background per rank (pJ)
system.mem_ctrl_0.preBackEnergy                 96960                       # Energy for precharge background per rank (pJ)
system.mem_ctrl_0.actPowerDownEnergy         20164320                       # Energy for active power-down per rank (pJ)
system.mem_ctrl_0.prePowerDownEnergy          2885760                       # Energy for precharge power-down per rank (pJ)
system.mem_ctrl_0.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
system.mem_ctrl_0.totalEnergy                32025810                       # Total energy per rank (pJ)
system.mem_ctrl_0.averagePower             547.321100                       # Core power per rank (mW)
system.mem_ctrl_0.totalIdleTime              51467750                       # Total Idle time Per DRAM Rank
system.mem_ctrl_0.memoryStateTime::IDLE         59000                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::REF        1820000                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::SREF             0                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::PRE_PDN      7513000                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT        4902000                       # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT_PDN     44219000                       # Time in different power states
system.mem_ctrl_1.actEnergy                    535500                       # Energy for activate commands per rank (pJ)
system.mem_ctrl_1.preEnergy                    273240                       # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.readEnergy                  1428000                       # Energy for read commands per rank (pJ)
system.mem_ctrl_1.writeEnergy                       0                       # Energy for write commands per rank (pJ)
system.mem_ctrl_1.refreshEnergy          4302480.000000                       # Energy for refresh commands per rank (pJ)
system.mem_ctrl_1.actBackEnergy               3735210                       # Energy for active background per rank (pJ)
system.mem_ctrl_1.preBackEnergy                150720                       # Energy for precharge background per rank (pJ)
system.mem_ctrl_1.actPowerDownEnergy         22328040                       # Energy for active power-down per rank (pJ)
system.mem_ctrl_1.prePowerDownEnergy           370560                       # Energy for precharge power-down per rank (pJ)
system.mem_ctrl_1.selfRefreshEnergy                 0                       # Energy for self refresh per rank (pJ)
system.mem_ctrl_1.totalEnergy                33123750                       # Total energy per rank (pJ)
system.mem_ctrl_1.averagePower             566.084895                       # Core power per rank (mW)
system.mem_ctrl_1.totalIdleTime              49870500                       # Total Idle time Per DRAM Rank
system.mem_ctrl_1.memoryStateTime::IDLE        184000                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::REF        1820000                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::SREF             0                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::PRE_PDN       965000                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT        6563000                       # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN     48981000                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock                16000                       # Clock period in ticks
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls                   11                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON        58513000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                            58513                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                        5712                       # Number of instructions committed
system.cpu.committedOps                         10314                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses                 10205                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                         221                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts          986                       # number of instructions that are conditional controls
system.cpu.num_int_insts                        10205                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads               19296                       # number of times the integer registers were read
system.cpu.num_int_register_writes               7977                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads                 7020                       # number of times the CC registers were read
system.cpu.num_cc_register_writes                3825                       # number of times the CC registers were written
system.cpu.num_mem_refs                          2025                       # number of memory refs
system.cpu.num_load_insts                        1084                       # Number of load instructions
system.cpu.num_store_insts                        941                       # Number of store instructions
system.cpu.num_idle_cycles                   0.001000                       # Number of idle cycles
system.cpu.num_busy_cycles               58512.999000                       # Number of busy cycles
system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
system.cpu.Branches                              1306                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     1      0.01%      0.01% # Class of executed instruction
system.cpu.op_class::IntAlu                      8275     80.23%     80.24% # Class of executed instruction
system.cpu.op_class::IntMult                        6      0.06%     80.30% # Class of executed instruction
system.cpu.op_class::IntDiv                         7      0.07%     80.37% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::FloatMultAcc                   0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::FloatMisc                      0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     80.37% # Class of executed instruction
system.cpu.op_class::MemRead                     1084     10.51%     90.88% # Class of executed instruction
system.cpu.op_class::MemWrite                     941      9.12%    100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite                  0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                      10314                       # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse            81.299644                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                1890                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               135                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs                    14                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    81.299644                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.079394                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.079394                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           12                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          123                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.131836                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              4185                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             4185                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data         1028                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1028                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          862                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            862                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          1890                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             1890                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         1890                       # number of overall hits
system.cpu.dcache.overall_hits::total            1890                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           56                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            56                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data           79                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           79                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          135                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            135                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          135                       # number of overall misses
system.cpu.dcache.overall_misses::total           135                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      6406000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      6406000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      8602000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      8602000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     15008000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     15008000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     15008000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     15008000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1084                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1084                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          941                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          941                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2025                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2025                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2025                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2025                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.051661                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.051661                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.083953                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.083953                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.066667                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.066667                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.066667                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.066667                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 111170.370370                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 111170.370370                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           56                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           56                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           79                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           79                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          135                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          135                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          135                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          135                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6294000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      6294000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      8444000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      8444000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     14738000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     14738000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     14738000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     14738000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.051661                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.051661                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083953                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083953                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066667                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.066667                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066667                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.066667                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                58                       # number of replacements
system.cpu.icache.tags.tagsinuse            90.704136                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                7048                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               235                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             29.991489                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst    90.704136                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.354313                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.354313                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          177                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          134                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.691406                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses             14801                       # Number of tag accesses
system.cpu.icache.tags.data_accesses            14801                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst         7048                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            7048                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          7048                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             7048                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         7048                       # number of overall hits
system.cpu.icache.overall_hits::total            7048                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          235                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           235                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          235                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            235                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          235                       # number of overall misses
system.cpu.icache.overall_misses::total           235                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     25629000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     25629000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     25629000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     25629000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     25629000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     25629000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         7283                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         7283                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         7283                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         7283                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         7283                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         7283                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.032267                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.032267                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.032267                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.032267                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.032267                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.032267                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 109059.574468                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 109059.574468                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          235                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          235                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          235                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          235                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          235                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          235                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25159000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     25159000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25159000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     25159000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25159000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     25159000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.032267                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.032267                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.032267                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.032267                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.032267                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.032267                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468                       # average overall mshr miss latency
system.l2bus.snoop_filter.tot_requests            428                       # Total number of requests made to the snoop filter.
system.l2bus.snoop_filter.hit_single_requests           59                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.l2bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.l2bus.snoop_filter.tot_snoops                0                       # Total number of snoops made to the snoop filter.
system.l2bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l2bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.l2bus.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.l2bus.trans_dist::ReadResp                 291                       # Transaction distribution
system.l2bus.trans_dist::CleanEvict                58                       # Transaction distribution
system.l2bus.trans_dist::ReadExReq                 79                       # Transaction distribution
system.l2bus.trans_dist::ReadExResp                79                       # Transaction distribution
system.l2bus.trans_dist::ReadSharedReq            291                       # Transaction distribution
system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side          528                       # Packet count per connected master and slave (bytes)
system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side          270                       # Packet count per connected master and slave (bytes)
system.l2bus.pkt_count::total                     798                       # Packet count per connected master and slave (bytes)
system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side        15040                       # Cumulative packet size per connected master and slave (bytes)
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side         8640                       # Cumulative packet size per connected master and slave (bytes)
system.l2bus.pkt_size::total                    23680                       # Cumulative packet size per connected master and slave (bytes)
system.l2bus.snoops                                 0                       # Total snoops (count)
system.l2bus.snoopTraffic                           0                       # Total snoop traffic (bytes)
system.l2bus.snoop_fanout::samples                370                       # Request fanout histogram
system.l2bus.snoop_fanout::mean              0.002703                       # Request fanout histogram
system.l2bus.snoop_fanout::stdev             0.051988                       # Request fanout histogram
system.l2bus.snoop_fanout::underflows               0      0.00%      0.00% # Request fanout histogram
system.l2bus.snoop_fanout::0                      369     99.73%     99.73% # Request fanout histogram
system.l2bus.snoop_fanout::1                        1      0.27%    100.00% # Request fanout histogram
system.l2bus.snoop_fanout::2                        0      0.00%    100.00% # Request fanout histogram
system.l2bus.snoop_fanout::overflows                0      0.00%    100.00% # Request fanout histogram
system.l2bus.snoop_fanout::min_value                0                       # Request fanout histogram
system.l2bus.snoop_fanout::max_value                1                       # Request fanout histogram
system.l2bus.snoop_fanout::total                  370                       # Request fanout histogram
system.l2bus.reqLayer0.occupancy               428000                       # Layer occupancy (ticks)
system.l2bus.reqLayer0.utilization                0.7                       # Layer utilization (%)
system.l2bus.respLayer0.occupancy              705000                       # Layer occupancy (ticks)
system.l2bus.respLayer0.utilization               1.2                       # Layer utilization (%)
system.l2bus.respLayer1.occupancy              405000                       # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization               0.7                       # Layer utilization (%)
system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.l2cache.tags.replacements                    0                       # number of replacements
system.l2cache.tags.tagsinuse              187.541609                       # Cycle average of tags in use
system.l2cache.tags.total_refs                     64                       # Total number of references to valid blocks.
system.l2cache.tags.sampled_refs                  364                       # Sample count of references to valid blocks.
system.l2cache.tags.avg_refs                 0.175824                       # Average number of references to valid blocks.
system.l2cache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.l2cache.tags.occ_blocks::cpu.inst   106.193515                       # Average occupied blocks per requestor
system.l2cache.tags.occ_blocks::cpu.data    81.348095                       # Average occupied blocks per requestor
system.l2cache.tags.occ_percent::cpu.inst     0.025926                       # Average percentage of cache occupancy
system.l2cache.tags.occ_percent::cpu.data     0.019860                       # Average percentage of cache occupancy
system.l2cache.tags.occ_percent::total       0.045787                       # Average percentage of cache occupancy
system.l2cache.tags.occ_task_id_blocks::1024          364                       # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
system.l2cache.tags.occ_task_id_percent::1024     0.088867                       # Percentage of cache occupancy per task id
system.l2cache.tags.tag_accesses                 3788                       # Number of tag accesses
system.l2cache.tags.data_accesses                3788                       # Number of data accesses
system.l2cache.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.l2cache.ReadSharedReq_hits::cpu.inst            6                       # number of ReadSharedReq hits
system.l2cache.ReadSharedReq_hits::total            6                       # number of ReadSharedReq hits
system.l2cache.demand_hits::cpu.inst                6                       # number of demand (read+write) hits
system.l2cache.demand_hits::total                   6                       # number of demand (read+write) hits
system.l2cache.overall_hits::cpu.inst               6                       # number of overall hits
system.l2cache.overall_hits::total                  6                       # number of overall hits
system.l2cache.ReadExReq_misses::cpu.data           79                       # number of ReadExReq misses
system.l2cache.ReadExReq_misses::total             79                       # number of ReadExReq misses
system.l2cache.ReadSharedReq_misses::cpu.inst          229                       # number of ReadSharedReq misses
system.l2cache.ReadSharedReq_misses::cpu.data           56                       # number of ReadSharedReq misses
system.l2cache.ReadSharedReq_misses::total          285                       # number of ReadSharedReq misses
system.l2cache.demand_misses::cpu.inst            229                       # number of demand (read+write) misses
system.l2cache.demand_misses::cpu.data            135                       # number of demand (read+write) misses
system.l2cache.demand_misses::total               364                       # number of demand (read+write) misses
system.l2cache.overall_misses::cpu.inst           229                       # number of overall misses
system.l2cache.overall_misses::cpu.data           135                       # number of overall misses
system.l2cache.overall_misses::total              364                       # number of overall misses
system.l2cache.ReadExReq_miss_latency::cpu.data      8207000                       # number of ReadExReq miss cycles
system.l2cache.ReadExReq_miss_latency::total      8207000                       # number of ReadExReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.inst     24326000                       # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.data      6126000                       # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::total     30452000                       # number of ReadSharedReq miss cycles
system.l2cache.demand_miss_latency::cpu.inst     24326000                       # number of demand (read+write) miss cycles
system.l2cache.demand_miss_latency::cpu.data     14333000                       # number of demand (read+write) miss cycles
system.l2cache.demand_miss_latency::total     38659000                       # number of demand (read+write) miss cycles
system.l2cache.overall_miss_latency::cpu.inst     24326000                       # number of overall miss cycles
system.l2cache.overall_miss_latency::cpu.data     14333000                       # number of overall miss cycles
system.l2cache.overall_miss_latency::total     38659000                       # number of overall miss cycles
system.l2cache.ReadExReq_accesses::cpu.data           79                       # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadExReq_accesses::total           79                       # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadSharedReq_accesses::cpu.inst          235                       # number of ReadSharedReq accesses(hits+misses)
system.l2cache.ReadSharedReq_accesses::cpu.data           56                       # number of ReadSharedReq accesses(hits+misses)
system.l2cache.ReadSharedReq_accesses::total          291                       # number of ReadSharedReq accesses(hits+misses)
system.l2cache.demand_accesses::cpu.inst          235                       # number of demand (read+write) accesses
system.l2cache.demand_accesses::cpu.data          135                       # number of demand (read+write) accesses
system.l2cache.demand_accesses::total             370                       # number of demand (read+write) accesses
system.l2cache.overall_accesses::cpu.inst          235                       # number of overall (read+write) accesses
system.l2cache.overall_accesses::cpu.data          135                       # number of overall (read+write) accesses
system.l2cache.overall_accesses::total            370                       # number of overall (read+write) accesses
system.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.l2cache.ReadSharedReq_miss_rate::cpu.inst     0.974468                       # miss rate for ReadSharedReq accesses
system.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
system.l2cache.ReadSharedReq_miss_rate::total     0.979381                       # miss rate for ReadSharedReq accesses
system.l2cache.demand_miss_rate::cpu.inst     0.974468                       # miss rate for demand accesses
system.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.l2cache.demand_miss_rate::total       0.983784                       # miss rate for demand accesses
system.l2cache.overall_miss_rate::cpu.inst     0.974468                       # miss rate for overall accesses
system.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.l2cache.overall_miss_rate::total      0.983784                       # miss rate for overall accesses
system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103886.075949                       # average ReadExReq miss latency
system.l2cache.ReadExReq_avg_miss_latency::total 103886.075949                       # average ReadExReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 106227.074236                       # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109392.857143                       # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::total 106849.122807                       # average ReadSharedReq miss latency
system.l2cache.demand_avg_miss_latency::cpu.inst 106227.074236                       # average overall miss latency
system.l2cache.demand_avg_miss_latency::cpu.data 106170.370370                       # average overall miss latency
system.l2cache.demand_avg_miss_latency::total 106206.043956                       # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236                       # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370                       # average overall miss latency
system.l2cache.overall_avg_miss_latency::total 106206.043956                       # average overall miss latency
system.l2cache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.l2cache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.l2cache.blocked::no_targets                  0                       # number of cycles access was blocked
system.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2cache.ReadExReq_mshr_misses::cpu.data           79                       # number of ReadExReq MSHR misses
system.l2cache.ReadExReq_mshr_misses::total           79                       # number of ReadExReq MSHR misses
system.l2cache.ReadSharedReq_mshr_misses::cpu.inst          229                       # number of ReadSharedReq MSHR misses
system.l2cache.ReadSharedReq_mshr_misses::cpu.data           56                       # number of ReadSharedReq MSHR misses
system.l2cache.ReadSharedReq_mshr_misses::total          285                       # number of ReadSharedReq MSHR misses
system.l2cache.demand_mshr_misses::cpu.inst          229                       # number of demand (read+write) MSHR misses
system.l2cache.demand_mshr_misses::cpu.data          135                       # number of demand (read+write) MSHR misses
system.l2cache.demand_mshr_misses::total          364                       # number of demand (read+write) MSHR misses
system.l2cache.overall_mshr_misses::cpu.inst          229                       # number of overall MSHR misses
system.l2cache.overall_mshr_misses::cpu.data          135                       # number of overall MSHR misses
system.l2cache.overall_mshr_misses::total          364                       # number of overall MSHR misses
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data      6627000                       # number of ReadExReq MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_latency::total      6627000                       # number of ReadExReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst     19746000                       # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      5006000                       # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::total     24752000                       # number of ReadSharedReq MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.inst     19746000                       # number of demand (read+write) MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.data     11633000                       # number of demand (read+write) MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::total     31379000                       # number of demand (read+write) MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.inst     19746000                       # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.data     11633000                       # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::total     31379000                       # number of overall MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst     0.974468                       # mshr miss rate for ReadSharedReq accesses
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
system.l2cache.ReadSharedReq_mshr_miss_rate::total     0.979381                       # mshr miss rate for ReadSharedReq accesses
system.l2cache.demand_mshr_miss_rate::cpu.inst     0.974468                       # mshr miss rate for demand accesses
system.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.l2cache.demand_mshr_miss_rate::total     0.983784                       # mshr miss rate for demand accesses
system.l2cache.overall_mshr_miss_rate::cpu.inst     0.974468                       # mshr miss rate for overall accesses
system.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.l2cache.overall_mshr_miss_rate::total     0.983784                       # mshr miss rate for overall accesses
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949                       # average ReadExReq mshr miss latency
system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949                       # average ReadExReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236                       # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143                       # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807                       # average ReadSharedReq mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236                       # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370                       # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956                       # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236                       # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370                       # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests           364                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED     58513000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                285                       # Transaction distribution
system.membus.trans_dist::ReadExReq                79                       # Transaction distribution
system.membus.trans_dist::ReadExResp               79                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           285                       # Transaction distribution
system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port          728                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2cache.mem_side::total          728                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    728                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port        23296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2cache.mem_side::total        23296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   23296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               364                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     364    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 364                       # Request fanout histogram
system.membus.reqLayer2.occupancy              364000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.6                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1951250                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              3.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
