
---------- Begin Simulation Statistics ----------
sim_seconds                                 51.688775                       # Number of seconds simulated
sim_ticks                                51688774990000                       # Number of ticks simulated
final_tick                               51688774990000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 278192                       # Simulator instruction rate (inst/s)
host_op_rate                                   326870                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            15185295340                       # Simulator tick rate (ticks/s)
host_mem_usage                                 686764                       # Number of bytes of host memory used
host_seconds                                  3403.87                       # Real time elapsed on the host
sim_insts                                   946928269                       # Number of instructions simulated
sim_ops                                    1112623169                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker       401472                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       331520                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst          10196544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          65400968                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        425152                       # Number of bytes read from this memory
system.physmem.bytes_read::total             76755656                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst     10196544                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        10196544                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     93615936                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          93636516                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         6273                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         5180                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             159321                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1021903                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6643                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1199320                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1462749                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1465322                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           7767                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           6414                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               197268                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1265284                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8225                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1484958                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          197268                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             197268                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1811146                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1811544                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1811146                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          7767                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          6414                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              197268                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1265682                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8225                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3296502                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1199320                       # Number of read requests accepted
system.physmem.writeReqs                      1465322                       # Number of write requests accepted
system.physmem.readBursts                     1199320                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1465322                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 76712512                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     43968                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  93634496                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  76755656                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               93636516                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      687                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2262                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               70144                       # Per bank write bursts
system.physmem.perBankRdBursts::1               74650                       # Per bank write bursts
system.physmem.perBankRdBursts::2               68418                       # Per bank write bursts
system.physmem.perBankRdBursts::3               68145                       # Per bank write bursts
system.physmem.perBankRdBursts::4               72367                       # Per bank write bursts
system.physmem.perBankRdBursts::5               76479                       # Per bank write bursts
system.physmem.perBankRdBursts::6               68140                       # Per bank write bursts
system.physmem.perBankRdBursts::7               71247                       # Per bank write bursts
system.physmem.perBankRdBursts::8               66581                       # Per bank write bursts
system.physmem.perBankRdBursts::9              125666                       # Per bank write bursts
system.physmem.perBankRdBursts::10              74635                       # Per bank write bursts
system.physmem.perBankRdBursts::11              76739                       # Per bank write bursts
system.physmem.perBankRdBursts::12              72169                       # Per bank write bursts
system.physmem.perBankRdBursts::13              75530                       # Per bank write bursts
system.physmem.perBankRdBursts::14              66172                       # Per bank write bursts
system.physmem.perBankRdBursts::15              71551                       # Per bank write bursts
system.physmem.perBankWrBursts::0               89120                       # Per bank write bursts
system.physmem.perBankWrBursts::1               91694                       # Per bank write bursts
system.physmem.perBankWrBursts::2               88427                       # Per bank write bursts
system.physmem.perBankWrBursts::3               87889                       # Per bank write bursts
system.physmem.perBankWrBursts::4               92386                       # Per bank write bursts
system.physmem.perBankWrBursts::5               94711                       # Per bank write bursts
system.physmem.perBankWrBursts::6               88472                       # Per bank write bursts
system.physmem.perBankWrBursts::7               91239                       # Per bank write bursts
system.physmem.perBankWrBursts::8               88274                       # Per bank write bursts
system.physmem.perBankWrBursts::9               94990                       # Per bank write bursts
system.physmem.perBankWrBursts::10              92874                       # Per bank write bursts
system.physmem.perBankWrBursts::11              94799                       # Per bank write bursts
system.physmem.perBankWrBursts::12              93039                       # Per bank write bursts
system.physmem.perBankWrBursts::13              95949                       # Per bank write bursts
system.physmem.perBankWrBursts::14              87664                       # Per bank write bursts
system.physmem.perBankWrBursts::15              91512                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         468                       # Number of times write queue was full causing retry
system.physmem.totGap                    51688773130000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1199305                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1462749                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1127245                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     64919                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       779                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       328                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       491                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       476                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       609                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       509                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1056                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       628                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      296                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      301                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      207                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      165                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      112                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      104                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       93                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       80                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    29655                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    37473                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    78822                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    84952                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    87044                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    83743                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    88388                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    87662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    88784                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    85626                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    88571                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    89853                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    87229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    84323                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    82904                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    81964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    79861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    79771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2782                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2080                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1918                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1552                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1254                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      996                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      968                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      849                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      723                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      703                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      804                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      853                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      763                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      765                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      689                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      985                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                     1056                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      910                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      634                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                     1027                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                     1982                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                     1362                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      537                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                     1066                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       662940                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      256.956322                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     154.084684                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     293.850288                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         284383     42.90%     42.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       170705     25.75%     68.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        61081      9.21%     77.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        33561      5.06%     82.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        23575      3.56%     86.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        15515      2.34%     88.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        11286      1.70%     90.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9362      1.41%     91.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        53472      8.07%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         662940                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         77129                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        15.540445                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      141.912078                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          77126    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           77129                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         77129                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.968728                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.139558                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        8.416384                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           64621     83.78%     83.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            3761      4.88%     88.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            3195      4.14%     92.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31            2420      3.14%     95.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35            1145      1.48%     97.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             346      0.45%     97.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             199      0.26%     98.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47             173      0.22%     98.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             112      0.15%     98.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              62      0.08%     98.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              79      0.10%     98.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              69      0.09%     98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             561      0.73%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              77      0.10%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75             111      0.14%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              54      0.07%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              32      0.04%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               4      0.01%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.00%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.00%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.00%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.00%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             3      0.00%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            13      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             7      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            17      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             5      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             4      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143            12      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             5      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             5      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195            12      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           77129                       # Writes before turning the bus around for reads
system.physmem.totQLat                    38956691672                       # Total ticks spent queuing
system.physmem.totMemAccLat               61431060422                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   5993165000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       32500.93                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  51250.93                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.48                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.81                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.48                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.81                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.35                       # Average write queue length when enqueuing
system.physmem.readRowHits                     929087                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1069644                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.51                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.11                       # Row buffer hit rate for writes
system.physmem.avgGap                     19398017.87                       # Average gap between requests
system.physmem.pageHitRate                      75.09                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2341677240                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1244627175                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4066872600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3778956360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           50725624560.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            43528474080                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             3238135680                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       96319832910                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy       74142648000                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       12293580495315                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             12572988857670                       # Total energy per rank (pJ)
system.physmem_0.averagePower              243.244086                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           51584838283234                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE     6009063000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     21570724000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   51180529926500                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 193079953190                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     76356875016                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 211228448294                       # Time in different power states
system.physmem_1.actEnergy                 2391721500                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1271230125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4491367020                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3858107220                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           51763751520.000015                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            44789626440                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             3183541920                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       99591324540                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy       75005755680                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       12290774240265                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             12577142748300                       # Total energy per rank (pJ)
system.physmem_1.averagePower              243.324450                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           51582206485554                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE     5783812250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     22010710000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   51168482999000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 195327455894                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     78768252696                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 218401760160                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             16                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               261505306                       # Number of BP lookups
system.cpu.branchPred.condPredicted         182498706                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12291836                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            192874347                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               130159045                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             67.483855                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                31722667                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2144910                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         7175659                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            5109497                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses          2066162                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       844099                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                    574319                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                574319                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        21733                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       190269                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples       574319                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0          574319    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       574319                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       212002                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 25745.962302                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 21834.815515                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 18121.324193                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       209468     98.80%     98.80% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         2131      1.01%     99.81% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607          103      0.05%     99.86% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143          132      0.06%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679           91      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           29      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751           12      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287            3      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359           29      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::786432-851967            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       212002                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    316311704                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       316311704    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    316311704                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        190270     89.75%     89.75% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         21733     10.25%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       212003                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       574319                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       574319                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       212003                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       212003                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       786322                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    182769858                       # DTB read hits
system.cpu.dtb.read_misses                     473161                       # DTB read misses
system.cpu.dtb.write_hits                   162201881                       # DTB write hits
system.cpu.dtb.write_misses                    101158                       # DTB write misses
system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               47051                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1109                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    79796                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1477                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  15505                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     23270                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                183243019                       # DTB read accesses
system.cpu.dtb.write_accesses               162303039                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         344971739                       # DTB hits
system.cpu.dtb.misses                          574319                       # DTB misses
system.cpu.dtb.accesses                     345546058                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                    135751                       # Table walker walks requested
system.cpu.itb.walker.walksLong                135751                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1056                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       117755                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       135751                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          135751    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       135751                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       118811                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 28810.606762                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24143.293111                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 28291.561253                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       115975     97.61%     97.61% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071         2399      2.02%     99.63% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607          123      0.10%     99.74% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143          101      0.09%     99.82% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679           44      0.04%     99.86% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           20      0.02%     99.87% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751            3      0.00%     99.88% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            3      0.00%     99.88% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%     99.88% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359          141      0.12%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       118811                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    315425204                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       315425204    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    315425204                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        117755     99.11%     99.11% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1056      0.89%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       118811                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       135751                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       135751                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       118811                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       118811                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       254562                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    452655900                       # ITB inst hits
system.cpu.itb.inst_misses                     135751                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               47051                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1109                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    57242                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    322846                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                452791651                       # ITB inst accesses
system.cpu.itb.hits                         452655900                       # DTB hits
system.cpu.itb.misses                          135751                       # DTB misses
system.cpu.itb.accesses                     452791651                       # DTB accesses
system.cpu.numPwrStateTransitions               33180                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples         16590                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     3039388324.246233                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    59640903157.908096                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows         7293     43.96%     43.96% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10         9262     55.83%     99.79% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.82% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            2      0.01%     99.83% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            2      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::6e+11-6.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::8.5e+11-9e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 1988777698120                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total           16590                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    1265322690755                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 50423452299245                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                       2530699433                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   946928269                       # Number of instructions committed
system.cpu.committedOps                    1112623169                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      97851669                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      7730                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                 100847957157                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.672536                       # CPI: cycles per instruction
system.cpu.ipc                               0.374177                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                   1      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu               771151081     69.31%     69.31% # Class of committed instruction
system.cpu.op_class_0::IntMult                2302642      0.21%     69.52% # Class of committed instruction
system.cpu.op_class_0::IntDiv                   99189      0.01%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     8      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                    13      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                    21      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc                 0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatMisc               108989      0.01%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::MemRead              177200146     15.93%     85.46% # Class of committed instruction
system.cpu.op_class_0::MemWrite             160983743     14.47%     99.93% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead            112460      0.01%     99.94% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite           664876      0.06%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total               1112623169                       # Class of committed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16590                       # number of quiesce instructions executed
system.cpu.tickCycles                      1791525295                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       739174138                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements          11091024                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.954083                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           329234475                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          11091536                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.683398                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4655908500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.954083                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999910                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999910                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          384                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           62                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1381544711                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1381544711                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    168600534                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       168600534                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    151416750                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      151416750                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       521238                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        521238                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       337307                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       337307                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      4005998                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      4005998                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      4318996                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      4318996                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     320354591                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        320354591                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    320875829                       # number of overall hits
system.cpu.dcache.overall_hits::total       320875829                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      6093036                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       6093036                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      4287792                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      4287792                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1473735                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1473735                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1243168                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1243168                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       314729                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       314729                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     11623996                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       11623996                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     13097731                       # number of overall misses
system.cpu.dcache.overall_misses::total      13097731                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 107249746000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 107249746000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 169106972500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 169106972500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  27289591000                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  27289591000                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5063641000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   5063641000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        83000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        83000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 303646309500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 303646309500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 303646309500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 303646309500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    174693570                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    174693570                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    155704542                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    155704542                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1994973                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1994973                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1580475                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1580475                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4320727                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      4320727                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      4318997                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      4318997                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    331978587                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    331978587                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    333973560                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    333973560                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.034878                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.034878                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027538                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.027538                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.738724                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.738724                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786579                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.786579                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.072842                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.072842                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.035014                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.035014                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.039218                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.039218                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17602.020733                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17602.020733                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39439.173472                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39439.173472                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 21951.651748                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 21951.651748                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16088.892349                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16088.892349                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.368719                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26122.368719                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23183.123054                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23183.123054                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           19                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs           19                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      8512101                       # number of writebacks
system.cpu.dcache.writebacks::total           8512101                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       311042                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       311042                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1897692                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1897692                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          152                       # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total          152                       # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70889                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        70889                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2208886                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2208886                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2208886                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2208886                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5781994                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5781994                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2390100                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2390100                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1466271                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1466271                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1243016                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1243016                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       243840                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       243840                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9415110                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9415110                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data     10881381                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total     10881381                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33696                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33696                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67403                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  94763834000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  94763834000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  88482137000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  88482137000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  25605238500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  25605238500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  26041674000                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  26041674000                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3459340500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3459340500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        82000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        82000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 209287645000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 209287645000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 234892883500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 234892883500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6231136500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6231136500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6231136500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6231136500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033098                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033098                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015350                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015350                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.734983                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.734983                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786483                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786483                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.056435                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056435                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028361                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.028361                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032582                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.032582                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16389.472905                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16389.472905                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37020.265679                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37020.265679                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17462.828154                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17462.828154                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20950.393237                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20950.393237                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14186.927904                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14186.927904                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22228.911293                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22228.911293                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21586.679439                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21586.679439                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184922.142094                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184922.142094                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92445.981633                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92445.981633                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements          24547500                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.926335                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           427774095                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          24548012                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             17.426018                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       21430762500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.926335                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999856                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999856                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          292                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          126                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         476870138                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        476870138                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    427774095                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       427774095                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     427774095                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        427774095                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    427774095                       # number of overall hits
system.cpu.icache.overall_hits::total       427774095                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     24548022                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      24548022                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     24548022                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       24548022                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     24548022                       # number of overall misses
system.cpu.icache.overall_misses::total      24548022                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 329750158000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 329750158000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 329750158000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 329750158000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 329750158000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 329750158000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    452322117                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    452322117                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    452322117                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    452322117                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    452322117                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    452322117                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054271                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.054271                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.054271                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.054271                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.054271                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.054271                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13432.860619                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13432.860619                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13432.860619                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13432.860619                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13432.860619                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13432.860619                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks     24547500                       # number of writebacks
system.cpu.icache.writebacks::total          24547500                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24548022                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     24548022                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     24548022                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     24548022                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     24548022                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     24548022                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52291                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        52291                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52291                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        52291                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305202137000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 305202137000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305202137000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 305202137000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305202137000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 305202137000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   4421533000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   4421533000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   4421533000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   4421533000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054271                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054271                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054271                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.054271                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054271                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.054271                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12432.860660                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12432.860660                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12432.860660                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12432.860660                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12432.860660                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12432.860660                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 84556.290757                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 84556.290757                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 84556.290757                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 84556.290757                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements          1591901                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65408.549959                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           69520908                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1655396                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            41.996542                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       6255171000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  9036.958133                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   433.683776                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   402.305370                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  7871.756997                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 47663.845683                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.137893                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.006617                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006139                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.120113                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.727293                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.998055                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          271                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63224                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          271                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          790                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5976                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56108                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004135                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.964722                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        582399864                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       582399864                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       921588                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       261482                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1183070                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks      8512101                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      8512101                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks     24543775                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total     24543775                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data        29573                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        29573                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1660508                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1660508                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24440962                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     24440962                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7164937                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      7164937                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       700668                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       700668                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       921588                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       261482                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     24440962                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      8825445                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        34449477                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       921588                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       261482                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     24440962                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      8825445                       # number of overall hits
system.cpu.l2cache.overall_hits::total       34449477                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6273                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5180                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        11453                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         4073                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         4073                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       696158                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       696158                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       107059                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total       107059                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       326956                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       326956                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       542348                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       542348                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         6273                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         5180                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst       107059                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1023114                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1141626                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         6273                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         5180                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst       107059                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1023114                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1141626                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    939749000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    683365000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1623114000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     72777000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     72777000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        80500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total        80500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  66999821500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  66999821500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  11524194500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total  11524194500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  37120013000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  37120013000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data      2135500                       # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total      2135500                       # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    939749000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    683365000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  11524194500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 104119834500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 117267143000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    939749000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    683365000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  11524194500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 104119834500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 117267143000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       927861                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       266662                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1194523                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks      8512101                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      8512101                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks     24543775                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total     24543775                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        33646                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        33646                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2356666                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2356666                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24548021                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     24548021                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7491893                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      7491893                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1243016                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1243016                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       927861                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       266662                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     24548021                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9848559                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     35591103                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       927861                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       266662                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     24548021                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9848559                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     35591103                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006761                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.019425                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.009588                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.121055                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.121055                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.295400                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.295400                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004361                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004361                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043641                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043641                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.436316                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.436316                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006761                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.019425                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004361                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.103885                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.032076                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006761                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.019425                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004361                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.103885                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.032076                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 149808.544556                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 131923.745174                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 141719.549463                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17868.156150                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17868.156150                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96242.263251                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96242.263251                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107643.397566                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107643.397566                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 113532.135823                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 113532.135823                       # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data     3.937509                       # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total     3.937509                       # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 149808.544556                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 131923.745174                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107643.397566                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101767.578686                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 102719.404604                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 149808.544556                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 131923.745174                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107643.397566                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101767.578686                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 102719.404604                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks      1356118                       # number of writebacks
system.cpu.l2cache.writebacks::total          1356118                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           24                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6273                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5180                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        11453                       # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            3                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total            3                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4073                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         4073                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       696158                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       696158                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       107056                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total       107056                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       326935                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       326935                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       542348                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       542348                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6273                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5180                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       107056                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1023093                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1141602                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6273                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5180                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       107056                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1023093                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1141602                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52291                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33696                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        85987                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52291                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119694                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    877019000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    631565000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1508584000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     77761500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     77761500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        70500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        70500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60038241001                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60038241001                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10453433004                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10453433004                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33849413548                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33849413548                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  11199554001                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  11199554001                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    877019000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    631565000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10453433004                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  93887654549                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 105849671553                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    877019000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    631565000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10453433004                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  93887654549                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 105849671553                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3611009000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5809783000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   9420792000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3611009000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5809783000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9420792000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006761                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.019425                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.009588                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.121055                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.121055                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.295400                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.295400                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004361                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004361                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043639                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043639                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.436316                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.436316                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006761                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.019425                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004361                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.103883                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.032075                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006761                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.019425                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004361                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.103883                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.032075                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 121923.745174                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131719.549463                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19091.946968                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19091.946968                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86242.262534                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86242.262534                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97644.531871                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97644.531871                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103535.606613                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103535.606613                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20650.125014                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20650.125014                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 121923.745174                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97644.531871                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91768.445829                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92720.292670                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139808.544556                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 121923.745174                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97644.531871                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91768.445829                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92720.292670                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69056.032587                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172417.586657                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109560.654518                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69056.032587                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.724270                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78707.303624                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests     72021080                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     36381496                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4425                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1940                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1940                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq        1770978                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      33811680                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33707                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33707                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      9868219                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean     24547500                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2814706                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        33649                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        33650                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2356666                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2356666                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     24548022                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      7494335                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1271849                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1243016                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     73748124                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     33477065                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       672528                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2206986                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total         110104703                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3145459904                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1175323090                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2133296                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7422888                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         4330339178                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     2114439                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic              90765792                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples     39101108                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.018304                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.134047                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           38385418     98.17%     98.17% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             715690      1.83%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       39101108                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    69634684493                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1487890                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   36904751913                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   15462672587                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     405908415                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1279140469                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40325                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40325                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231008                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231008                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353792                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334464                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334464                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492384                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             37691500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               338000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               16000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25239000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36441500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           569511366                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147768000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115486                       # number of replacements
system.iocache.tags.tagsinuse               10.448155                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115502                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13141696144000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.519387                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.928768                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219962                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.433048                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653010                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039893                       # Number of tag accesses
system.iocache.tags.data_accesses             1039893                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8840                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8877                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115504                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115544                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115504                       # number of overall misses
system.iocache.overall_misses::total           115544                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5085500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   2067712004                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   2072797504                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13276938862                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13276938862                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5436500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  15344650866                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  15350087366                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5436500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  15344650866                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  15350087366                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8840                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8877                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115504                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115544                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115504                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115544                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 233904.072851                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 233502.028163                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124474.413692                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 124474.413692                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 132849.519203                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 132850.579571                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 132849.519203                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 132850.579571                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         54006                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3503                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    15.417071                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8840                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8877                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115504                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115544                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115504                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115544                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3235500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1625712004                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1628947504                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7936726922                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7936726922                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3436500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9562438926                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9565875426                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3436500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9562438926                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9565875426                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 183904.072851                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 183502.028163                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74408.675111                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74408.675111                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 82788.811868                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 82789.893253                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 82788.811868                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 82789.893253                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests       3510315                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      1740308                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3085                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               85987                       # Transaction distribution
system.membus.trans_dist::ReadResp             540308                       # Transaction distribution
system.membus.trans_dist::WriteReq              33707                       # Transaction distribution
system.membus.trans_dist::WriteResp             33707                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1462749                       # Transaction distribution
system.membus.trans_dist::CleanEvict           243530                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4703                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               7                       # Transaction distribution
system.membus.trans_dist::ReadExReq            695596                       # Transaction distribution
system.membus.trans_dist::ReadExResp           695596                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        454321                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        648947                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4528935                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4658587                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237673                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237673                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4896260                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13832                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    163142636                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    163313042                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7249536                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7249536                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               170562578                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             2899                       # Total snoops (count)
system.membus.snoopTraffic                     185088                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           1923263                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.016618                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.127834                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 1891303     98.34%     98.34% # Request fanout histogram
system.membus.snoop_fanout::1                   31960      1.66%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             1923263                       # Request fanout histogram
system.membus.reqLayer0.occupancy            99811000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5612500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9664854495                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         6432615655                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           44921497                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688774990000                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------
