
---------- Begin Simulation Statistics ----------
sim_seconds                                 47.405013                       # Number of seconds simulated
sim_ticks                                47405012960500                       # Number of ticks simulated
final_tick                               47405012960500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1080699                       # Simulator instruction rate (inst/s)
host_op_rate                                  1271286                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            58247547339                       # Simulator tick rate (ticks/s)
host_mem_usage                                 759864                       # Number of bytes of host memory used
host_seconds                                   813.85                       # Real time elapsed on the host
sim_insts                                   879531552                       # Number of instructions simulated
sim_ops                                    1034641707                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       107584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       111616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3269620                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         13856200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     15427200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       122176                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       126272                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2852024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          9626320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     10834112                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        432576                       # Number of bytes read from this memory
system.physmem.bytes_read::total             56765700                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3269620                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2852024                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6121644                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     74832256                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          74852840                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1681                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1744                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             91495                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            216516                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       241050                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1909                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1973                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             44651                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            150424                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       169283                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6759                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                927485                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1169254                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1171828                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2269                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2355                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               68972                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              292294                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       325434                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2577                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2664                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               60163                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              203065                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       228544                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9125                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1197462                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          68972                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          60163                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             129135                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1578573                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1579007                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1578573                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2269                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2355                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              68972                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             292728                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       325434                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2577                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2664                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              60163                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             203066                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       228544                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9125                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2776469                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        927485                       # Number of read requests accepted
system.physmem.writeReqs                      1171828                       # Number of write requests accepted
system.physmem.readBursts                      927485                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1171828                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 59337472                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     21568                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  74850880                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  56765700                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               74852840                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      337                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2262                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               53188                       # Per bank write bursts
system.physmem.perBankRdBursts::1               58555                       # Per bank write bursts
system.physmem.perBankRdBursts::2               49548                       # Per bank write bursts
system.physmem.perBankRdBursts::3               58849                       # Per bank write bursts
system.physmem.perBankRdBursts::4               61060                       # Per bank write bursts
system.physmem.perBankRdBursts::5               64213                       # Per bank write bursts
system.physmem.perBankRdBursts::6               58593                       # Per bank write bursts
system.physmem.perBankRdBursts::7               62574                       # Per bank write bursts
system.physmem.perBankRdBursts::8               53530                       # Per bank write bursts
system.physmem.perBankRdBursts::9               96457                       # Per bank write bursts
system.physmem.perBankRdBursts::10              50033                       # Per bank write bursts
system.physmem.perBankRdBursts::11              57571                       # Per bank write bursts
system.physmem.perBankRdBursts::12              47029                       # Per bank write bursts
system.physmem.perBankRdBursts::13              51615                       # Per bank write bursts
system.physmem.perBankRdBursts::14              49510                       # Per bank write bursts
system.physmem.perBankRdBursts::15              54823                       # Per bank write bursts
system.physmem.perBankWrBursts::0               69378                       # Per bank write bursts
system.physmem.perBankWrBursts::1               74382                       # Per bank write bursts
system.physmem.perBankWrBursts::2               69427                       # Per bank write bursts
system.physmem.perBankWrBursts::3               75087                       # Per bank write bursts
system.physmem.perBankWrBursts::4               76532                       # Per bank write bursts
system.physmem.perBankWrBursts::5               78990                       # Per bank write bursts
system.physmem.perBankWrBursts::6               75385                       # Per bank write bursts
system.physmem.perBankWrBursts::7               77589                       # Per bank write bursts
system.physmem.perBankWrBursts::8               70916                       # Per bank write bursts
system.physmem.perBankWrBursts::9               76207                       # Per bank write bursts
system.physmem.perBankWrBursts::10              70858                       # Per bank write bursts
system.physmem.perBankWrBursts::11              75862                       # Per bank write bursts
system.physmem.perBankWrBursts::12              66596                       # Per bank write bursts
system.physmem.perBankWrBursts::13              70423                       # Per bank write bursts
system.physmem.perBankWrBursts::14              68869                       # Per bank write bursts
system.physmem.perBankWrBursts::15              73044                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         516                       # Number of times write queue was full causing retry
system.physmem.totGap                    47405009605000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  884260                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1169254                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    645919                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     88942                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     42222                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     33520                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     28634                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     25074                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     21962                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     18312                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     15502                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2962                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1110                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      816                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      608                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      446                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      314                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      249                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      195                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      169                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      100                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       79                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    28620                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    36458                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    48218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    54653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    60726                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    63711                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    65994                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    67665                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    70176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    70363                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    73600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    75174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    72029                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    70698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    71278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    75021                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    68576                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    65669                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     3787                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2027                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1477                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1063                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      975                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1013                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      865                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      814                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      756                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      763                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      668                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      705                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      747                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      666                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      760                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      682                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      648                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      743                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      716                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      785                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      937                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      852                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      928                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                     1380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                     1236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      535                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                     1170                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       929017                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      144.440810                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      98.331936                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     191.352121                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         617371     66.45%     66.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       189527     20.40%     86.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        44674      4.81%     91.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        20356      2.19%     93.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        14838      1.60%     95.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         9142      0.98%     96.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         6196      0.67%     97.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5371      0.58%     97.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        21542      2.32%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         929017                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         60832                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        15.240992                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      130.606668                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          60830    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           60832                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         60832                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.225819                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.418138                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        8.471341                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           49295     81.03%     81.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            4521      7.43%     88.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            2878      4.73%     93.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31            1749      2.88%     96.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35            1023      1.68%     97.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             226      0.37%     98.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              91      0.15%     98.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47             113      0.19%     98.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              47      0.08%     98.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              23      0.04%     98.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              10      0.02%     98.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              42      0.07%     98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             494      0.81%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              82      0.13%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              51      0.08%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              57      0.09%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              26      0.04%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.00%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               4      0.01%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.00%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             5      0.01%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             4      0.01%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            14      0.02%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            21      0.03%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             3      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143            13      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             4      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             3      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-243             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           60832                       # Writes before turning the bus around for reads
system.physmem.totQLat                    46218732203                       # Total ticks spent queuing
system.physmem.totMemAccLat               63602757203                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4635740000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       49850.44                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  68600.44                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.25                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.58                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.20                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.58                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.15                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.09                       # Average write queue length when enqueuing
system.physmem.readRowHits                     685692                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    481982                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   73.96                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  41.21                       # Row buffer hit rate for writes
system.physmem.avgGap                     22581201.38                       # Average gap between requests
system.physmem.pageHitRate                      55.69                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3446827860                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1832028660                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3331381200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3115139400                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           41510941680.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            46501533090                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             2234866560                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       80625696300                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy       57761558880                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       11279719224960                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             11520096687780                       # Total energy per rank (pJ)
system.physmem_0.averagePower              243.014314                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           47297174723637                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE     3911587994                       # Time in different power states
system.physmem_0.memoryStateTime::REF     17636282000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   46969945639000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 150420602883                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     86288423369                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 176810425254                       # Time in different power states
system.physmem_1.actEnergy                 3186367800                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1693590855                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3288455520                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               2989885500                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           39461117280.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            47361781080                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             2153404320                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       72224847060                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy       55366694400                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       11285008491285                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             11512750460370                       # Total energy per rank (pJ)
system.physmem_1.averagePower              242.859346                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           47295506898407                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE     3731843770                       # Time in different power states
system.physmem_1.memoryStateTime::REF     16766470000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   46992934432500                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 144184093324                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     89007700573                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 158388420333                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   110745                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               110745                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10295                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        84545                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore           22                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       110723                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean     0.234820                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev    78.136585                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-2047       110722    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       110723                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        94862                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 23879.314162                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 22054.085361                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 16759.177694                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535        93763     98.84%     98.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          840      0.89%     99.73% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          113      0.12%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           60      0.06%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           52      0.05%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           15      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            1      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359           13      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        94862                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  -2682325288                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     2.121047                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     3007013124   -112.10%   -112.10% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1    -5689338412    212.10%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  -2682325288                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        84546     89.14%     89.14% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        10295     10.86%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        94841                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       110745                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       110745                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        94841                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        94841                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       205586                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    86849149                       # DTB read hits
system.cpu0.dtb.read_misses                     83538                       # DTB read misses
system.cpu0.dtb.write_hits                   78785461                       # DTB write hits
system.cpu0.dtb.write_misses                    27207                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              41059                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   37555                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4746                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     9443                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                86932687                       # DTB read accesses
system.cpu0.dtb.write_accesses               78812668                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        165634610                       # DTB hits
system.cpu0.dtb.misses                         110745                       # DTB misses
system.cpu0.dtb.accesses                    165745355                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    57780                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                57780                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          572                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        51544                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        57780                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          57780    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        57780                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        52116                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 25803.102694                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23425.328726                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 22386.426518                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        51056     97.97%     97.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          692      1.33%     99.29% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          219      0.42%     99.71% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           60      0.12%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           50      0.10%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           14      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            4      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359           14      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::655360-720895            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        52116                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples     14842204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0       14842204    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total     14842204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        51544     98.90%     98.90% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          572      1.10%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        52116                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        57780                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        57780                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52116                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52116                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       109896                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   463942995                       # ITB inst hits
system.cpu0.itb.inst_misses                     57780                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              41059                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   26477                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               464000775                       # ITB inst accesses
system.cpu0.itb.hits                        463942995                       # DTB hits
system.cpu0.itb.misses                          57780                       # DTB misses
system.cpu0.itb.accesses                    464000775                       # DTB accesses
system.cpu0.numPwrStateTransitions               8984                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         4492                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    10426010818.709705                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   169261679723.888153                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         3260     72.57%     72.57% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         1205     26.83%     99.40% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            8      0.18%     99.58% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.02%     99.60% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            2      0.04%     99.64% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            2      0.04%     99.69% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            1      0.02%     99.71% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.02%     99.73% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows           12      0.27%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 7033293863000                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           4492                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   571372362856                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46833640597644                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                     94810025915                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    4492                       # number of quiesce instructions executed
system.cpu0.committedInsts                  463690677                       # Number of instructions committed
system.cpu0.committedOps                    544305781                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            499985272                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                430429                       # Number of float alu accesses
system.cpu0.num_func_calls                   27825312                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     70353837                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   499985272                       # number of integer instructions
system.cpu0.num_fp_insts                       430429                       # number of float instructions
system.cpu0.num_int_register_reads          725660016                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         396645033                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              713342                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             322808                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           121489824                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          121106505                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    165624912                       # number of memory refs
system.cpu0.num_load_insts                   86844124                       # Number of load instructions
system.cpu0.num_store_insts                  78780788                       # Number of store instructions
system.cpu0.num_idle_cycles              93667281189.358337                       # Number of idle cycles
system.cpu0.num_busy_cycles              1142744725.641658                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.012053                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.987947                       # Percentage of idle cycles
system.cpu0.Branches                        103560532                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                377679680     69.35%     69.35% # Class of executed instruction
system.cpu0.op_class::IntMult                 1190205      0.22%     69.57% # Class of executed instruction
system.cpu0.op_class::IntDiv                    61578      0.01%     69.58% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.58% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.58% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.58% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.58% # Class of executed instruction
system.cpu0.op_class::FloatMultAcc                  0      0.00%     69.58% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.58% # Class of executed instruction
system.cpu0.op_class::FloatMisc                 44848      0.01%     69.59% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.59% # Class of executed instruction
system.cpu0.op_class::MemRead                86795135     15.94%     85.53% # Class of executed instruction
system.cpu0.op_class::MemWrite               78444196     14.40%     99.93% # Class of executed instruction
system.cpu0.op_class::FloatMemRead              48989      0.01%     99.94% # Class of executed instruction
system.cpu0.op_class::FloatMemWrite            336592      0.06%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 544601223                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements          5731745                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          479.859189                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          159669170                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5732255                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.854513                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       4328406000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   479.859189                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.937225                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.937225                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          452                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        337018109                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       337018109                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     80850678                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       80850678                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     74290365                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      74290365                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       206988                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       206988                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       237888                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       237888                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1848102                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1848102                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1813975                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1813975                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    155378931                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       155378931                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    155585919                       # number of overall hits
system.cpu0.dcache.overall_hits::total      155585919                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3109712                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3109712                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1421405                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1421405                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       649654                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       649654                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       796576                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       796576                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       167654                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       167654                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       200528                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       200528                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      5327693                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       5327693                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5977347                       # number of overall misses
system.cpu0.dcache.overall_misses::total      5977347                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  48841831500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  48841831500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  30112535000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  30112535000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  25700725500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  25700725500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2575322000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2575322000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4758884500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4758884500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2246000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2246000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 104655092000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 104655092000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 104655092000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 104655092000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     83960390                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     83960390                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     75711770                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     75711770                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       856642                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       856642                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1034464                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1034464                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2015756                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2015756                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2014503                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2014503                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    160706624                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    160706624                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    161563266                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    161563266                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.037038                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.037038                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018774                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.018774                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.758373                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.758373                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.770037                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.770037                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.083172                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.083172                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.099542                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.099542                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.033152                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.033152                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.036997                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.036997                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15706.223438                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15706.223438                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21185.049300                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 21185.049300                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32263.996781                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32263.996781                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15360.933828                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15360.933828                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23731.770626                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23731.770626                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19643.604089                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19643.604089                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17508.619125                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17508.619125                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      5731745                       # number of writebacks
system.cpu0.dcache.writebacks::total          5731745                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        26385                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        26385                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21245                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21245                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        44162                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        44162                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        47630                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        47630                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        47630                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        47630                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3083327                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3083327                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1400160                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1400160                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       648080                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       648080                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       796576                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       796576                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       123492                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       123492                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       200528                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       200528                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      5280063                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5280063                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5928143                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5928143                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16381                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        16381                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        17694                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        17694                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34075                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34075                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  44323294000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  44323294000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  28148510000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  28148510000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14944693500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14944693500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  24904149500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24904149500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1681387500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1681387500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4558410500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4558410500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2192000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2192000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  97375953500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  97375953500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112320647000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 112320647000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3040589500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3040589500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3040589500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3040589500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036724                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036724                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018493                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018493                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.756535                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.756535                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.770037                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.770037                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061263                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.061263                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.099542                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.099542                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.032855                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.032855                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.036692                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.036692                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14375.151906                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14375.151906                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20103.780996                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20103.780996                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23059.951703                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23059.951703                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31263.996781                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31263.996781                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13615.355651                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13615.355651                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22732.039915                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22732.039915                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18442.195387                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18442.195387                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.020509                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.020509                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185616.842684                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185616.842684                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89232.267058                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89232.267058                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          4959559                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.903947                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          458982923                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          4960071                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            92.535555                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      30768955000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.903947                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999812                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999812                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          421                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        932846061                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       932846061                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    458982923                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      458982923                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    458982923                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       458982923                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    458982923                       # number of overall hits
system.cpu0.icache.overall_hits::total      458982923                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      4960072                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      4960072                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      4960072                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       4960072                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      4960072                       # number of overall misses
system.cpu0.icache.overall_misses::total      4960072                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  54306348500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  54306348500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  54306348500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  54306348500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  54306348500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  54306348500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    463942995                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    463942995                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    463942995                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    463942995                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    463942995                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    463942995                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010691                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.010691                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010691                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.010691                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010691                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.010691                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10948.701652                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10948.701652                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10948.701652                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10948.701652                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10948.701652                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10948.701652                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      4959559                       # number of writebacks
system.cpu0.icache.writebacks::total          4959559                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4960072                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      4960072                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      4960072                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      4960072                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      4960072                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      4960072                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  51826313000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  51826313000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  51826313000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  51826313000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  51826313000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  51826313000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4116534000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4116534000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4116534000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   4116534000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010691                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010691                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010691                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.010691                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010691                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.010691                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10448.701753                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10448.701753                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10448.701753                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10448.701753                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10448.701753                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10448.701753                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7732053                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7732077                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           21                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1019171                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements         2286879                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15893.622807                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           9162734                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2302009                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            3.980321                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      5406430500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15603.896064                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    29.949034                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    16.856945                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   242.920764                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.952386                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.001828                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001029                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.014827                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.970070                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          306                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           67                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14757                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          100                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          139                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           67                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           42                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4608                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         8403                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1616                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.018677                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004089                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.900696                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       368793343                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      368793343                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       252482                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       146217                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        398699                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      3794669                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      3794669                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      6895627                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      6895627                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       932984                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       932984                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4503327                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      4503327                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2919116                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2919116                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       217183                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       217183                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       252482                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       146217                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4503327                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3852100                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8754126                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       252482                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       146217                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4503327                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3852100                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8754126                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        17757                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8990                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        26747                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       236502                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       236502                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       200518                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       200518                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           10                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total           10                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       248602                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       248602                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       456745                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       456745                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       935783                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       935783                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       577322                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       577322                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        17757                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8990                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       456745                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1184385                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1667877                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        17757                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8990                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       456745                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1184385                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1667877                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    557104000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    362043000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total    919147000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    930109500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    930109500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    320714500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    320714500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2109497                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2109497                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  13818048499                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  13818048499                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  17338170000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  17338170000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  36151090000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  36151090000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    305279500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total    305279500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    557104000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    362043000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  17338170000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  49969138499                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  68226455499                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    557104000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    362043000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  17338170000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  49969138499                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  68226455499                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       270239                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       155207                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       425446                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3794669                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      3794669                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      6895627                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      6895627                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       236502                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       236502                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       200518                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       200518                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           10                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           10                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1181586                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1181586                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      4960072                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      4960072                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3854899                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3854899                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       794505                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       794505                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       270239                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       155207                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      4960072                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5036485                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     10422003                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       270239                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       155207                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      4960072                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5036485                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     10422003                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.065709                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.057923                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.062868                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.210397                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.210397                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.092084                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.092084                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.242752                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.242752                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.726644                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.726644                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.065709                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.057923                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.092084                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.235161                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.160034                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.065709                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.057923                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.092084                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.235161                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.160034                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31373.768091                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 40271.746385                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34364.489475                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3932.776467                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3932.776467                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1599.429976                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1599.429976                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 210949.700000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 210949.700000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55583.014211                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55583.014211                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37960.284185                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37960.284185                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38631.915733                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38631.915733                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   528.785496                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   528.785496                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31373.768091                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 40271.746385                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37960.284185                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42189.945414                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 40906.167241                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31373.768091                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 40271.746385                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37960.284185                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42189.945414                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 40906.167241                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           38115                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks      1518116                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1518116                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         6419                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         6419                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          459                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          459                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6878                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         6878                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6878                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         6878                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        17757                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8990                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        26747                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       749864                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       749864                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       236502                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       236502                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       200518                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       200518                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           10                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           10                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       242183                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       242183                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       456745                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       456745                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       935324                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       935324                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       577322                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       577322                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        17757                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8990                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       456745                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1177507                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1660999                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        17757                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8990                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       456745                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1177507                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       749864                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2410863                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        16381                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        59506                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        17694                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        17694                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        34075                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        77200                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    450562000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    308103000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    758665000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  37032584946                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  37032584946                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4392780000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4392780000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3053423000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3053423000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1785497                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1785497                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  11646133999                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  11646133999                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  14597700000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  14597700000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  30480683500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  30480683500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  18786696000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  18786696000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    450562000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    308103000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  14597700000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  42126817499                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  57483182499                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    450562000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    308103000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  14597700000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  42126817499                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  37032584946                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  94515767445                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3793096500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2909184500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6702281000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3793096500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   2909184500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6702281000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.065709                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.057923                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.062868                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.204964                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.204964                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.092084                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.092084                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.242633                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.242633                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.726644                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.726644                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.065709                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.057923                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.092084                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.233795                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.159374                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.065709                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.057923                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.092084                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.233795                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.231324                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28364.489475                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49385.735208                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18573.965548                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18573.965548                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15227.675321                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15227.675321                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178549.700000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178549.700000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48088.156473                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48088.156473                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31960.284185                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31960.284185                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32588.368843                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32588.368843                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32541.105310                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32541.105310                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31960.284185                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35776.277762                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34607.596091                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31960.284185                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35776.277762                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39204.122111                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177595.049142                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112632.020300                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85375.920763                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86817.111399                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests     22159208                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11368269                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1008                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       619514                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       619512                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            2                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        553426                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      9465318                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        17695                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        17694                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5316723                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      6896635                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      1098455                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       916448                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       433150                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       369627                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       506111                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           59                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          103                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1214944                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1192020                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      4960072                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4756139                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       842201                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       794505                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     14965952                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18512478                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       327835                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       591529                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         34397794                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    635028820                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    696134983                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1241656                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2161912                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1334567371                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    5130075                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic            104832276                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples     16684270                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.051566                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.221149                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          15823936     94.84%     94.84% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            860332      5.16%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 2      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      16684270                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   21945410994                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    195855793                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   7483231500                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8196031021                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    172628000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    321290000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                    99152                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong                99152                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         8586                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        75770                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            4                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        99148                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.080687                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    25.406685                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-511        99147    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::7680-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        99148                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        84360                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 24513.021574                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 22367.425597                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 18734.439703                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        83116     98.53%     98.53% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          940      1.11%     99.64% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          161      0.19%     99.83% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           58      0.07%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           36      0.04%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           23      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751            6      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359           16      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        84360                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples    407519048                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     2.490877                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     -607560648   -149.09%   -149.09% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1     1015079696    249.09%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total    407519048                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        75770     89.82%     89.82% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         8586     10.18%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        84356                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        99152                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        99152                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        84356                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        84356                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       183508                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    78885011                       # DTB read hits
system.cpu1.dtb.read_misses                     72039                       # DTB read misses
system.cpu1.dtb.write_hits                   71761800                       # DTB write hits
system.cpu1.dtb.write_misses                    27113                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              41059                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   36637                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  3802                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10123                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                78957050                       # DTB read accesses
system.cpu1.dtb.write_accesses               71788913                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        150646811                       # DTB hits
system.cpu1.dtb.misses                          99152                       # DTB misses
system.cpu1.dtb.accesses                    150745963                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    58316                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                58316                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          626                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        52495                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        58316                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          58316    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        58316                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        53121                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 27183.693831                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24219.790403                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 26514.333195                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        51734     97.39%     97.39% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          949      1.79%     99.18% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          242      0.46%     99.63% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           79      0.15%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           53      0.10%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           14      0.03%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            9      0.02%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            5      0.01%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359           33      0.06%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        53121                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   -615394148                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     -615394148    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   -615394148                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        52495     98.82%     98.82% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          626      1.18%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        53121                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        58316                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        58316                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        53121                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        53121                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       111437                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   416140593                       # ITB inst hits
system.cpu1.itb.inst_misses                     58316                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              41059                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   25699                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               416198909                       # ITB inst accesses
system.cpu1.itb.hits                        416140593                       # DTB hits
system.cpu1.itb.misses                          58316                       # DTB misses
system.cpu1.itb.accesses                    416198909                       # DTB accesses
system.cpu1.numPwrStateTransitions              28692                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples        14346                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    3269284130.341071                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   86001867955.202789                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         3953     27.55%     27.55% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10        10364     72.24%     99.80% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.83% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            3      0.02%     99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           14      0.10%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 7510077904252                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total          14346                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   503862826627                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 46901150133873                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                     94810025921                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   14346                       # number of quiesce instructions executed
system.cpu1.committedInsts                  415840875                       # Number of instructions committed
system.cpu1.committedOps                    490335926                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            450775425                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                467875                       # Number of float alu accesses
system.cpu1.num_func_calls                   24835210                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     63203882                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   450775425                       # number of integer instructions
system.cpu1.num_fp_insts                       467875                       # number of float instructions
system.cpu1.num_int_register_reads          655878523                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         357644258                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              746575                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             415812                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           107608929                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          107374492                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    150638767                       # number of memory refs
system.cpu1.num_load_insts                   78882725                       # Number of load instructions
system.cpu1.num_store_insts                  71756042                       # Number of store instructions
system.cpu1.num_idle_cycles              93802300267.744019                       # Number of idle cycles
system.cpu1.num_busy_cycles              1007725653.255979                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.010629                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.989371                       # Percentage of idle cycles
system.cpu1.Branches                         92635099                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                338840052     69.06%     69.06% # Class of executed instruction
system.cpu1.op_class::IntMult                 1031473      0.21%     69.27% # Class of executed instruction
system.cpu1.op_class::IntDiv                    58381      0.01%     69.28% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      8      0.00%     69.28% # Class of executed instruction
system.cpu1.op_class::FloatCmp                     13      0.00%     69.28% # Class of executed instruction
system.cpu1.op_class::FloatCvt                     21      0.00%     69.28% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.28% # Class of executed instruction
system.cpu1.op_class::FloatMultAcc                  0      0.00%     69.28% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.28% # Class of executed instruction
system.cpu1.op_class::FloatMisc                 67037      0.01%     69.30% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.30% # Class of executed instruction
system.cpu1.op_class::MemRead                78824615     16.07%     85.36% # Class of executed instruction
system.cpu1.op_class::MemWrite               71413356     14.56%     99.92% # Class of executed instruction
system.cpu1.op_class::FloatMemRead              58110      0.01%     99.93% # Class of executed instruction
system.cpu1.op_class::FloatMemWrite            342686      0.07%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 490635753                       # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements          4949273                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          456.328608                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          145491110                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          4949785                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            29.393420                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8379669141000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   456.328608                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.891267                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.891267                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          415                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           36                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        306227498                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       306227498                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data     73475131                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       73475131                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     68103188                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      68103188                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       168046                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       168046                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data        87192                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total        87192                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1644934                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1644934                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1602204                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1602204                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    141665511                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       141665511                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    141833557                       # number of overall hits
system.cpu1.dcache.overall_hits::total      141833557                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      2804863                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      2804863                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1292961                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1292961                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       609189                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       609189                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       443031                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       443031                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       160663                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       160663                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       202242                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       202242                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4540855                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4540855                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      5150044                       # number of overall misses
system.cpu1.dcache.overall_misses::total      5150044                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  42649111500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  42649111500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  25017964000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  25017964000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  10518897000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  10518897000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2505987000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2505987000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4791659000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4791659000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2159000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2159000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  78185972500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  78185972500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  78185972500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  78185972500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     76279994                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     76279994                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     69396149                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     69396149                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       777235                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       777235                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       530223                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       530223                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1805597                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1805597                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1804446                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1804446                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    146206366                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    146206366                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    146983601                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    146983601                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036771                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.036771                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018632                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018632                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.783790                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.783790                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.835556                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.835556                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.088981                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.088981                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.112080                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.112080                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031058                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.031058                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035038                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.035038                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.416985                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.416985                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19349.357019                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 19349.357019                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23743.027012                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23743.027012                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15597.785427                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15597.785427                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23692.699835                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23692.699835                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17218.337185                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17218.337185                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15181.612526                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15181.612526                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks      4949273                       # number of writebacks
system.cpu1.dcache.writebacks::total          4949273                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18154                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        18154                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          423                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total          423                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        43805                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        43805                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        18577                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        18577                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        18577                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        18577                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2786709                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2786709                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1292538                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1292538                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       609189                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       609189                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       443031                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       443031                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       116858                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       116858                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       202242                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       202242                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4522278                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4522278                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5131467                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5131467                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        22203                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        22203                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        20755                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        20755                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        42958                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        42958                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38628648000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38628648000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  23695979500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  23695979500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13886318000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13886318000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  10075866000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  10075866000                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1623112500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1623112500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4589466000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4589466000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2110000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2110000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  72400493500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  72400493500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  86286811500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  86286811500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3923399500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3923399500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3923399500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3923399500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036533                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036533                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018626                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018626                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.783790                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.783790                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.835556                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.835556                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064720                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.064720                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.112080                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.112080                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030931                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.030931                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034912                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.034912                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13861.744445                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13861.744445                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18332.907427                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18332.907427                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22794.761560                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22794.761560                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22743.027012                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22743.027012                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13889.613890                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13889.613890                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22692.942119                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22692.942119                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16009.739671                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16009.739671                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16815.232662                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16815.232662                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176705.828041                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176705.828041                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91331.055915                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91331.055915                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements          4981311                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.212019                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          411158765                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          4981823                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            82.531789                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8379594860000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.212019                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969164                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969164                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          314                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          140                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        837263014                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       837263014                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst    411158765                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      411158765                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    411158765                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       411158765                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    411158765                       # number of overall hits
system.cpu1.icache.overall_hits::total      411158765                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      4981828                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      4981828                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      4981828                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       4981828                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      4981828                       # number of overall misses
system.cpu1.icache.overall_misses::total      4981828                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  54111358000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  54111358000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  54111358000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  54111358000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  54111358000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  54111358000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    416140593                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    416140593                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    416140593                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    416140593                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    416140593                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    416140593                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011972                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.011972                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011972                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.011972                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011972                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.011972                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10861.747535                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10861.747535                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10861.747535                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10861.747535                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10861.747535                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10861.747535                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks      4981311                       # number of writebacks
system.cpu1.icache.writebacks::total          4981311                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4981828                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      4981828                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      4981828                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      4981828                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      4981828                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      4981828                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  51620444000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  51620444000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  51620444000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  51620444000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  51620444000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  51620444000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10472000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10472000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10472000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     10472000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011972                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011972                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011972                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.011972                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011972                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.011972                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10361.747535                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10361.747535                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10361.747535                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10361.747535                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10361.747535                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10361.747535                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        95200                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total        95200                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst        95200                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total        95200                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued      6872416                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      6872436                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           18                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       852028                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements         1861043                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       12976.163549                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           8767962                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         1876890                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            4.671537                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12709.863020                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    27.854479                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    23.050365                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   215.395684                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.775748                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001700                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.001407                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.013147                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.792002                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          377                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           55                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15415                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            6                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          137                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           69                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          165                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           25                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1400                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5858                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4122                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3918                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.023010                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003357                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.940857                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       342605185                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      342605185                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       220532                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       147847                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        368379                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3122709                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3122709                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      6807120                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      6807120                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       835381                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       835381                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4529100                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4529100                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2623579                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2623579                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       191618                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       191618                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       220532                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       147847                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4529100                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3458960                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8356439                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       220532                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       147847                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4529100                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3458960                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8356439                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        17957                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        10279                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        28236                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       208369                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       208369                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       202239                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       202239                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       250965                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       250965                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       452728                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       452728                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       889177                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       889177                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       249433                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       249433                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        17957                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker        10279                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       452728                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1140142                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1621106                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        17957                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker        10279                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       452728                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1140142                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1621106                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    590137500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    422641500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1012779000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    875652500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    875652500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    333590500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    333590500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2035999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2035999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  11238175000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  11238175000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  16933068500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  16933068500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  31773824000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  31773824000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    403814500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total    403814500                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    590137500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    422641500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  16933068500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  43011999000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  60957846500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    590137500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    422641500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  16933068500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  43011999000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  60957846500                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       238489                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       158126                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       396615                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3122709                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3122709                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      6807120                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      6807120                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       208369                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       208369                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       202239                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       202239                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1086346                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1086346                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4981828                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      4981828                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3512756                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3512756                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       441051                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       441051                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       238489                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       158126                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      4981828                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4599102                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total      9977545                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       238489                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       158126                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      4981828                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4599102                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total      9977545                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.075295                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.065005                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.071192                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.231018                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.231018                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.090876                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.090876                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.253128                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.253128                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.565542                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.565542                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.075295                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.065005                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.090876                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.247905                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.162475                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.075295                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.065005                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.090876                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.247905                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.162475                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32863.924932                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41116.986088                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 35868.359541                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4202.412547                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4202.412547                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1649.486499                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1649.486499                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 678666.333333                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 678666.333333                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44779.849780                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44779.849780                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37402.300057                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37402.300057                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35733.969727                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35733.969727                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1618.929733                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1618.929733                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32863.924932                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41116.986088                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37402.300057                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37725.124590                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 37602.628391                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32863.924932                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41116.986088                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37402.300057                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37725.124590                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 37602.628391                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches           38928                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks      1071108                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1071108                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         4423                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         4423                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          417                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          417                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4840                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         4840                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4840                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         4840                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        17957                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        10279                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        28236                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       666851                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       666851                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       208369                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       208369                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       202239                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       202239                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       246542                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       246542                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       452728                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       452728                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       888760                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       888760                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       249433                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       249433                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        17957                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        10279                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       452728                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1135302                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1616266                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        17957                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        10279                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       452728                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1135302                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       666851                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2283117                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        22203                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        22313                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        20755                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        20755                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        42958                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        43068                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    482395500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    360967500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    843363000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  27800562984                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  27800562984                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   3852073000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   3852073000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3071337500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3071337500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1741999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1741999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   9224946500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   9224946500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  14216700500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  14216700500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  26383538000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  26383538000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6621907000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6621907000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    482395500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    360967500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  14216700500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  35608484500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  50668548000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    482395500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    360967500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  14216700500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  35608484500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  27800562984                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  78469110984                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9647000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3745274000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3754921000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9647000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3745274000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3754921000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.075295                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.065005                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.071192                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.226946                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.226946                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.090876                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.090876                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.253009                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.253009                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.565542                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.565542                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.075295                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.065005                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.090876                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.246853                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.161990                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.075295                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.065005                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.090876                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.246853                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.228826                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29868.359541                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41689.317380                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18486.785462                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18486.785462                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15186.672699                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15186.672699                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 580666.333333                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 580666.333333                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37417.342684                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37417.342684                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31402.300057                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31402.300057                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29685.784689                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29685.784689                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26547.838498                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26547.838498                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31402.300057                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31364.768581                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31349.139312                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31402.300057                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31364.768581                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34369.290310                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        87700                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168683.241003                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168284.004840                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst        87700                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87184.552353                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87185.868859                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests     20600525                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10578683                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          754                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       558580                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       558580                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq        484798                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9068801                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        20755                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        20755                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4199993                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      6807874                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      1098101                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       809012                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       385894                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       368515                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       474989                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           57                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          103                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1114310                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1093127                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4981828                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4385137                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       490192                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       441051                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14945187                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16097398                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       332311                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       526789                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         31901685                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    637641336                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    617397659                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1265008                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1907912                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1258211915                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    4504290                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic             75632944                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples     15215883                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.052359                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.222750                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          14419192     94.76%     94.76% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            796691      5.24%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      15215883                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   20375325498                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    176794994                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   7472852000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7357432377                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    174185000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    288300000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40355                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40355                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136628                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136628                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47782                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122664                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231222                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231222                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353966                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47802                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155794                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338904                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338904                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36982500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                12500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               322500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               14000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            26451500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            37417000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           569427501                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92767000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147918000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115615                       # number of replacements
system.iocache.tags.tagsinuse               11.298649                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115631                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9136560427000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.416178                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.882471                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.463511                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.242654                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706166                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040856                       # Number of tag accesses
system.iocache.tags.data_accesses             1040856                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8883                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8920                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115611                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115651                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115611                       # number of overall misses
system.iocache.overall_misses::total           115651                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5193500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1828649003                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1833842503                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13346157998                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13346157998                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5562500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  15174807001                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  15180369501                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5562500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  15174807001                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  15180369501                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8883                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8920                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115611                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115651                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115611                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115651                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140364.864865                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 205859.394686                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 205587.724552                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125048.328442                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125048.328442                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139062.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 131257.466859                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 131260.166371                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139062.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 131257.466859                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 131260.166371                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         41899                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3535                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    11.852617                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106702                       # number of writebacks
system.iocache.writebacks::total               106702                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8883                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8920                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115611                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115651                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115611                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115651                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3343500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1384499003                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1387842503                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8000796585                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8000796585                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3562500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9385295588                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9388858088                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3562500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9385295588                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9388858088                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90364.864865                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 155859.394686                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 155587.724552                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74964.363475                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74964.363475                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89062.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 81179.953361                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 81182.679683                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89062.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 81179.953361                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 81182.679683                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1376932                       # number of replacements
system.l2c.tags.tagsinuse                65061.419917                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5975056                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1437120                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     4.157660                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               9858759500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   11843.449139                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   304.799159                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   356.696004                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3585.763677                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    19085.445505                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14223.146945                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   128.223998                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   149.509582                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3193.954857                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     6240.562219                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  5949.868833                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.180717                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.004651                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.005443                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.054714                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.291221                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.217028                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.001957                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.002281                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.048736                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.095223                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.090788                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.992758                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        11266                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          259                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        48663                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          152                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          297                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        10816                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          259                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          888                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4525                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        43209                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.171906                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003952                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.742538                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 68586261                       # Number of tag accesses
system.l2c.tags.data_accesses                68586261                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks      2589224                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2589224                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data          191644                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          164185                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              355829                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         48914                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         48173                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             97087                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            47737                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            58567                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               106304                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         9201                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         3860                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       408160                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       537157                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       271610                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        10477                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         5555                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       408048                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       521656                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       272486                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2448210                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       124551                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       127410                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           251961                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker          9201                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3860                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              408160                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              584894                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       271610                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         10477                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5555                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              408048                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              580223                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       272486                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2554514                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         9201                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3860                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             408160                       # number of overall hits
system.l2c.overall_hits::cpu0.data             584894                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       271610                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        10477                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5555                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             408048                       # number of overall hits
system.l2c.overall_hits::cpu1.data             580223                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       272486                       # number of overall hits
system.l2c.overall_hits::total                2554514                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         24439                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         23204                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             47643                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          628                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          554                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1182                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          75730                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          50449                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             126179                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1681                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1744                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        48585                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       141383                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       241091                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1909                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1973                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        44680                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       100605                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       169474                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         753125                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       440725                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       106525                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         547250                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1681                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1744                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             48585                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            217113                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       241091                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1909                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1973                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             44680                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            151054                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       169474                       # number of demand (read+write) misses
system.l2c.demand_misses::total                879304                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1681                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1744                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            48585                       # number of overall misses
system.l2c.overall_misses::cpu0.data           217113                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       241091                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1909                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1973                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            44680                       # number of overall misses
system.l2c.overall_misses::cpu1.data           151054                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       169474                       # number of overall misses
system.l2c.overall_misses::total               879304                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    162640000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    138377500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    301017500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      7502500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      7047000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total     14549500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   8218459999                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5520286999                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  13738746998                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    167721500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    180518500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   5556413500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  15487743000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  32099260605                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    194137000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    210753000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   5171670000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  11743795000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  22852256906                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  93664269011                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data     42596000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data     33301500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total     75897500                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    167721500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    180518500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   5556413500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  23706202999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  32099260605                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    194137000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    210753000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   5171670000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  17264081999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  22852256906                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    107403016009                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    167721500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    180518500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   5556413500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  23706202999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  32099260605                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    194137000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    210753000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   5171670000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  17264081999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  22852256906                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   107403016009                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2589224                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2589224                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       216083                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       187389                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          403472                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        49542                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        48727                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         98269                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       123467                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       109016                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           232483                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        10882                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         5604                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       456745                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       678540                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       512701                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        12386                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7528                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       452728                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       622261                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       441960                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3201335                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       565276                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       233935                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       799211                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        10882                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         5604                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          456745                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          802007                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       512701                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        12386                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7528                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          452728                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          731277                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       441960                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             3433818                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        10882                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         5604                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         456745                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         802007                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       512701                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        12386                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7528                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         452728                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         731277                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       441960                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            3433818                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.113100                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.123828                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.118083                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.012676                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.011369                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.012028                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.613362                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.462767                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.542745                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.154475                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.311206                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.106372                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.208364                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.470237                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.154126                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.262088                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.098691                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.161677                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.383460                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.235253                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.779663                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.455362                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.684738                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.154475                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.311206                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.106372                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.270712                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.470237                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.154126                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.262088                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.098691                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.206562                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.383460                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.256072                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.154475                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.311206                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.106372                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.270712                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.470237                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.154126                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.262088                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.098691                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.206562                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.383460                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.256072                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6654.936781                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5963.519221                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6318.189451                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11946.656051                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12720.216606                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 12309.221658                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108523.174422                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109423.120359                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 108882.991607                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 99774.836407                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 103508.314220                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 114364.793661                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 109544.591641                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 101695.652174                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 106818.550431                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 115749.104745                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116731.723075                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 124367.494122                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    96.649838                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   312.616757                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total   138.688899                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 99774.836407                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 103508.314220                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 114364.793661                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 109188.316678                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 101695.652174                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 106818.550431                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 115749.104745                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 114290.796662                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 122145.487805                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 99774.836407                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 103508.314220                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 114364.793661                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 109188.316678                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 101695.652174                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 106818.550431                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 115749.104745                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 114290.796662                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 122145.487805                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               340                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       16                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     21.250000                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1062552                       # number of writebacks
system.l2c.writebacks::total                  1062552                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          178                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           32                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          123                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           57                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          390                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            178                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             32                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            123                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             57                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                390                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           178                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            32                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           123                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            57                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               390                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        55381                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        55381                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        24439                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        23204                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        47643                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          628                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          554                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1182                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        75730                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        50449                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        126179                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1681                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1744                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        48407                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       141351                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       241091                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1909                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1973                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        44557                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       100548                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       169474                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       752735                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       440725                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       106525                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       547250                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1681                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1744                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        48407                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       217081                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       241091                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1909                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1973                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        44557                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       150997                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       169474                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           878914                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1681                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1744                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        48407                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       217081                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       241091                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1909                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1973                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        44557                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       150997                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       169474                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          878914                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16381                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        22201                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        81817                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        17694                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        20755                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38449                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        34075                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        42956                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       120266                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    494587500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    479394000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    973981500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     15163500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     13789000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     28952500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7461135548                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5015765562                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  12476901110                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    150911500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    163078500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   5057062528                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  14070826165                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  29688205910                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    175047000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    191021503                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   4714685544                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  10733108269                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  21157302360                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  86101249279                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   8759971500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2141412000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  10901383500                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    150911500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    163078500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   5057062528                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  21531961713                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  29688205910                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    175047000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    191021503                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   4714685544                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  15748873831                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  21157302360                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  98578150389                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    150911500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    163078500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   5057062528                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  21531961713                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  29688205910                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    175047000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    191021503                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   4714685544                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  15748873831                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  21157302360                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  98578150389                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3016846000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2614209002                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7665500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3345576000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8984296502                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3016846000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2614209002                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7665500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3345576000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   8984296502                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.113100                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.123828                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.118083                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.012676                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.011369                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.012028                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.613362                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.462767                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.542745                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.154475                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.311206                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.105983                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.208316                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.470237                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.154126                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.262088                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.098419                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.161585                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383460                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.235132                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.779663                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.455362                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.684738                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.154475                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.311206                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.105983                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.270672                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.470237                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.154126                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.262088                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.098419                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.206484                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383460                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.255958                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.154475                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.311206                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.105983                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.270672                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.470237                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.154126                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.262088                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.098419                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.206484                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.383460                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.255958                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20237.632473                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20659.972419                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20443.328506                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24145.700637                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24889.891697                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24494.500846                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98522.851552                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99422.497215                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 98882.548681                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104469.653728                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99545.289138                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 105812.454698                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106746.113985                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114384.543404                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19876.275455                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20102.436048                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19920.298767                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104469.653728                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99188.605696                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 105812.454698                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 104299.249859                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 112159.039894                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104469.653728                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99188.605696                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 105812.454698                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 104299.249859                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 112159.039894                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159587.876320                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150694.833566                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109809.654497                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76719.266383                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77883.788062                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 74703.544659                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests       3576184                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      2127782                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3085                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               81817                       # Transaction distribution
system.membus.trans_dist::ReadResp             843472                       # Transaction distribution
system.membus.trans_dist::WriteReq              38449                       # Transaction distribution
system.membus.trans_dist::WriteResp             38449                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1169254                       # Transaction distribution
system.membus.trans_dist::CleanEvict           223620                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           320332                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         305580                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
system.membus.trans_dist::ReadExReq            143723                       # Transaction distribution
system.membus.trans_dist::ReadExResp           125482                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        761655                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        651499                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122664                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26178                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4313500                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4462434                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238025                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       238025                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4700459                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155794                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52356                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    124357036                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    124565390                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7261504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7261504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               131826894                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           595046                       # Total snoops (count)
system.membus.snoopTraffic                     184128                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2303059                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.014256                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.118544                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 2270227     98.57%     98.57% # Request fanout histogram
system.membus.snoop_fanout::1                   32832      1.43%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2303059                       # Request fanout histogram
system.membus.reqLayer0.occupancy           101257500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21679000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8033203938                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         4846349578                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           45469982                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     10759482                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      5851735                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1766751                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         181547                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       166860                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        14687                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              81819                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4062742                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38449                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38449                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      3651776                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2342209                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          672985                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        402667                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1075652                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          103                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          103                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           288170                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          288170                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      3981632                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       828938                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       799211                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8607895                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7128520                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              15736415                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    211923339                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    174059331                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              385982670                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2818319                       # Total snoops (count)
system.toL2Bus.snoopTraffic                 121467536                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples          7671705                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.367658                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.486122                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                4865825     63.43%     63.43% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                2791193     36.38%     99.81% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  14687      0.19%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            7671705                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         8456586164                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2556167                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        3921212144                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3534160915                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
