
---------- Begin Simulation Statistics ----------
sim_seconds                                 47.296282                       # Number of seconds simulated
sim_ticks                                47296281748500                       # Number of ticks simulated
final_tick                               47296281748500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1698090                       # Simulator instruction rate (inst/s)
host_op_rate                                  1997558                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            82199406118                       # Simulator tick rate (ticks/s)
host_mem_usage                                 696116                       # Number of bytes of host memory used
host_seconds                                   575.38                       # Real time elapsed on the host
sim_insts                                   977055082                       # Number of instructions simulated
sim_ops                                    1149364510                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       154816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       128128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          4238644                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         35981768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       224128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       222976                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3009416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         39414640                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        402560                       # Number of bytes read from this memory
system.physmem.bytes_read::total             83777076                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      4238644                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3009416                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7248060                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    102370496                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total         102391080                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2419                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2002                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst            106636                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            562228                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         3502                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         3484                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             47129                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            615870                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6290                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1349560                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1599539                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1602113                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3273                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2709                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               89619                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              760774                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          4739                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          4714                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               63629                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              833356                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8511                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1771325                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          89619                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          63629                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             153248                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2164451                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                435                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2164886                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2164451                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3273                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2709                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              89619                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             761209                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         4739                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         4714                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              63629                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             833356                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8511                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3936211                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   125159                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               125159                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples       125159                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         125159    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       125159                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0       22846000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        96412     89.79%     89.79% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        10963     10.21%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       107375                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       125159                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       125159                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       107375                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       107375                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       232534                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    92471463                       # DTB read hits
system.cpu0.dtb.read_misses                     88826                       # DTB read misses
system.cpu0.dtb.write_hits                   85455153                       # DTB write hits
system.cpu0.dtb.write_misses                    36333                       # DTB write misses
system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              49425                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   36431                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4810                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    10399                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                92560289                       # DTB read accesses
system.cpu0.dtb.write_accesses               85491486                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        177926616                       # DTB hits
system.cpu0.dtb.misses                         125159                       # DTB misses
system.cpu0.dtb.accesses                    178051775                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    61082                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                61082                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples        61082                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          61082    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        61082                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples     22844500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0       22844500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total     22844500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        54995     98.82%     98.82% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          656      1.18%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        55651                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        61082                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        61082                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        55651                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        55651                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       116733                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   496679820                       # ITB inst hits
system.cpu0.itb.inst_misses                     61082                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              49425                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   25177                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               496740902                       # ITB inst accesses
system.cpu0.itb.hits                        496679820                       # DTB hits
system.cpu0.itb.misses                          61082                       # DTB misses
system.cpu0.itb.accesses                    496740902                       # DTB accesses
system.cpu0.numPwrStateTransitions              26445                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples        13222                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    3555001605.490697                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   88683028869.484894                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         3170     23.98%     23.98% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10        10025     75.82%     99.80% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            3      0.02%     99.82% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            2      0.02%     99.83% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            2      0.02%     99.85% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            2      0.02%     99.86% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            2      0.02%     99.89% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows           14      0.11%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 7351153278004                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total          13222                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   292050520702                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 47004231227798                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                     94592576721                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13223                       # number of quiesce instructions executed
system.cpu0.committedInsts                  496443686                       # Number of instructions committed
system.cpu0.committedOps                    583761680                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            535025290                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                524584                       # Number of float alu accesses
system.cpu0.num_func_calls                   28899937                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     76311856                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   535025290                       # number of integer instructions
system.cpu0.num_fp_insts                       524584                       # number of float instructions
system.cpu0.num_int_register_reads          783282318                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         424505870                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              845921                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             445948                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           133408683                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          133073326                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    178027643                       # number of memory refs
system.cpu0.num_load_insts                   92545018                       # Number of load instructions
system.cpu0.num_store_insts                  85482625                       # Number of store instructions
system.cpu0.num_idle_cycles              94008475597.936935                       # Number of idle cycles
system.cpu0.num_busy_cycles              584101123.063064                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.006175                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.993825                       # Percentage of idle cycles
system.cpu0.Branches                        111093071                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                404699186     69.29%     69.29% # Class of executed instruction
system.cpu0.op_class::IntMult                 1236587      0.21%     69.50% # Class of executed instruction
system.cpu0.op_class::IntDiv                    60193      0.01%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      8      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatCmp                     13      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatCvt                     21      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatMultAcc                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatMisc                 72938      0.01%     69.52% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::MemRead                92483705     15.83%     85.35% # Class of executed instruction
system.cpu0.op_class::MemWrite               85092334     14.57%     99.92% # Class of executed instruction
system.cpu0.op_class::FloatMemRead              61313      0.01%     99.93% # Class of executed instruction
system.cpu0.op_class::FloatMemWrite            390291      0.07%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 584096590                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements          6248914                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          501.980044                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          171607957                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          6249426                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.459795                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   501.980044                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.980430                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.980430                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          199                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        362271539                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       362271539                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     86024172                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       86024172                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     80674063                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      80674063                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       216269                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       216269                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       261006                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       261006                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2087975                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      2087975                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2051823                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      2051823                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    166959241                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       166959241                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    167175510                       # number of overall hits
system.cpu0.dcache.overall_hits::total      167175510                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3298422                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3298422                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1477781                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1477781                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       769563                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       769563                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       824193                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       824193                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       119751                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       119751                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       154814                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       154814                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      5600396                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       5600396                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      6369959                       # number of overall misses
system.cpu0.dcache.overall_misses::total      6369959                       # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data     89322594                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     89322594                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     82151844                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     82151844                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       985832                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       985832                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1085199                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1085199                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2207726                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2207726                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2206637                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2206637                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    172559637                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    172559637                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    173545469                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    173545469                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036927                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036927                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017988                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017988                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.780623                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.780623                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.759486                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.759486                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054242                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054242                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.070158                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.070158                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.032455                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.032455                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.036705                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.036705                       # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      6248914                       # number of writebacks
system.cpu0.dcache.writebacks::total          6248914                       # number of writebacks
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          5509624                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.989024                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          491225330                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5510136                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            89.149402                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       5759898000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.989024                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999979                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999979                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          200                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          248                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           63                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        998981083                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       998981083                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    491225330                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      491225330                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    491225330                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       491225330                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    491225330                       # number of overall hits
system.cpu0.icache.overall_hits::total      491225330                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5510141                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      5510141                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5510141                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       5510141                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5510141                       # number of overall misses
system.cpu0.icache.overall_misses::total      5510141                       # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst    496735471                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    496735471                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    496735471                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    496735471                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    496735471                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    496735471                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011093                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.011093                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011093                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.011093                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011093                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.011093                       # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      5509624                       # number of writebacks
system.cpu0.icache.writebacks::total          5509624                       # number of writebacks
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements         2567589                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15706.944975                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           9429067                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2583246                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            3.650085                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle       290949000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15656.940594                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    27.364617                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    22.639763                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.955624                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.001670                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001382                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.958676                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           57                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15600                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           41                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            8                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          421                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         2091                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5339                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5411                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2338                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003479                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.952148                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       401859473                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      401859473                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       287369                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       155522                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        442891                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      4441046                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      4441046                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      7316094                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      7316094                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       640560                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       640560                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5011469                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      5011469                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2961462                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2961462                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       222733                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       222733                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       287369                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       155522                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      5011469                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3602022                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        9056382                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       287369                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       155522                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      5011469                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3602022                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       9056382                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        20057                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         9858                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        29915                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       137835                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       137835                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       154814                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       154814                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       699738                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       699738                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       498672                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       498672                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1226274                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total      1226274                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       601108                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       601108                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        20057                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         9858                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       498672                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1926012                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2454599                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        20057                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         9858                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       498672                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1926012                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2454599                       # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       307426                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       165380                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       472806                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4441046                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      4441046                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      7316094                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      7316094                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       137835                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       137835                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       154814                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       154814                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1340298                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1340298                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5510141                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      5510141                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4187736                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      4187736                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       823841                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       823841                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       307426                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       165380                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5510141                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5528034                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     11510981                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       307426                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       165380                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5510141                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5528034                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     11510981                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.065242                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.059608                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.063271                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.522076                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.522076                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.090501                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.090501                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.292825                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.292825                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.729641                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.729641                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.065242                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.059608                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.090501                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.348408                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.213240                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.065242                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.059608                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.090501                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.348408                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.213240                       # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.writebacks::writebacks      1552940                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1552940                       # number of writebacks
system.cpu0.toL2Bus.snoop_filter.tot_requests     24175638                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12313629                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1398                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       303605                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       303605                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        622617                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     10320494                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        33234                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        33234                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      4441046                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      7317492                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       137835                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       154814                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       292649                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1340298                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1340298                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5510141                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4187736                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       823841                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       823841                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     16616156                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19670562                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       364916                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       727936                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         37379570                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    705437460                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    753923068                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1459664                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2911744                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1463731936                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    4670427                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic            101174852                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples     29058250                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.019576                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.138538                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          28489407     98.04%     98.04% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            568843      1.96%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      29058250                       # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                   144363                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               144363                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walkWaitTime::samples       144363                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         144363    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       144363                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples   -274399872                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     -274399872    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   -274399872                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K       111796     88.76%     88.76% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        14154     11.24%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       125950                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       144363                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       144363                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       125950                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       125950                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       270313                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    90656208                       # DTB read hits
system.cpu1.dtb.read_misses                    111973                       # DTB read misses
system.cpu1.dtb.write_hits                   81688076                       # DTB write hits
system.cpu1.dtb.write_misses                    32390                       # DTB write misses
system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              49425                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   44622                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4399                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    11479                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                90768181                       # DTB read accesses
system.cpu1.dtb.write_accesses               81720466                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        172344284                       # DTB hits
system.cpu1.dtb.misses                         144363                       # DTB misses
system.cpu1.dtb.accesses                    172488647                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    61351                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                61351                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walkWaitTime::samples        61351                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          61351    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        61351                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples   -274400872                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     -274400872    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   -274400872                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        54387     99.05%     99.05% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          524      0.95%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        54911                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        61351                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        61351                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        54911                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        54911                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       116262                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   480862179                       # ITB inst hits
system.cpu1.itb.inst_misses                     61351                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              49425                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   31395                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               480923530                       # ITB inst accesses
system.cpu1.itb.hits                        480862179                       # DTB hits
system.cpu1.itb.misses                          61351                       # DTB misses
system.cpu1.itb.accesses                    480923530                       # DTB accesses
system.cpu1.numPwrStateTransitions              12248                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         6124                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    7676898273.449706                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   188572680414.552032                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         4459     72.81%     72.81% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         1644     26.85%     99.66% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            5      0.08%     99.74% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.02%     99.76% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            1      0.02%     99.77% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            2      0.03%     99.80% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            1      0.02%     99.82% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11            1      0.02%     99.84% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           10      0.16%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 11813542452500                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           6124                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   282956721894                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 47013325026606                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                     94592569622                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    6124                       # number of quiesce instructions executed
system.cpu1.committedInsts                  480611396                       # Number of instructions committed
system.cpu1.committedOps                    565602830                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            519092247                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                374666                       # Number of float alu accesses
system.cpu1.num_func_calls                   28363152                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     73579507                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   519092247                       # number of integer instructions
system.cpu1.num_fp_insts                       374666                       # number of float instructions
system.cpu1.num_int_register_reads          766987939                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         413187755                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              609913                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             303136                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           127077975                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          126798720                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    172465256                       # number of memory refs
system.cpu1.num_load_insts                   90755131                       # Number of load instructions
system.cpu1.num_store_insts                  81710125                       # Number of store instructions
system.cpu1.num_idle_cycles              94026656141.566330                       # Number of idle cycles
system.cpu1.num_busy_cycles              565913480.433670                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.005983                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.994017                       # Percentage of idle cycles
system.cpu1.Branches                        107067845                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                392212619     69.31%     69.31% # Class of executed instruction
system.cpu1.op_class::IntMult                 1132978      0.20%     69.51% # Class of executed instruction
system.cpu1.op_class::IntDiv                    61173      0.01%     69.52% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::FloatMultAcc                  0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::FloatMisc                 36628      0.01%     69.52% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::MemRead                90705162     16.03%     85.55% # Class of executed instruction
system.cpu1.op_class::MemWrite               81422056     14.39%     99.94% # Class of executed instruction
system.cpu1.op_class::FloatMemRead              49969      0.01%     99.95% # Class of executed instruction
system.cpu1.op_class::FloatMemWrite            288069      0.05%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 565908654                       # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements          5970884                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          423.354804                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          166384448                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5971395                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            27.863581                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8470277781000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   423.354804                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.826865                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.826865                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          180                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          330                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        350957211                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       350957211                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data     84198598                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       84198598                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     77531561                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      77531561                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       187263                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       187263                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data        64886                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total        64886                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      2055500                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      2055500                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2044725                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      2044725                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    161795045                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       161795045                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    161982308                       # number of overall hits
system.cpu1.dcache.overall_hits::total      161982308                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3367290                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3367290                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1466124                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1466124                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       793623                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       793623                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       433871                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       433871                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       147105                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       147105                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       156674                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       156674                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      5267285                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       5267285                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      6060908                       # number of overall misses
system.cpu1.dcache.overall_misses::total      6060908                       # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data     87565888                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     87565888                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     78997685                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     78997685                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       980886                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       980886                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       498757                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       498757                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2202605                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      2202605                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2201399                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      2201399                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    167062330                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    167062330                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    168043216                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    168043216                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038454                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.038454                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018559                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018559                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.809088                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.809088                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.869905                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.869905                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.066787                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.066787                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.071170                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.071170                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031529                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.031529                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.036068                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.036068                       # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks      5970884                       # number of writebacks
system.cpu1.dcache.writebacks::total          5970884                       # number of writebacks
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements          4768482                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.452247                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          476148096                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          4768994                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            99.842461                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8470205818500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.452247                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969633                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969633                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          308                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          146                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        966603174                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       966603174                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst    476148096                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      476148096                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    476148096                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       476148096                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    476148096                       # number of overall hits
system.cpu1.icache.overall_hits::total      476148096                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      4768994                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      4768994                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      4768994                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       4768994                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      4768994                       # number of overall misses
system.cpu1.icache.overall_misses::total      4768994                       # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst    480917090                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    480917090                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    480917090                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    480917090                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    480917090                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    480917090                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.009916                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.009916                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.009916                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.009916                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.009916                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.009916                       # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks      4768482                       # number of writebacks
system.cpu1.icache.writebacks::total          4768482                       # number of writebacks
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements         2174770                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13105.960937                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           8815603                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2190453                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            4.024557                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 13068.855777                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    21.863128                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    15.242032                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.797660                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001334                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000930                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.799924                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           90                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15593                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           57                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           12                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          246                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         2414                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         7618                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         3564                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1751                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005493                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.951721                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       369059783                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      369059783                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       338101                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       153667                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        491768                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      4061526                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      4061526                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      6677473                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      6677473                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       614785                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       614785                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4308825                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4308825                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3093892                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      3093892                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       164960                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       164960                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       338101                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       153667                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4308825                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3708677                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8509270                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       338101                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       153667                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4308825                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3708677                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8509270                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        22355                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        10972                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        33327                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       145242                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       145242                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       156674                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       156674                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       706301                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       706301                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       460169                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       460169                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1214126                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total      1214126                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       268707                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       268707                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        22355                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker        10972                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       460169                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1920427                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      2413923                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        22355                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker        10972                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       460169                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1920427                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      2413923                       # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       360456                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       164639                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       525095                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      4061526                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      4061526                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      6677473                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      6677473                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       145242                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       145242                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       156674                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       156674                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1321086                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1321086                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4768994                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      4768994                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4308018                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      4308018                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       433667                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       433667                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       360456                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       164639                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      4768994                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      5629104                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10923193                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       360456                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       164639                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      4768994                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      5629104                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10923193                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.062019                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.066643                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.063469                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.534637                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.534637                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.096492                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.096492                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.281829                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.281829                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.619616                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.619616                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.062019                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.066643                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.096492                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.341160                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.220991                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.062019                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.066643                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.096492                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.341160                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.220991                       # miss rate for overall accesses
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.writebacks::writebacks      1197912                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1197912                       # number of writebacks
system.cpu1.toL2Bus.snoop_filter.tot_requests     22146544                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11314780                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          367                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       285761                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       285759                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            2                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq        607661                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9684673                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         5564                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         5564                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4061526                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      6677840                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       145242                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       156674                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       301916                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1321086                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1321086                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4768994                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4308018                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       433667                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       433667                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14306730                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18723008                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       366766                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       836674                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         34233178                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    610398984                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    742432559                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1467064                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3346696                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1357645303                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    4277162                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic             79243712                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples     26604267                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.021049                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.143548                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          26044274     97.90%     97.90% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            559991      2.10%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 2      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      26604267                       # Request fanout histogram
system.iobus.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40301                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40301                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136636                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136636                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47642                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122576                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231218                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231218                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353874                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47662                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155683                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496657                       # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115590                       # number of replacements
system.iocache.tags.tagsinuse               11.298808                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115606                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9107772860509                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.845510                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.453298                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.240344                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.465831                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706176                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040838                       # Number of tag accesses
system.iocache.tags.data_accesses             1040838                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8881                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8918                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115609                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115649                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115609                       # number of overall misses
system.iocache.overall_misses::total           115649                       # number of overall misses
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8881                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8918                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115609                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115649                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115609                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115649                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106694                       # number of writebacks
system.iocache.writebacks::total               106694                       # number of writebacks
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1924793                       # number of replacements
system.l2c.tags.tagsinuse                65250.197909                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5713780                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1986359                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.876509                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                477350500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   10662.392220                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    41.728586                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker    44.787257                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3175.849688                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    15990.343630                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   362.595804                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   421.087250                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2804.760651                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    31746.652822                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.162695                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000637                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000683                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.048460                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.243993                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.005533                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.006425                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.042797                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.484415                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995639                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          224                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        61342                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          223                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          260                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3566                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4579                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        52911                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.003418                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.936005                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 71904156                       # Number of tag accesses
system.l2c.tags.data_accesses                71904156                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks      2750852                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2750852                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           60132                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           51539                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              111671                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          8500                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          7695                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             16195                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           199510                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           176557                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               376067                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        12368                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5246                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       435137                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       707607                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        12105                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4097                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       413141                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       664483                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2254184                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       130356                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       113567                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           243923                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker         12368                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          5246                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              435137                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              907117                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         12105                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4097                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              413141                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              841040                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2630251                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        12368                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         5246                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             435137                       # number of overall hits
system.l2c.overall_hits::cpu0.data             907117                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        12105                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4097                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             413141                       # number of overall hits
system.l2c.overall_hits::cpu1.data             841040                       # number of overall hits
system.l2c.overall_hits::total                2630251                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         21889                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         25427                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             47316                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          415                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          794                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1209                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         372583                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         420111                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             792694                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2419                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2002                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        63535                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       191729                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         3502                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         3484                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        47028                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       197713                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         511412                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       462716                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       149158                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         611874                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2419                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2002                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             63535                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            564312                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         3502                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         3484                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             47028                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            617824                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1304106                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2419                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2002                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            63535                       # number of overall misses
system.l2c.overall_misses::cpu0.data           564312                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         3502                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         3484                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            47028                       # number of overall misses
system.l2c.overall_misses::cpu1.data           617824                       # number of overall misses
system.l2c.overall_misses::total              1304106                       # number of overall misses
system.l2c.WritebackDirty_accesses::writebacks      2750852                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2750852                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        82021                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        76966                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          158987                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         8915                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         8489                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         17404                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       572093                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       596668                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          1168761                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        14787                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7248                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       498672                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       899336                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        15607                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7581                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       460169                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       862196                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      2765596                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       593072                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       262725                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       855797                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        14787                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7248                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          498672                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1471429                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        15607                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7581                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          460169                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1458864                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             3934357                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        14787                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7248                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         498672                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1471429                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        15607                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7581                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         460169                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1458864                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            3934357                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.266871                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.330367                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.297609                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.046551                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.093533                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.069467                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.651263                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.704095                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.678234                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.163590                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.276214                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.127408                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.213190                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.224386                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.459570                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.102197                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.229313                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.184919                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.780202                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.567734                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.714976                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.163590                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.276214                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.127408                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.383513                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.224386                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.459570                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.102197                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.423497                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.331466                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.163590                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.276214                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.127408                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.383513                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.224386                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.459570                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.102197                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.423497                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.331466                       # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1492845                       # number of writebacks
system.l2c.writebacks::total                  1492845                       # number of writebacks
system.membus.snoop_filter.tot_requests       4436915                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      2508187                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3478                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               82130                       # Transaction distribution
system.membus.trans_dist::ReadResp             602460                       # Transaction distribution
system.membus.trans_dist::WriteReq              38798                       # Transaction distribution
system.membus.trans_dist::WriteResp             38798                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1599539                       # Transaction distribution
system.membus.trans_dist::CleanEvict           267122                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           245150                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         295293                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           53835                       # Transaction distribution
system.membus.trans_dist::ReadExReq            792754                       # Transaction distribution
system.membus.trans_dist::ReadExResp           789263                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        520330                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        716726                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       716726                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122576                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27542                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6261826                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      6412036                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346888                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       346888                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                6758924                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155683                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        55084                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    178979036                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    179190007                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7399168                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7399168                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               186589175                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           4557842                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.007340                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.085359                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 4524387     99.27%     99.27% # Request fanout histogram
system.membus.snoop_fanout::1                   33455      0.73%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4557842                       # Request fanout histogram
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     11075061                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      5706480                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1648775                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         269190                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       248390                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        20800                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              82132                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           3544615                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38798                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38798                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      2750852                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1991304                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          351511                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        311488                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         662999                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1351623                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1351623                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      3462483                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       855797                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       855797                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9483041                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8166779                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17649820                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    254997904                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    229564151                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              484562055                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1959256                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  95582592                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples         13153559                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.293824                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.458971                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                9309527     70.78%     70.78% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                3823232     29.07%     99.84% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  20800      0.16%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           13153559                       # Request fanout histogram

---------- End Simulation Statistics   ----------
