
---------- Begin Simulation Statistics ----------
sim_seconds                                  2.854886                       # Number of seconds simulated
sim_ticks                                2854886132500                       # Number of ticks simulated
final_tick                               2854886132500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 259825                       # Simulator instruction rate (inst/s)
host_op_rate                                   314145                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6635713455                       # Simulator tick rate (ticks/s)
host_mem_usage                                 588360                       # Number of bytes of host memory used
host_seconds                                   430.23                       # Real time elapsed on the host
sim_insts                                   111784531                       # Number of instructions simulated
sim_ops                                     135154718                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker         7232                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1667840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9176172                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10852268                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1667840                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1667840                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7959296                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7976820                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker          113                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26060                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             143899                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                170088                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          124364                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               128745                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           2533                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               584205                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3214199                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              336                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3801296                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          584205                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             584205                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2787956                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6138                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2794094                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2787956                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2533                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              584205                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3220337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             336                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6595390                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        170088                       # Number of read requests accepted
system.physmem.writeReqs                       128745                       # Number of write requests accepted
system.physmem.readBursts                      170088                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     128745                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10876160                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9472                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7989120                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10852268                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7976820                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      148                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10602                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10348                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10682                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10189                       # Per bank write bursts
system.physmem.perBankRdBursts::4               13369                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10294                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10368                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10838                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10130                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10489                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10055                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9592                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10755                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11804                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10513                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9912                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7846                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7741                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8334                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7790                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7606                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7522                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7517                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7997                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7756                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7896                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7435                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7391                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8149                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8812                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7798                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7240                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          69                       # Number of times write queue was full causing retry
system.physmem.totGap                    2854885682000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  169531                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 124364                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    160094                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      9538                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       296                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1848                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2664                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5925                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6598                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6259                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6588                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6880                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7703                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7446                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8538                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7391                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7010                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7044                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6699                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6588                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6615                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      445                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      300                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      326                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      257                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      277                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      297                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      214                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      243                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      242                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      159                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        60347                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      312.612325                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     185.506399                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     329.136235                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          21716     35.99%     35.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14599     24.19%     60.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6802     11.27%     71.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3528      5.85%     77.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2551      4.23%     81.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1581      2.62%     84.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1111      1.84%     85.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1010      1.67%     87.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7449     12.34%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          60347                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6172                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.532242                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      583.546907                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6171     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6172                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6172                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.225211                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.326492                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       15.268498                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5463     88.51%     88.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              63      1.02%     89.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              33      0.53%     90.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              41      0.66%     90.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             274      4.44%     95.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              26      0.42%     95.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              14      0.23%     95.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               8      0.13%     95.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              10      0.16%     96.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               4      0.06%     96.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               5      0.08%     96.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               7      0.11%     96.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             140      2.27%     98.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.08%     98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               6      0.10%     98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               3      0.05%     98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.03%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.05%     99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.02%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            11      0.18%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.05%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            14      0.23%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             6      0.10%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             4      0.06%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             6      0.10%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             2      0.03%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.02%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             2      0.03%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.02%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             3      0.05%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6172                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4562123250                       # Total ticks spent queuing
system.physmem.totMemAccLat                7748498250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    849700000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       26845.49                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  45595.49                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.80                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.79                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.21                       # Average write queue length when enqueuing
system.physmem.readRowHits                     140395                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     94027                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.61                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.31                       # Row buffer hit rate for writes
system.physmem.avgGap                      9553448.52                       # Average gap between requests
system.physmem.pageHitRate                      79.52                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  217784280                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  115755090                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 618966600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                325482660                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           6028389120.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             4546972650                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              380659200                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       12537712590                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        8446773120                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       671876398965                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             705097688865                       # Total energy per rank (pJ)
system.physmem_0.averagePower              246.979269                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           2843583812750                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      720868250                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2563490000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   2794425375000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  21996678750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      7684667500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  27495053000                       # Time in different power states
system.physmem_1.actEnergy                  213100440                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  113261775                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 594405000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                326129940                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           6103375200.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             4480349340                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              365416320                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       12364122510                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        8637319200                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       671971041390                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             705171178185                       # Total energy per rank (pJ)
system.physmem_1.averagePower              247.005010                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           2844103138750                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      682770250                       # Time in different power states
system.physmem_1.memoryStateTime::REF      2596086000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   2794495958000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN  22493040000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      7504072000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  27114206250                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst           179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              179                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          179                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst          179                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             179                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                31050902                       # Number of BP lookups
system.cpu.branchPred.condPredicted          16823011                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           2467385                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18598277                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                10398347                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             55.910271                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 7909634                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1502216                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         3035557                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            2846976                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses           188581                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       109207                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                     67916                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                67916                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1        44853                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23063                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples        67916                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0           67916    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total        67916                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7871                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 10132.638801                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean  8470.700593                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  9365.136659                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535         7864     99.91%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071            6      0.08%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7871                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    276581000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       276581000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    276581000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6482     82.35%     82.35% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1389     17.65%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7871                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        67916                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total        67916                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7871                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7871                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        75787                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24685993                       # DTB read hits
system.cpu.dtb.read_misses                      61030                       # DTB read misses
system.cpu.dtb.write_hits                    19409907                       # DTB write hits
system.cpu.dtb.write_misses                      6886                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4276                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1444                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1826                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       755                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24747023                       # DTB read accesses
system.cpu.dtb.write_accesses                19416793                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44095900                       # DTB hits
system.cpu.dtb.misses                           67916                       # DTB misses
system.cpu.dtb.accesses                      44163816                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                      5836                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 5836                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          323                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         5513                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         5836                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            5836    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         5836                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3199                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 10502.500781                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean  8663.235820                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  6980.719897                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191         1845     57.67%     57.67% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383          784     24.51%     82.18% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575          564     17.63%     99.81% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::24576-32767            5      0.16%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::90112-98303            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3199                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    276141500                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       276141500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    276141500                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2889     90.31%     90.31% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           310      9.69%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3199                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5836                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         5836                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3199                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3199                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         9035                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                     57468050                       # ITB inst hits
system.cpu.itb.inst_misses                       5836                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2922                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                      8340                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 57473886                       # ITB inst accesses
system.cpu.itb.hits                          57468050                       # DTB hits
system.cpu.itb.misses                            5836                       # DTB misses
system.cpu.itb.accesses                      57473886                       # DTB accesses
system.cpu.numPwrStateTransitions                6066                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples          3033                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     887944293.276624                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    17437791477.805088                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows         2968     97.86%     97.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10           59      1.95%     99.80% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.03%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.03%     99.90% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 499966835544                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total            3033                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    161751090992                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 2693135041508                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        323505132                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   111784531                       # Number of instructions committed
system.cpu.committedOps                     135154718                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       7776689                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      3033                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                   5386331427                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.894006                       # CPI: cycles per instruction
system.cpu.ipc                               0.345542                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                2337      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu                90595549     67.03%     67.03% # Class of committed instruction
system.cpu.op_class_0::IntMult                 113150      0.08%     67.12% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatMisc                    0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc             8471      0.01%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.12% # Class of committed instruction
system.cpu.op_class_0::MemRead               24195627     17.90%     85.02% # Class of committed instruction
system.cpu.op_class_0::MemWrite              20228352     14.97%     99.99% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead              2708      0.00%     99.99% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite             8524      0.01%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                135154718                       # Class of committed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
system.cpu.tickCycles                       217865051                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       105640081                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements            843791                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.945118                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42554576                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            844303                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             50.402019                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         330588500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.945118                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999893                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999893                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          364                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           61                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         175868835                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        175868835                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     23043762                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23043762                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18247268                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18247268                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       357174                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        357174                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443432                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443432                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460038                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460038                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41291030                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41291030                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     41648204                       # number of overall hits
system.cpu.dcache.overall_hits::total        41648204                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       465012                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        465012                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       548381                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       548381                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       168658                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       168658                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22398                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22398                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      1013393                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1013393                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1182051                       # number of overall misses
system.cpu.dcache.overall_misses::total       1182051                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   7327923000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   7327923000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  26756956980                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  26756956980                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    306920500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    306920500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       171000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       171000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  34084879980                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  34084879980                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  34084879980                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  34084879980                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23508774                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23508774                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     18795649                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18795649                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       525832                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       525832                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465830                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       465830                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460040                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460040                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42304423                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42304423                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42830255                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42830255                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.019780                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.019780                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029176                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.029176                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.320745                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.320745                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048082                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048082                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.023955                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.023955                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.027599                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.027599                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15758.567521                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15758.567521                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48792.640482                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48792.640482                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13703.031521                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13703.031521                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        85500                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        85500                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33634.414270                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 33634.414270                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28835.371723                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28835.371723                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          201                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                21                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.571429                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       701301                       # number of writebacks
system.cpu.dcache.writebacks::total            701301                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        45802                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        45802                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249489                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       249489                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14157                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        14157                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       295291                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       295291                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       295291                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       295291                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       419210                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       419210                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298892                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298892                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       120813                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       120813                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8241                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8241                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       718102                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       718102                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       838915                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       838915                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31130                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6438741500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6438741500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14235579000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  14235579000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1652909500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1652909500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    122323000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    122323000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       169000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       169000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  20674320500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  20674320500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22327230000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  22327230000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6305432000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6305432000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6305432000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6305432000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017832                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017832                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015902                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015902                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.229756                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.229756                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017691                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017691                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016975                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016975                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019587                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.019587                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15359.226879                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15359.226879                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47627.835472                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47627.835472                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13681.553310                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13681.553310                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14843.222910                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14843.222910                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        84500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        84500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28790.228268                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28790.228268                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26614.412664                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26614.412664                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202551.622229                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202551.622229                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107392.308478                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107392.308478                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements           2889413                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.370681                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            54569461                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           2889925                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             18.882656                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       16116553500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.370681                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998771                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998771                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          60349332                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         60349332                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     54569461                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        54569461                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      54569461                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         54569461                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     54569461                       # number of overall hits
system.cpu.icache.overall_hits::total        54569461                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      2889936                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       2889936                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      2889936                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        2889936                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      2889936                       # number of overall misses
system.cpu.icache.overall_misses::total       2889936                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  39799359500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  39799359500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  39799359500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  39799359500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  39799359500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  39799359500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     57459397                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     57459397                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     57459397                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     57459397                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     57459397                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     57459397                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050295                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.050295                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.050295                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.050295                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.050295                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.050295                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13771.709650                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13771.709650                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13771.709650                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13771.709650                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13771.709650                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13771.709650                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks      2889413                       # number of writebacks
system.cpu.icache.writebacks::total           2889413                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2889936                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      2889936                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      2889936                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      2889936                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      2889936                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      2889936                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3119                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         3119                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3119                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         3119                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36909424500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  36909424500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36909424500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  36909424500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36909424500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  36909424500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    265216500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    265216500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    265216500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    265216500                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050295                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050295                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050295                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.050295                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050295                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.050295                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12771.709996                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12771.709996                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12771.709996                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12771.709996                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12771.709996                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12771.709996                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements            96873                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65145.709178                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            7314750                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           162275                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            45.076259                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      99924187000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    73.512854                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.023684                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 12110.922280                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 52961.250360                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001122                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.184798                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.808125                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.994045                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023           58                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65344                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4           57                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4564                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        60694                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000885                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         60034528                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        60034528                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        67803                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3361                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          71164                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks       701301                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       701301                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      2838672                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      2838672                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         2815                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         2815                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       166503                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       166503                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2866935                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      2866935                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       533944                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       533944                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        67803                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         3361                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      2866935                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       700447                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3638546                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        67803                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         3361                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      2866935                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       700447                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3638546                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          113                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          114                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       129573                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       129573                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22965                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        22965                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14315                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        14315                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker          113                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        22965                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       143888                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        166967                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker          113                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            1                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        22965                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       143888                       # number of overall misses
system.cpu.l2cache.overall_misses::total       166967                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     38662500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker        89500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     38752000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       174000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       174000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       166000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       166000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12000990500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  12000990500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2404531500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2404531500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1744805500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1744805500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     38662500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker        89500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2404531500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  13745796000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  16189079500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     38662500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker        89500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2404531500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  13745796000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  16189079500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        67916                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3362                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        71278                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks       701301                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       701301                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      2838672                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      2838672                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2821                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2821                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       296076                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       296076                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      2889900                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      2889900                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       548259                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       548259                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        67916                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         3362                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      2889900                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       844335                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      3805513                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        67916                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         3362                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      2889900                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       844335                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      3805513                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001664                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000297                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.001599                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.002127                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.002127                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.437634                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.437634                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007947                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007947                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026110                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026110                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001664                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000297                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007947                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.170416                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.043875                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001664                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000297                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007947                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.170416                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.043875                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 342146.017699                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        89500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 339929.824561                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        29000                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        29000                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        83000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        83000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92619.531075                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92619.531075                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 104704.180274                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 104704.180274                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121886.517639                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121886.517639                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 342146.017699                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        89500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 104704.180274                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95531.218726                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 96959.755521                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 342146.017699                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        89500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 104704.180274                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95531.218726                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 96959.755521                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        88174                       # number of writebacks
system.cpu.l2cache.writebacks::total            88174                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          144                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          144                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data          144                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          157                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data          144                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          157                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          113                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          114                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       129573                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       129573                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22952                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22952                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14171                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14171                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          113                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        22952                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       143744                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       166810                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          113                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        22952                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143744                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       166810                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3119                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34249                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3119                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61833                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     37532500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        79500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     37612000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       114000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       114000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       146000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       146000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  10705260500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  10705260500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2173786500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2173786500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1590255500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1590255500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     37532500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        79500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2173786500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12295516000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  14506914500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     37532500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        79500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2173786500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12295516000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  14506914500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    216819500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5916233500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6133053000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    216819500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5916233500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6133053000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001664                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000297                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001599                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.002127                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.002127                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.437634                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.437634                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007942                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007942                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025847                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025847                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001664                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000297                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007942                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.170245                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.043834                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001664                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000297                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007942                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.170245                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.043834                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        79500                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 329929.824561                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        19000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        19000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        73000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        73000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82619.531075                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82619.531075                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 94710.112409                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 94710.112409                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 112219.003599                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112219.003599                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        79500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94710.112409                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85537.594613                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86966.695642                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        79500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94710.112409                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85537.594613                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86966.695642                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190049.261163                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179072.469269                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100763.591307                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99187.375673                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests      7501348                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      3767098                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58079                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          189                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          189                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq         136577                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3574918                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       789475                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      2889413                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       151189                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2821                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2823                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       296076                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       296076                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      2889936                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       548482                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq         4413                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp           16                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8675486                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2655698                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14711                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       158895                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          11504790                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    370075584                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     99113193                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        13448                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       271664                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          469473889                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      132758                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               5779048                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      4002764                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.022319                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.147720                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3913425     97.77%     97.77% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              89339      2.23%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4002764                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     7421735500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       289875                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    4340119421                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1313068534                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      11352493                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      91007942                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             46393500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               333000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                30000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                14000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                91000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               613000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               21500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               52000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6090000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            39095500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187683346                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.033754                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         272028370000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.033754                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.064610                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.064610                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36458                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36458                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36458                       # number of overall misses
system.iocache.overall_misses::total            36458                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     29456377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     29456377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4371874969                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4371874969                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4401331346                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4401331346                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4401331346                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4401331346                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36458                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36458                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36458                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36458                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 125881.952991                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125881.952991                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120690.011291                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120690.011291                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 120723.334961                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 120723.334961                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 120723.334961                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 120723.334961                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36458                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36458                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36458                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36458                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17756377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17756377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2558822831                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2558822831                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2576579208                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2576579208                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2576579208                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2576579208                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75881.952991                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75881.952991                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70638.881156                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70638.881156                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70672.532997                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70672.532997                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70672.532997                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70672.532997                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests        336642                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       137901                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          539                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               34249                       # Transaction distribution
system.membus.trans_dist::ReadResp              71720                       # Transaction distribution
system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       124364                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8933                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              128                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129451                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129451                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         37471                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp         4363                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2074                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446194                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       553762                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 626659                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16511968                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16675753                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                18992873                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             4867                       # Total snoops (count)
system.membus.snoopTraffic                      32128                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            265109                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.018562                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.134973                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  260188     98.14%     98.14% # Request fanout histogram
system.membus.snoop_fanout::1                    4921      1.86%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              265109                       # Request fanout histogram
system.membus.reqLayer0.occupancy            92913500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                8000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1698000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           904283412                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          988660500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            5813415                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------
