
---------- Begin Simulation Statistics ----------
sim_seconds                                 47.356210                       # Number of seconds simulated
sim_ticks                                47356210126000                       # Number of ticks simulated
final_tick                               47356210126000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 269105                       # Simulator instruction rate (inst/s)
host_op_rate                                   316551                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            14489745940                       # Simulator tick rate (ticks/s)
host_mem_usage                                 771556                       # Number of bytes of host memory used
host_seconds                                  3268.26                       # Real time elapsed on the host
sim_insts                                   879504495                       # Number of instructions simulated
sim_ops                                    1034569807                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       139968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       127936                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          7960960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         14481160                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     15033920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       105216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        97088                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3386304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          9267600                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     11152448                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        451392                       # Number of bytes read from this memory
system.physmem.bytes_read::total             62203992                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      7960960                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3386304                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        11347264                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     74964928                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          74985512                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2187                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1999                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst            124390                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            226281                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       234905                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1644                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1517                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             52911                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            144819                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       174257                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           7053                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                971963                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1171327                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1173901                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2956                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2702                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              168108                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              305792                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       317465                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2222                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2050                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               71507                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              195700                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       235501                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9532                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1313534                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         168108                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          71507                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             239615                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1583001                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                435                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1583436                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1583001                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2956                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2702                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             168108                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             306227                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       317465                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2222                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2050                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              71507                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             195700                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       235501                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9532                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2896970                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        971963                       # Number of read requests accepted
system.physmem.writeReqs                      1173901                       # Number of write requests accepted
system.physmem.readBursts                      971963                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1173901                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 62180096                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     25536                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  74984000                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  62203992                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               74985512                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      399                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               55033                       # Per bank write bursts
system.physmem.perBankRdBursts::1               62597                       # Per bank write bursts
system.physmem.perBankRdBursts::2               50092                       # Per bank write bursts
system.physmem.perBankRdBursts::3               57292                       # Per bank write bursts
system.physmem.perBankRdBursts::4               55886                       # Per bank write bursts
system.physmem.perBankRdBursts::5               65305                       # Per bank write bursts
system.physmem.perBankRdBursts::6               62171                       # Per bank write bursts
system.physmem.perBankRdBursts::7               60911                       # Per bank write bursts
system.physmem.perBankRdBursts::8               55564                       # Per bank write bursts
system.physmem.perBankRdBursts::9              110087                       # Per bank write bursts
system.physmem.perBankRdBursts::10              50665                       # Per bank write bursts
system.physmem.perBankRdBursts::11              58731                       # Per bank write bursts
system.physmem.perBankRdBursts::12              55379                       # Per bank write bursts
system.physmem.perBankRdBursts::13              59204                       # Per bank write bursts
system.physmem.perBankRdBursts::14              58833                       # Per bank write bursts
system.physmem.perBankRdBursts::15              53814                       # Per bank write bursts
system.physmem.perBankWrBursts::0               70729                       # Per bank write bursts
system.physmem.perBankWrBursts::1               73923                       # Per bank write bursts
system.physmem.perBankWrBursts::2               67641                       # Per bank write bursts
system.physmem.perBankWrBursts::3               73309                       # Per bank write bursts
system.physmem.perBankWrBursts::4               73460                       # Per bank write bursts
system.physmem.perBankWrBursts::5               77994                       # Per bank write bursts
system.physmem.perBankWrBursts::6               75119                       # Per bank write bursts
system.physmem.perBankWrBursts::7               77047                       # Per bank write bursts
system.physmem.perBankWrBursts::8               72172                       # Per bank write bursts
system.physmem.perBankWrBursts::9               76177                       # Per bank write bursts
system.physmem.perBankWrBursts::10              69310                       # Per bank write bursts
system.physmem.perBankWrBursts::11              74055                       # Per bank write bursts
system.physmem.perBankWrBursts::12              71196                       # Per bank write bursts
system.physmem.perBankWrBursts::13              73730                       # Per bank write bursts
system.physmem.perBankWrBursts::14              72781                       # Per bank write bursts
system.physmem.perBankWrBursts::15              72982                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         338                       # Number of times write queue was full causing retry
system.physmem.totGap                    47356208030500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  971933                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1171327                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    599542                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    159109                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     46981                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     36741                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     28369                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     25953                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     23819                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     21360                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     18806                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      4598                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1833                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1239                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      994                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      697                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      408                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      339                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      286                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      244                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      126                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       93                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    24305                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    32346                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    48833                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    56114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    61688                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    64343                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    66279                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    68229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    71242                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    71432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    74216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    76183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    73010                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    71262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    72325                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    75575                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    67464                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    63552                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     4902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     3071                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1943                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1445                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      965                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      888                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      894                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      765                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      736                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      628                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      732                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      601                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      589                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      546                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      578                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      623                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      597                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      584                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      815                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      810                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      531                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      839                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      764                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      423                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      769                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       927860                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      147.827612                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      99.770435                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     195.442358                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         609464     65.68%     65.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       190800     20.56%     86.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        46263      4.99%     91.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        21195      2.28%     93.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        15500      1.67%     95.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         9774      1.05%     96.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7067      0.76%     97.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5586      0.60%     97.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        22211      2.39%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         927860                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         57099                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        17.014939                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      164.898277                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          57097    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::29696-30719            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           57099                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         57099                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.519186                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.696547                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       14.054604                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           49168     86.11%     86.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            2307      4.04%     90.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             623      1.09%     91.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             607      1.06%     92.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             970      1.70%     94.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             377      0.66%     94.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             342      0.60%     95.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47             248      0.43%     95.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             171      0.30%     96.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             147      0.26%     96.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59             125      0.22%     96.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63             141      0.25%     96.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             491      0.86%     97.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71             181      0.32%     97.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75             140      0.25%     98.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             149      0.26%     98.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             103      0.18%     98.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              79      0.14%     98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91              87      0.15%     98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95              90      0.16%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99              76      0.13%     99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103            61      0.11%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107            62      0.11%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            70      0.12%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115            41      0.07%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119            40      0.07%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123            42      0.07%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127            34      0.06%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            42      0.07%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135            20      0.04%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139            12      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143            13      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             6      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             4      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             4      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             5      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             6      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           57099                       # Writes before turning the bus around for reads
system.physmem.totQLat                    49354955217                       # Total ticks spent queuing
system.physmem.totMemAccLat               67571780217                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4857820000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       50799.49                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  69549.49                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.31                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.58                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.31                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.58                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.16                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.53                       # Average write queue length when enqueuing
system.physmem.readRowHits                     725116                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    490210                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.63                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  41.84                       # Row buffer hit rate for writes
system.physmem.avgGap                     22068597.09                       # Average gap between requests
system.physmem.pageHitRate                      56.71                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 3347988840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1779490680                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3350709180                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3075738840                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           40224500160.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            43885079760                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             2109996960                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       79595636190                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy       56472597600                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       11270458828185                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             11504320668105                       # Total energy per rank (pJ)
system.physmem_0.averagePower              242.931616                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           47254429054365                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE     3740889550                       # Time in different power states
system.physmem_0.memoryStateTime::REF     17088544000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   46932815651000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 147063936092                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     80948731835                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 174552373523                       # Time in different power states
system.physmem_1.actEnergy                 3276952980                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1741738020                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3586257780                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3040143660                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           38004420480.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            43585213590                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             1995622560                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       72860280210                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy       53203975680                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       11275978868760                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             11497290812280                       # Total energy per rank (pJ)
system.physmem_1.averagePower              242.783170                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           47255392508641                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE     3486165610                       # Time in different power states
system.physmem_1.memoryStateTime::REF     16146094000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   46957059679500                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 138551420004                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     81185307499                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 159781459387                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          640                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          1388                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          640                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         1344                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           10                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             27                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           15                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               29                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           15                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           28                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           15                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              29                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              135721275                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         95221356                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          6297780                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups           101561419                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               70514394                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            69.430296                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               16061922                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect           1062204                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        3676908                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           2416966                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses         1259942                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted       447333                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   280305                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               280305                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         9673                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        80745                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples       280305                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         280305    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       280305                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples        90418                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 24557.682099                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 22462.475848                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 18823.909973                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535        89075     98.51%     98.51% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         1011      1.12%     99.63% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          175      0.19%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           66      0.07%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           41      0.05%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           17      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            5      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            6      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            1      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359           21      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total        90418                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1049600704                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     1049600704    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1049600704                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        80745     89.30%     89.30% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M         9673     10.70%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        90418                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       280305                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       280305                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        90418                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        90418                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       370723                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    85620412                       # DTB read hits
system.cpu0.dtb.read_misses                    232360                       # DTB read misses
system.cpu0.dtb.write_hits                   76323418                       # DTB write hits
system.cpu0.dtb.write_misses                    47945                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              40720                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   37568                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     2099                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                 10030                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    11718                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                85852772                       # DTB read accesses
system.cpu0.dtb.write_accesses               76371363                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        161943830                       # DTB hits
system.cpu0.dtb.misses                         280305                       # DTB misses
system.cpu0.dtb.accesses                    162224135                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    68220                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                68220                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2          613                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        59689                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        68220                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          68220    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        68220                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        60302                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 26595.826009                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24233.258451                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 21809.844701                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        58891     97.66%     97.66% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071         1009      1.67%     99.33% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          274      0.45%     99.79% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           71      0.12%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           14      0.02%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           15      0.02%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            3      0.00%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            1      0.00%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359           21      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::655360-720895            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        60302                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1048830204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1048830204    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1048830204                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        59689     98.98%     98.98% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          613      1.02%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        60302                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        68220                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        68220                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        60302                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        60302                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       128522                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   240780512                       # ITB inst hits
system.cpu0.itb.inst_misses                     68220                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              40720                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   26473                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   160298                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               240848732                       # ITB inst accesses
system.cpu0.itb.hits                        240780512                       # DTB hits
system.cpu0.itb.misses                          68220                       # DTB misses
system.cpu0.itb.accesses                    240848732                       # DTB accesses
system.cpu0.numPwrStateTransitions              27604                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples        13802                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    3395512179.708375                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   87569621243.897629                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         3847     27.87%     27.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         9929     71.94%     99.81% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            3      0.02%     99.83% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.86% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows           14      0.10%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 7470353787292                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total          13802                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   491351021665                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46864859104335                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       982743358                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  443442317                       # Number of instructions committed
system.cpu0.committedOps                    521139520                       # Number of ops (including micro ops) committed
system.cpu0.discardedOps                     46171758                       # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends                     4942                       # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles                 93730487058                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi                              2.216170                       # CPI: cycles per instruction
system.cpu0.ipc                              0.451229                       # IPC: instructions per cycle
system.cpu0.op_class_0::No_OpClass                  0      0.00%      0.00% # Class of committed instruction
system.cpu0.op_class_0::IntAlu              361587453     69.38%     69.38% # Class of committed instruction
system.cpu0.op_class_0::IntMult               1073144      0.21%     69.59% # Class of committed instruction
system.cpu0.op_class_0::IntDiv                  57197      0.01%     69.60% # Class of committed instruction
system.cpu0.op_class_0::FloatAdd                    8      0.00%     69.60% # Class of committed instruction
system.cpu0.op_class_0::FloatCmp                   13      0.00%     69.60% # Class of committed instruction
system.cpu0.op_class_0::FloatCvt                   21      0.00%     69.60% # Class of committed instruction
system.cpu0.op_class_0::FloatMult                   0      0.00%     69.60% # Class of committed instruction
system.cpu0.op_class_0::FloatMultAcc                0      0.00%     69.60% # Class of committed instruction
system.cpu0.op_class_0::FloatDiv                    0      0.00%     69.60% # Class of committed instruction
system.cpu0.op_class_0::FloatMisc               48874      0.01%     69.61% # Class of committed instruction
system.cpu0.op_class_0::FloatSqrt                   0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdAdd                     0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdAlu                     0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdCmp                     0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdCvt                     0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdMisc                    0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdMult                    0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdShift                   0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdSqrt                    0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAdd                0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCmp                0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCvt                0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMisc               0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMult               0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     69.61% # Class of committed instruction
system.cpu0.op_class_0::MemRead              82336787     15.80%     85.41% # Class of committed instruction
system.cpu0.op_class_0::MemWrite             75604792     14.51%     99.92% # Class of committed instruction
system.cpu0.op_class_0::FloatMemRead            54276      0.01%     99.93% # Class of committed instruction
system.cpu0.op_class_0::FloatMemWrite          376955      0.07%    100.00% # Class of committed instruction
system.cpu0.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
system.cpu0.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
system.cpu0.op_class_0::total               521139520                       # Class of committed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13802                       # number of quiesce instructions executed
system.cpu0.tickCycles                      716804238                       # Number of cycles that the object actually ticked
system.cpu0.idleCycles                      265939120                       # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements          5714630                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          503.374360                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          153605175                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5715141                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            26.876883                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       5354308000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   503.374360                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.983153                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.983153                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          391                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          100                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        326958988                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       326958988                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     78624149                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       78624149                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     70655306                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      70655306                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       268473                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       268473                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       172491                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       172491                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1691736                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1691736                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1666426                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1666426                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    149451946                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       149451946                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    149720419                       # number of overall hits
system.cpu0.dcache.overall_hits::total      149720419                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3212821                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3212821                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      2434459                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2434459                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       667240                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       667240                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       831306                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       831306                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       163515                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       163515                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       187633                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       187633                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      6478586                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       6478586                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      7145826                       # number of overall misses
system.cpu0.dcache.overall_misses::total      7145826                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  52300502500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  52300502500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  52442906000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  52442906000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  26430842500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  26430842500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2572412500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2572412500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4480220000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4480220000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2147000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2147000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 131174251000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 131174251000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 131174251000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 131174251000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     81836970                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     81836970                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     73089765                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     73089765                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       935713                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       935713                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1003797                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1003797                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1855251                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      1855251                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1854059                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      1854059                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    155930532                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    155930532                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    156866245                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    156866245                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.039259                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.039259                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033308                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.033308                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.713082                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.713082                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.828161                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.828161                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088136                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088136                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.101201                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.101201                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.041548                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.041548                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.045554                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.045554                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16278.685461                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16278.685461                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21541.913830                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 21541.913830                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31794.360320                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31794.360320                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15731.966486                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15731.966486                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23877.569511                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23877.569511                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20247.358143                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20247.358143                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18356.765334                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18356.765334                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      5714633                       # number of writebacks
system.cpu0.dcache.writebacks::total          5714633                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       202792                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       202792                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1014502                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1014502                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           93                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total           93                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        43372                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        43372                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           49                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total           49                       # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1217387                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1217387                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1217387                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1217387                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3010029                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3010029                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1419957                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1419957                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       664995                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       664995                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       831213                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       831213                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       120143                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       120143                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       187584                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       187584                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      5261199                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5261199                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5926194                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5926194                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31550                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31550                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        31201                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        31201                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        62751                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        62751                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  44196910500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  44196910500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  29509664500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  29509664500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16065417000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16065417000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  25593186000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  25593186000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1671520500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1671520500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4291457000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4291457000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1958500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1958500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  99299761000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  99299761000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115365178000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 115365178000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6087891000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6087891000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6087891000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6087891000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036781                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036781                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019428                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019428                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.710683                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.710683                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.828069                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.828069                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064758                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064758                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.101175                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.101175                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.033741                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.033741                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.037779                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.037779                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14683.217504                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14683.217504                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20782.083190                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20782.083190                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24158.703449                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24158.703449                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30790.165698                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30790.165698                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13912.758130                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13912.758130                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22877.521537                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22877.521537                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18873.979296                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18873.979296                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19466.993149                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19466.993149                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 192960.095087                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192960.095087                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97016.637185                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97016.637185                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          9611464                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.928699                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          231001616                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          9611976                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            24.032688                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      22883257000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.928699                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999861                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999861                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          426                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        490839190                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       490839190                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    231001616                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      231001616                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    231001616                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       231001616                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    231001616                       # number of overall hits
system.cpu0.icache.overall_hits::total      231001616                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      9611986                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      9611986                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      9611986                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       9611986                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      9611986                       # number of overall misses
system.cpu0.icache.overall_misses::total      9611986                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  98657772000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  98657772000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  98657772000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  98657772000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  98657772000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  98657772000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    240613602                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    240613602                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    240613602                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    240613602                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    240613602                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    240613602                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039948                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.039948                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039948                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.039948                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039948                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.039948                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10264.036173                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10264.036173                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10264.036173                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10264.036173                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10264.036173                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10264.036173                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      9611464                       # number of writebacks
system.cpu0.icache.writebacks::total          9611464                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9611986                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      9611986                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      9611986                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      9611986                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      9611986                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      9611986                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52284                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        52284                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52284                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        52284                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  93851779000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  93851779000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  93851779000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  93851779000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  93851779000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  93851779000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5161606000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5161606000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   5161606000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   5161606000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039948                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039948                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039948                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.039948                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039948                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.039948                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9764.036173                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9764.036173                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9764.036173                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9764.036173                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9764.036173                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9764.036173                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98722.477240                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98722.477240                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      7434042                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      7435434                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         1234                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       974582                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements         2611270                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15687.218696                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          13797239                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2627042                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            5.252005                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      5985886000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15319.283860                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    42.805682                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    26.313962                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   298.815192                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.935015                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002613                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001606                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.018238                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.957472                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          263                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           99                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15410                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           82                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3           89                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           92                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1           19                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           19                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           35                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           26                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         2136                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5462                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5455                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2257                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.016052                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006042                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.940552                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       526460646                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      526460646                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       522971                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       177971                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        700942                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      3820006                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      3820006                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks     11503050                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total     11503050                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       900259                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       900259                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8923530                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      8923530                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2824509                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2824509                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       229490                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       229490                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       522971                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       177971                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      8923530                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3724768                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       13349240                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       522971                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       177971                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      8923530                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3724768                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      13349240                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        20616                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         9971                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        30587                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       242554                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       242554                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       187582                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       187582                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       283527                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       283527                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       688455                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       688455                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       970291                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       970291                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       601723                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       601723                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        20616                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         9971                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       688455                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1253818                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1972860                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        20616                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         9971                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       688455                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1253818                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1972860                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    693953500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    416737500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   1110691000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    877430000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    877430000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    285529500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    285529500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1883000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1883000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  15417318498                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  15417318498                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  25525674000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  25525674000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  37603567991                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  37603567991                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data       104000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total       104000                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    693953500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    416737500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  25525674000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  53020886489                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  79657251489                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    693953500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    416737500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  25525674000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  53020886489                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  79657251489                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       543587                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       187942                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       731529                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3820006                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      3820006                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks     11503050                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total     11503050                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       242554                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       242554                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       187582                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       187582                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1183786                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1183786                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      9611985                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      9611985                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3794800                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      3794800                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       831213                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       831213                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       543587                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       187942                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      9611985                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      4978586                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     15322100                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       543587                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       187942                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      9611985                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      4978586                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     15322100                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.037926                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.053054                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.041812                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.239509                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.239509                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.071625                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.071625                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.255690                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.255690                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.723910                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.723910                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.037926                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.053054                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.071625                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.251842                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.128759                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.037926                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.053054                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.071625                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.251842                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.128759                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33660.918704                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41794.955371                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36312.518390                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3617.462503                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3617.462503                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1522.158309                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1522.158309                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       941500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       941500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54376.897079                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54376.897079                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37076.750114                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37076.750114                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38754.938458                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38754.938458                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data     0.172837                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total     0.172837                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33660.918704                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41794.955371                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37076.750114                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42287.546110                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 40376.535329                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33660.918704                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41794.955371                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37076.750114                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42287.546110                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 40376.535329                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs           25                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           25                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           44451                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks      1620068                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1620068                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker           23                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker           98                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          121                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         8857                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         8857                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            6                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            6                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          996                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          996                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            2                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker           23                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker           98                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            6                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         9853                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         9980                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker           23                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker           98                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            6                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         9853                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         9980                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        20593                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         9873                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        30466                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       782341                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       782341                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       242554                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       242554                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       187582                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       187582                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       274670                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       274670                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       688449                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       688449                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       969295                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       969295                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       601721                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       601721                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        20593                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         9873                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       688449                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1243965                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1962880                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        20593                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         9873                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       688449                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1243965                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       782341                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2745221                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52284                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31550                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        83834                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        31201                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        31201                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52284                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        62751                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       115035                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    569758000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    355875500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    925633500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  38599728272                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  38599728272                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4476827494                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4476827494                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2879854497                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2879854497                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1583000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1583000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  12562742498                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  12562742498                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  21394767500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  21394767500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  31646923991                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  31646923991                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  19132934000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  19132934000                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    569758000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    355875500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  21394767500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  44209666489                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  66530067489                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    569758000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    355875500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  21394767500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  44209666489                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  38599728272                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 105129795761                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4743334000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5835246500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total  10578580500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4743334000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5835246500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10578580500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.037884                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.052532                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.041647                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.232027                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.232027                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.071624                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.071624                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.255427                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.255427                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.723907                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.723907                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.037884                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.052532                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.071624                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.249863                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.128108                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.037884                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.052532                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.071624                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.249863                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.179167                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30382.508370                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49338.751608                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49338.751608                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18457.034285                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18457.034285                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15352.509820                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15352.509820                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       791500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       791500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45737.585095                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45737.585095                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31076.764582                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31076.764582                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32649.424572                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32649.424572                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31797.018884                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31797.018884                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31076.764582                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35539.317014                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33894.108396                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31076.764582                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35539.317014                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49338.751608                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38295.567374                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184952.345483                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126184.847437                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92990.494175                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91959.668796                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests     31463839                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     16044170                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         3048                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       652134                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       652077                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops           57                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        887708                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     14387458                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        31201                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        31200                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5457517                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean     11506087                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      1359708                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       999352                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       454749                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       343952                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       493156                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           49                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           97                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1220335                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1191280                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9611986                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4900402                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       909564                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       832554                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     28940003                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18484921                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       391848                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1143553                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         48960325                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side   1233646912                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    690994144                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1503536                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4348696                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1930493288                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    5822948                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic            111810824                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples     22356517                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.042093                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.200815                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          21415512     95.79%     95.79% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            940948      4.21%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                57      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      22356517                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   31390166976                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    183129639                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy  14498904485                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8149348322                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    204016279                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    600088255                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              132997996                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         94215152                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          6033479                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            99520242                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               69476937                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            69.811865                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               15575496                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect           1022946                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        3462102                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           2360825                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses         1101277                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted       401735                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                   271949                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               271949                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         9428                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        76874                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples       271949                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         271949    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       271949                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        86302                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23685.366504                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21920.409810                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 15487.631024                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        85344     98.89%     98.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          718      0.83%     99.72% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          138      0.16%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           39      0.05%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           32      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           18      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        86302                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples    114608944                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0      114608944    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total    114608944                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        76874     89.08%     89.08% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         9428     10.92%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        86302                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       271949                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       271949                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        86302                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        86302                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       358251                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    86154833                       # DTB read hits
system.cpu1.dtb.read_misses                    225974                       # DTB read misses
system.cpu1.dtb.write_hits                   74805729                       # DTB write hits
system.cpu1.dtb.write_misses                    45975                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              40720                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   36571                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     1221                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  7188                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10263                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                86380807                       # DTB read accesses
system.cpu1.dtb.write_accesses               74851704                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        160960562                       # DTB hits
system.cpu1.dtb.misses                         271949                       # DTB misses
system.cpu1.dtb.accesses                    161232511                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    60899                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                60899                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          513                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        50941                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        60899                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          60899    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        60899                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        51454                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 25618.018036                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23516.416553                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 19409.340181                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        50489     98.12%     98.12% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          670      1.30%     99.43% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          212      0.41%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           46      0.09%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           12      0.02%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215            7      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359           13      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        51454                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples    113972444                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0      113972444    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total    113972444                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        50941     99.00%     99.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          513      1.00%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        51454                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        60899                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        60899                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        51454                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        51454                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       112353                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   236231380                       # ITB inst hits
system.cpu1.itb.inst_misses                     60899                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              40720                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   26538                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   178013                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               236292279                       # ITB inst accesses
system.cpu1.itb.hits                        236231380                       # DTB hits
system.cpu1.itb.misses                          60899                       # DTB misses
system.cpu1.itb.accesses                    236292279                       # DTB accesses
system.cpu1.numPwrStateTransitions               9440                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         4720                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    9937322156.794067                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   214697400239.899719                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         3380     71.61%     71.61% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         1320     27.97%     99.58% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            5      0.11%     99.68% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.02%     99.70% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            2      0.04%     99.75% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            1      0.02%     99.77% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11            1      0.02%     99.79% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           10      0.21%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 11813594348000                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           4720                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   452049545932                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 46904160580068                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                       904105497                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  436062178                       # Number of instructions committed
system.cpu1.committedOps                    513430287                       # Number of ops (including micro ops) committed
system.cpu1.discardedOps                     45590191                       # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends                     4720                       # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles                 93808990671                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi                              2.073341                       # CPI: cycles per instruction
system.cpu1.ipc                              0.482313                       # IPC: instructions per cycle
system.cpu1.op_class_0::No_OpClass                  1      0.00%      0.00% # Class of committed instruction
system.cpu1.op_class_0::IntAlu              354600208     69.06%     69.06% # Class of committed instruction
system.cpu1.op_class_0::IntMult               1143323      0.22%     69.29% # Class of committed instruction
system.cpu1.op_class_0::IntDiv                  59569      0.01%     69.30% # Class of committed instruction
system.cpu1.op_class_0::FloatAdd                    0      0.00%     69.30% # Class of committed instruction
system.cpu1.op_class_0::FloatCmp                    0      0.00%     69.30% # Class of committed instruction
system.cpu1.op_class_0::FloatCvt                    0      0.00%     69.30% # Class of committed instruction
system.cpu1.op_class_0::FloatMult                   0      0.00%     69.30% # Class of committed instruction
system.cpu1.op_class_0::FloatMultAcc                0      0.00%     69.30% # Class of committed instruction
system.cpu1.op_class_0::FloatDiv                    0      0.00%     69.30% # Class of committed instruction
system.cpu1.op_class_0::FloatMisc               63096      0.01%     69.31% # Class of committed instruction
system.cpu1.op_class_0::FloatSqrt                   0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdAdd                     0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdAlu                     0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdCmp                     0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdCvt                     0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdMisc                    0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdMult                    0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdShift                   0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdSqrt                    0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMisc               0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMult               0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     69.31% # Class of committed instruction
system.cpu1.op_class_0::MemRead              82989666     16.16%     85.48% # Class of committed instruction
system.cpu1.op_class_0::MemWrite             74191847     14.45%     99.93% # Class of committed instruction
system.cpu1.op_class_0::FloatMemRead            64253      0.01%     99.94% # Class of committed instruction
system.cpu1.op_class_0::FloatMemWrite          318324      0.06%    100.00% # Class of committed instruction
system.cpu1.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
system.cpu1.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
system.cpu1.op_class_0::total               513430287                       # Class of committed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    4720                       # number of quiesce instructions executed
system.cpu1.tickCycles                      704305988                       # Number of cycles that the object actually ticked
system.cpu1.idleCycles                      199799509                       # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements          5048947                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          416.228585                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          153590869                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5049459                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            30.417292                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8378525599500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   416.228585                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.812946                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.812946                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          402                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        324622701                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       324622701                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data     79356977                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       79356977                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     69837106                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      69837106                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       233112                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       233112                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       147127                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       147127                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1782955                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1782955                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1749534                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1749534                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    149341210                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       149341210                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    149574322                       # number of overall hits
system.cpu1.dcache.overall_hits::total      149574322                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3104936                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3104936                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      2154320                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      2154320                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       600203                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       600203                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       416637                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       416637                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       162547                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       162547                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       194652                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       194652                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      5675893                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       5675893                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      6276096                       # number of overall misses
system.cpu1.dcache.overall_misses::total      6276096                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  47629871000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  47629871000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  40774475000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  40774475000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data   9727566000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total   9727566000                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2415502000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2415502000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4643846000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4643846000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2158500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2158500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  98131912000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  98131912000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  98131912000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  98131912000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     82461913                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     82461913                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     71991426                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     71991426                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       833315                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       833315                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       563764                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       563764                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1945502                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1945502                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1944186                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1944186                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    155017103                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    155017103                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    155850418                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    155850418                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037653                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.037653                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.029925                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.029925                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.720259                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.720259                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.739027                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.739027                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.083550                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.083550                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100120                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100120                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.036615                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.036615                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040270                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.040270                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15340.049199                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15340.049199                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18926.842345                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18926.842345                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23347.820765                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23347.820765                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14860.329628                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14860.329628                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23857.170746                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23857.170746                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17289.246291                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17289.246291                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15635.820740                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15635.820740                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks      5048949                       # number of writebacks
system.cpu1.dcache.writebacks::total          5048949                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       157294                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total       157294                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       878635                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       878635                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           59                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total           59                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        39126                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        39126                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           65                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total           65                       # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      1035988                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      1035988                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      1035988                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      1035988                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2947642                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2947642                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1275685                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1275685                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       599894                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       599894                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       416578                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       416578                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       123421                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       123421                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       194587                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       194587                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4639905                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4639905                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5239799                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5239799                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         6968                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         6968                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         7187                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         7187                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        14155                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        14155                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  41244047000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  41244047000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  23526690000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  23526690000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13870615000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13870615000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   9306680500                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total   9306680500                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1636714500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1636714500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4447799000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4447799000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1876000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1876000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  74077417500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  74077417500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  87948032500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  87948032500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    882714500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    882714500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    882714500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    882714500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035745                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035745                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017720                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017720                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.719889                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.719889                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.738923                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.738923                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063439                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.063439                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100087                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100087                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029932                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.029932                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033621                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.033621                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13992.217169                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13992.217169                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18442.397614                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18442.397614                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23121.776514                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23121.776514                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22340.787320                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22340.787320                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13261.231881                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13261.231881                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22857.636944                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22857.636944                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15965.287544                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15965.287544                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16784.619505                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16784.619505                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126681.185419                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 126681.185419                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 62360.614624                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 62360.614624                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements          9106015                       # number of replacements
system.cpu1.icache.tags.tagsinuse          507.214941                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          226941610                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          9106527                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            24.920764                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8368863514500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.214941                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990654                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.990654                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        481202803                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       481202803                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst    226941610                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      226941610                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    226941610                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       226941610                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    226941610                       # number of overall hits
system.cpu1.icache.overall_hits::total      226941610                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      9106528                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      9106528                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      9106528                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       9106528                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      9106528                       # number of overall misses
system.cpu1.icache.overall_misses::total      9106528                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  93334039500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  93334039500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  93334039500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  93334039500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  93334039500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  93334039500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    236048138                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    236048138                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    236048138                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    236048138                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    236048138                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    236048138                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.038579                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.038579                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.038579                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.038579                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.038579                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.038579                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10249.135510                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10249.135510                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10249.135510                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10249.135510                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10249.135510                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10249.135510                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks      9106015                       # number of writebacks
system.cpu1.icache.writebacks::total          9106015                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9106528                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      9106528                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      9106528                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      9106528                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      9106528                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      9106528                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           95                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           95                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           95                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           95                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  88780776000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  88780776000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  88780776000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  88780776000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  88780776000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  88780776000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9602500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9602500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9602500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      9602500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.038579                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.038579                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.038579                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.038579                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.038579                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.038579                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9749.135565                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9749.135565                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9749.135565                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  9749.135565                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9749.135565                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  9749.135565                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101078.947368                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101078.947368                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101078.947368                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101078.947368                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7104941                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7105044                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           91                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       891372                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements         2193537                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13101.642441                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          12964075                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2209317                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            5.867911                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12819.727283                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    29.247108                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    16.647207                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   236.020843                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.782454                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001785                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.001016                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.014406                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.799661                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          358                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           47                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15375                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           11                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          152                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          121                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           74                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           36                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          232                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1753                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         6630                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5167                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1593                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.021851                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002869                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.938416                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       486850576                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      486850576                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       506555                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       152150                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        658705                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3098065                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3098065                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks     11055157                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total     11055157                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data            1                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            1                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       815552                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       815552                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8406399                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      8406399                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2722472                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2722472                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       157346                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       157346                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       506555                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       152150                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      8406399                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3538024                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total       12603128                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       506555                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       152150                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      8406399                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3538024                       # number of overall hits
system.cpu1.l2cache.overall_hits::total      12603128                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        20442                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9977                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        30419                       # number of ReadReq misses
system.cpu1.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
system.cpu1.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       219088                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       219088                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       194583                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       194583                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       241398                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       241398                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       700129                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       700129                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       948287                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       948287                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       259232                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       259232                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        20442                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9977                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       700129                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1189685                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1920233                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        20442                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9977                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       700129                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1189685                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1920233                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    617018000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    362407000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total    979425000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    937065000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    937065000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    273754000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    273754000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1804499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1804499                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10806413996                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  10806413996                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  24362152500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  24362152500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  33291553995                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  33291553995                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data       509000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total       509000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    617018000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    362407000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  24362152500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  44097967991                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  69439545491                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    617018000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    362407000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  24362152500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  44097967991                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  69439545491                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       526997                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       162127                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       689124                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3098065                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3098065                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks     11055158                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total     11055158                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       219089                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       219089                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       194584                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       194584                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1056950                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1056950                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      9106528                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      9106528                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3670759                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3670759                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       416578                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       416578                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       526997                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       162127                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      9106528                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4727709                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     14523361                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       526997                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       162127                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      9106528                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4727709                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     14523361                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.038790                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.061538                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.044142                       # miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.999995                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999995                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999995                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999995                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.228391                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.228391                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.076882                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.076882                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.258335                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.258335                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.622289                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.622289                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.038790                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.061538                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.076882                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.251641                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.132217                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.038790                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.061538                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.076882                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.251641                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.132217                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30183.837198                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36324.245765                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32197.804004                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4277.116958                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4277.116958                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1406.875215                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1406.875215                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 601499.666667                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 601499.666667                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44765.963247                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44765.963247                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34796.662472                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34796.662472                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35107.044592                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35107.044592                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data     1.963492                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total     1.963492                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30183.837198                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36324.245765                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34796.662472                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37066.927793                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 36162.041529                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30183.837198                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36324.245765                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34796.662472                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37066.927793                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 36162.041529                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches           43998                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks      1082545                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1082545                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker           17                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           90                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          107                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         6036                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         6036                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            4                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          724                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          724                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            3                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            3                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker           17                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           90                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            4                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         6760                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         6871                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker           17                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           90                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            4                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         6760                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         6871                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        20425                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9887                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        30312                       # number of ReadReq MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       721434                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       721434                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       219088                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       219088                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       194583                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       194583                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       235362                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       235362                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       700125                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       700125                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       947563                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       947563                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       259229                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       259229                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        20425                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9887                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       700125                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1182925                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1913362                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        20425                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9887                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       700125                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1182925                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       721434                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2634796                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           95                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         6968                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         7063                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         7187                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         7187                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           95                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        14155                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        14250                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    494064000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    301606000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    795670000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  29780460685                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  29780460685                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4150846499                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4150846499                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2983943996                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2983943996                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1522499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1522499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8542642996                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8542642996                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  20161321500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  20161321500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  27488554995                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  27488554995                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6032275000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6032275000                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    494064000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    301606000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  20161321500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  36031197991                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  56988189491                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    494064000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    301606000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  20161321500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  36031197991                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  29780460685                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  86768650176                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8842500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    826904500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    835747000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8842500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    826904500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    835747000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.038757                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.060983                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.043986                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.999995                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.999995                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999995                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999995                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.222680                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.222680                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.076882                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.076882                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.258138                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.258138                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.622282                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.622282                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.038757                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.060983                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.076882                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.250211                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.131744                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.038757                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.060983                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.076882                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.250211                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.181418                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26249.340195                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41279.535876                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41279.535876                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18946.023968                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18946.023968                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15335.070361                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15335.070361                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 507499.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 507499.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36295.761406                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36295.761406                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28796.745581                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28796.745581                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29009.738661                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29009.738661                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23270.062377                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23270.062377                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28796.745581                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30459.410352                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29784.321781                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28796.745581                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30459.410352                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41279.535876                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32931.828565                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93078.947368                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 118671.713548                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118327.481240                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93078.947368                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 58417.838220                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 58648.912281                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests     29139456                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     14890637                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1736                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       592017                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       591980                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops           37                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq        780515                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     13649954                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         7187                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         7187                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4195318                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean     11056894                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      1429217                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       912059                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       423433                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       346671                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       478761                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           53                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           97                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1089502                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1063784                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      9106528                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4703864                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       480825                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       417736                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     27319260                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16358508                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       344119                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1118457                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         45140344                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side   1165608768                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    632082996                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1297016                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4215976                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1803204756                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5174570                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic             77236160                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples     20377107                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.044844                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.206971                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          19463345     95.52%     95.52% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            913725      4.48%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                37      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      20377107                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   28962136490                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    181919759                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy  13662646557                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7521057995                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    182080323                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    591562794                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40336                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40336                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136646                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136645                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47799                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122681                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231202                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231202                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353963                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47820                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155812                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338824                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338824                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496722                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             42736003                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               316501                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               16500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25813003                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            34441500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           569849738                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92766000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147898000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115581                       # number of replacements
system.iocache.tags.tagsinuse               11.283387                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115597                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9167357489000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.841167                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.442220                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.240073                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.465139                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.705212                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040766                       # Number of tag accesses
system.iocache.tags.data_accesses             1040766                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8873                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8910                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115601                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115641                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115601                       # number of overall misses
system.iocache.overall_misses::total           115641                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5212500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1870801980                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1876014480                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13212782258                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13212782258                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5581500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  15083584238                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  15089165738                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5581500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  15083584238                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  15089165738                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8873                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8910                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115601                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115641                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115601                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115641                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140878.378378                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 210842.103009                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 210551.569024                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123798.649445                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 123798.649445                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139537.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 130479.703791                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 130482.836866                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139537.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 130479.703791                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 130482.836866                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         43615                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3535                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.338048                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106693                       # number of writebacks
system.iocache.writebacks::total               106693                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8873                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8910                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115601                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115641                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115601                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115641                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3362500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1427151980                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1430514480                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7870696448                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7870696448                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3581500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9297848428                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9301429928                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3581500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9297848428                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9301429928                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90878.378378                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 160842.103009                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 160551.569024                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73745.375609                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73745.375609                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89537.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80430.519009                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 80433.669097                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89537.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80430.519009                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 80433.669097                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1414426                       # number of replacements
system.l2c.tags.tagsinuse                65137.583571                       # Cycle average of tags in use
system.l2c.tags.total_refs                    6994560                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1476169                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     4.738319                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               8133240500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   11569.884492                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   195.527132                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   189.575172                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5571.537349                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    16752.169298                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10126.474274                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   243.722413                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   247.067471                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3668.697792                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     7415.172357                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  9157.755820                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.176542                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002984                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.002893                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.085015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.255618                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.154518                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003719                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003770                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.055980                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.113147                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.139736                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993921                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        10627                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          250                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        50866                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          125                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          764                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9737                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          246                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          240                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1551                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4265                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        44783                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.162155                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003815                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.776154                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 76792424                       # Number of tag accesses
system.l2c.tags.data_accesses                76792424                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks      2702608                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2702608                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data          192434                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          150964                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              343398                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         50257                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         52778                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total            103035                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            55782                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            52105                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               107887                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        13231                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5451                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       616225                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       581799                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       304510                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        10640                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4481                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       647147                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       570987                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       311044                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          3065515                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       124497                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       122676                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           247173                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker         13231                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          5451                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              616225                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              637581                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       304510                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         10640                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4481                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              647147                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              623092                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       311044                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 3173402                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        13231                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         5451                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             616225                       # number of overall hits
system.l2c.overall_hits::cpu0.data             637581                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       304510                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        10640                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4481                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             647147                       # number of overall hits
system.l2c.overall_hits::cpu1.data             623092                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       311044                       # number of overall hits
system.l2c.overall_hits::total                3173402                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         19140                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         25859                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             44999                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          523                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          682                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1205                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          81279                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          45582                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             126861                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2187                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1999                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        72224                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       145719                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       234962                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1644                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1517                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        52978                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data        99810                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       174436                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         787476                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       432248                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data        85316                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         517564                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2187                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1999                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             72224                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            226998                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       234962                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1644                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1517                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             52978                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            145392                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       174436                       # number of demand (read+write) misses
system.l2c.demand_misses::total                914337                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2187                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1999                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            72224                       # number of overall misses
system.l2c.overall_misses::cpu0.data           226998                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       234962                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1644                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1517                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            52978                       # number of overall misses
system.l2c.overall_misses::cpu1.data           145392                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       174436                       # number of overall misses
system.l2c.overall_misses::total               914337                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    159938500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    143600000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    303538500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      6591000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      8923000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total     15514000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   8642428000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4940577000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  13583005000                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    231505500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    211185500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   7798644500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  15829133000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  33053703122                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    165185000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    157137500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   6014742000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  11671652500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  24159469102                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  99292357724                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    231505500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    211185500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   7798644500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  24471561000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  33053703122                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    165185000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    157137500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   6014742000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  16612229500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  24159469102                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    112875362724                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    231505500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    211185500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   7798644500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  24471561000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  33053703122                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    165185000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    157137500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   6014742000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  16612229500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  24159469102                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   112875362724                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2702608                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2702608                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       211574                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       176823                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          388397                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        50780                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        53460                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total        104240                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       137061                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        97687                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           234748                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        15418                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7450                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       688449                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       727518                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       539472                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        12284                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5998                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       700125                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       670797                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       485480                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3852991                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       556745                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       207992                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       764737                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        15418                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7450                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          688449                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          864579                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       539472                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        12284                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         5998                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          700125                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          768484                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       485480                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4087739                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        15418                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7450                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         688449                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         864579                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       539472                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        12284                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         5998                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         700125                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         768484                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       485480                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4087739                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.090465                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.146242                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.115858                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.010299                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.012757                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.011560                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.593013                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.466613                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.540414                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.141847                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.268322                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.104908                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.200296                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.435541                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.133833                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.252918                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.075669                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.148793                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.359306                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.204380                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.776384                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.410189                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.676787                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.141847                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.268322                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.104908                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.262553                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.435541                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.133833                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.252918                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.075669                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.189193                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.359306                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.223678                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.141847                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.268322                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.104908                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.262553                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.435541                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.133833                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.252918                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.075669                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.189193                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.359306                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.223678                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  8356.243469                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5553.192312                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6745.449899                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12602.294455                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13083.577713                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 12874.688797                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 106330.392844                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108388.771884                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 107069.982106                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 105855.281207                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 105645.572786                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 107978.573604                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 108627.790473                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 100477.493917                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103584.377060                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 113532.824946                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116938.708546                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 126089.376342                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 105855.281207                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 105645.572786                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 107978.573604                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 107805.183306                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 100477.493917                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103584.377060                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 113532.824946                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 114258.208842                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 123450.503178                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 105855.281207                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 105645.572786                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 107978.573604                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 107805.183306                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 100477.493917                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103584.377060                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 113532.824946                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 114258.208842                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 123450.503178                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               159                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        6                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     26.500000                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1064634                       # number of writebacks
system.l2c.writebacks::total                  1064634                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          107                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           22                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          137                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           23                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          289                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst            107                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             22                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            137                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             23                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                289                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst           107                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            22                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           137                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            23                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               289                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        58693                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        58693                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        19140                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        25859                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        44999                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          523                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          682                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1205                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        81279                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        45582                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        126861                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         2187                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1999                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        72117                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       145697                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       234962                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1644                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1517                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        52841                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data        99787                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       174436                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       787187                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       432248                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data        85316                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       517564                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         2187                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1999                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        72117                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       226976                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       234962                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1644                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1517                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        52841                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       145369                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       174436                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           914048                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         2187                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1999                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        72117                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       226976                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       234962                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1644                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1517                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        52841                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       145369                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       174436                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          914048                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        52284                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31550                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           95                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         6966                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        90895                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        31201                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         7187                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38388                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        52284                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        62751                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           95                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        14153                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       129283                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    389704500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    525466000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    915170500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     12566500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     16471000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     29037500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7829611555                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4484731054                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  12314342609                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    209631508                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    191194502                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   7068927036                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  14369749705                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  30703963878                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    148744501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    141966502                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   5474322057                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  10671015209                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  22414941954                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  91394456852                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   8929441001                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   1642247000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  10571688001                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    209631508                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    191194502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   7068927036                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  22199361260                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  30703963878                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    148744501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    141966502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   5474322057                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  15155746263                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  22414941954                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 103708799461                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    209631508                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    191194502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   7068927036                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  22199361260                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  30703963878                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    148744501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    141966502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   5474322057                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  15155746263                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  22414941954                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 103708799461                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3645369500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5267143505                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6847500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    701418504                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   9620779009                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3645369500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5267143505                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6847500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    701418504                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   9620779009                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.090465                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.146242                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.115858                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.010299                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.012757                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.011560                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.593013                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.466613                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.540414                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.141847                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.268322                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.104753                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.200266                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.435541                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.133833                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.252918                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.075474                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.148759                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.359306                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.204305                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.776384                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.410189                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.676787                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.141847                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.268322                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.104753                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.262528                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.435541                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.133833                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.252918                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.075474                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.189163                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.359306                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.223607                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.141847                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.268322                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.104753                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.262528                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.435541                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.133833                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.252918                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.075474                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.189163                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.359306                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.223607                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20360.736677                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20320.430024                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20337.574168                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24027.724665                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24151.026393                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24097.510373                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 96330.067484                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98388.202668                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 97069.569127                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 98020.259245                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 98627.629292                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103599.895100                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106937.929881                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116102.599321                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20658.143013                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19248.991983                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20425.856514                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 98020.259245                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 97804.883600                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103599.895100                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 104257.071748                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 113460.999270                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 98020.259245                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 97804.883600                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103599.895100                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 104257.071748                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 113460.999270                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166945.911410                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72078.947368                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100691.717485                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105844.975070                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83937.204268                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72078.947368                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 49559.704939                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 74416.427597                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests       3622014                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      2135906                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         2993                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               90895                       # Transaction distribution
system.membus.trans_dist::ReadResp             886992                       # Transaction distribution
system.membus.trans_dist::WriteReq              38388                       # Transaction distribution
system.membus.trans_dist::WriteResp             38387                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1171327                       # Transaction distribution
system.membus.trans_dist::CleanEvict           257625                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           339183                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         279038                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              24                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq            141595                       # Transaction distribution
system.membus.trans_dist::ReadExResp           126059                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        796097                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        636810                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        29788                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122681                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           54                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25906                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4412900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4561541                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238275                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       238275                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4799816                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155812                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1388                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51812                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    129909760                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    130118772                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7279744                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7279744                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               137398516                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           631660                       # Total snoops (count)
system.membus.snoopTraffic                     165184                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2322011                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.014128                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.118018                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 2289206     98.59%     98.59% # Request fanout histogram
system.membus.snoop_fanout::1                   32805      1.41%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2322011                       # Request fanout histogram
system.membus.reqLayer0.occupancy           103411493                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               34812                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21687499                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8057234059                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         5202386097                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           79808698                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     12161965                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      6407928                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      2357892                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         209457                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       187271                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        22186                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              90897                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4728170                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38388                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38387                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      3767242                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2958537                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          681779                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        382073                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1063852                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           97                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           97                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           289918                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          289918                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4637675                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       890912                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       871981                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9721848                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8056306                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17778154                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    242672912                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    195596708                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              438269620                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2964469                       # Total snoops (count)
system.toL2Bus.snoopTraffic                 121867728                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples          8426211                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.390204                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.493164                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                5160452     61.24%     61.24% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                3243573     38.49%     99.74% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  22186      0.26%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            8426211                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         9265268057                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          8336972                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4478456950                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4027071928                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
