
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000024                       # Number of seconds simulated
sim_ticks                                    24405000                       # Number of ticks simulated
final_tick                                   24405000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  38911                       # Simulator instruction rate (inst/s)
host_op_rate                                    38904                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              189891987                       # Simulator tick rate (ticks/s)
host_mem_usage                                 234100                       # Number of bytes of host memory used
host_seconds                                     0.13                       # Real time elapsed on the host
sim_insts                                        4999                       # Number of instructions simulated
sim_ops                                          4999                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             21056                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              8960                       # Number of bytes read from this memory
system.physmem.bytes_read::total                30016                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        21056                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           21056                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                329                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                140                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   469                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            862774022                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            367137882                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1229911903                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       862774022                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          862774022                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           862774022                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           367137882                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1229911903                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           469                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         469                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    30016                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     30016                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  29                       # Per bank write bursts
system.physmem.perBankRdBursts::1                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::2                   1                       # Per bank write bursts
system.physmem.perBankRdBursts::3                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::4                   7                       # Per bank write bursts
system.physmem.perBankRdBursts::5                   3                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  13                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  53                       # Per bank write bursts
system.physmem.perBankRdBursts::8                  59                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  76                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 43                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 21                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 51                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 29                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 77                       # Per bank write bursts
system.physmem.perBankRdBursts::15                  7                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        24305500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     469                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       270                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       135                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        40                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        17                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          114                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      261.614035                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     175.762153                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     255.654479                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             36     31.58%     31.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           34     29.82%     61.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           19     16.67%     78.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            8      7.02%     85.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            4      3.51%     88.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            2      1.75%     90.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            4      3.51%     93.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            3      2.63%     96.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            4      3.51%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            114                       # Bytes accessed per row activation
system.physmem.totQLat                        7577250                       # Total ticks spent queuing
system.physmem.totMemAccLat                  16371000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      2345000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       16156.18                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  34906.18                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                        1229.91                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                     1229.91                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           9.61                       # Data bus utilization in percentage
system.physmem.busUtilRead                       9.61                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.76                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        352                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.05                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        51824.09                       # Average gap between requests
system.physmem.pageHitRate                      75.05                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     192780                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                      98670                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                    756840                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           1843920.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy                1602840                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                  46560                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy           8339100                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy            952800                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy                 13833510                       # Total energy per rank (pJ)
system.physmem_0.averagePower              566.830977                       # Core power per rank (mW)
system.physmem_0.totalIdleTime               20709000                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE          23500                       # Time in different power states
system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN      2481250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT         2828750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN     18291500                       # Time in different power states
system.physmem_1.actEnergy                     642600                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                     333960                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                   2591820                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           1843920.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy                4214580                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                  89760                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy           6593190                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy            180480                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy                 16490310                       # Total energy per rank (pJ)
system.physmem_1.averagePower              675.693915                       # Core power per rank (mW)
system.physmem_1.totalIdleTime               14889250                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE         122500                       # Time in different power states
system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN       470250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT         8563750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN     14468500                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                    2188                       # Number of BP lookups
system.cpu.branchPred.condPredicted              1456                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               424                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 1784                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     587                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             32.903587                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     252                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 70                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups             270                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits                  2                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses              268                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted           95                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                    7                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON        24405000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                            48811                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles               9088                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          13001                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        2188                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches                841                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                          5447                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                     868                       # Number of cycles fetch has spent squashing
system.cpu.fetch.PendingTrapStallCycles           205                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                      2050                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   263                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              15174                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.856795                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.144946                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                    11814     77.86%     77.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                     1507      9.93%     87.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      111      0.73%     88.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                      162      1.07%     89.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                      279      1.84%     91.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                      100      0.66%     92.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                      140      0.92%     93.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      158      1.04%     94.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                      903      5.95%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                15174                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.044826                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.266354                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                     8420                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                  3450                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      2768                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   142                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                    394                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved                  183                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                    40                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts                  12000                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   160                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                    394                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                     8571                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                     620                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           1023                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      2740                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                  1826                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                  11562                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                     5                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                      4                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                    193                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                   1606                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands                6927                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 13556                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups            13323                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups                 3                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                  3292                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                     3635                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 13                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts              9                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                       323                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 2468                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1158                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                 6                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores                2                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                       9014                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  11                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                      8118                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued                19                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined            4025                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined         2012                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         15174                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.534994                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.265800                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0               11850     78.09%     78.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                1336      8.80%     86.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                 728      4.80%     91.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                 453      2.99%     94.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                 341      2.25%     96.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 284      1.87%     98.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 110      0.72%     99.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                  53      0.35%     99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                  19      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           15174                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                       6      3.33%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc                    0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                    117     65.00%     68.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                    57     31.67%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite                0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                  4775     58.82%     58.82% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    4      0.05%     58.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     1      0.01%     58.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     58.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 2273     28.00%     86.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1063     13.09%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite              0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                   8118                       # Type of FU issued
system.cpu.iq.rate                           0.166315                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                         180                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.022173                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              31605                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             13057                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses         7337                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                  2                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                   8296                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                       2                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads               78                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads         1333                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses            5                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation           10                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores          257                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            25                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                    394                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                     490                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                    74                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts               10621                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts               154                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  2468                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 1158                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 11                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                    75                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents             10                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect            101                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          338                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                  439                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                  7790                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                  2129                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               328                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          1596                       # number of nop insts executed
system.cpu.iew.exec_refs                         3178                       # number of memory reference insts executed
system.cpu.iew.exec_branches                     1363                       # Number of branches executed
system.cpu.iew.exec_stores                       1049                       # Number of stores executed
system.cpu.iew.exec_rate                     0.159595                       # Inst execution rate
system.cpu.iew.wb_sent                           7432                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                          7339                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                      2867                       # num instructions producing a value
system.cpu.iew.wb_consumers                      4274                       # num instructions consuming a value
system.cpu.iew.wb_rate                       0.150355                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.670800                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts            4982                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls               9                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts               384                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        14293                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.394599                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.198950                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0        12101     84.66%     84.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1          885      6.19%     90.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2          521      3.65%     94.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          254      1.78%     96.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          160      1.12%     97.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5          166      1.16%     98.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6           63      0.44%     99.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7           41      0.29%     99.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8          102      0.71%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        14293                       # Number of insts commited each cycle
system.cpu.commit.committedInsts                 5640                       # Number of instructions committed
system.cpu.commit.committedOps                   5640                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                           2036                       # Number of memory references committed
system.cpu.commit.loads                          1135                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                        886                       # Number of branches committed
system.cpu.commit.fp_insts                          2                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                      4955                       # Number of committed integer instructions.
system.cpu.commit.function_calls                   85                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass          641     11.37%     11.37% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu             2959     52.46%     63.83% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult               2      0.04%     63.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     63.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              2      0.04%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc             0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.90% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead            1135     20.12%     84.02% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite            901     15.98%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total              5640                       # Class of committed instruction
system.cpu.commit.bw_lim_events                   102                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                        24800                       # The number of ROB reads
system.cpu.rob.rob_writes                       22133                       # The number of ROB writes
system.cpu.timesIdled                             264                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           33637                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                        4999                       # Number of Instructions Simulated
system.cpu.committedOps                          4999                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               9.764153                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         9.764153                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.102415                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.102415                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                    10560                       # number of integer regfile reads
system.cpu.int_regfile_writes                    5141                       # number of integer regfile writes
system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
system.cpu.misc_regfile_reads                     161                       # number of misc regfile reads
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse            91.114159                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                2395                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               140                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             17.107143                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    91.114159                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.022245                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.022245                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          140                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          109                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.034180                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              5952                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             5952                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data         1838                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1838                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          557                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            557                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          2395                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             2395                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         2395                       # number of overall hits
system.cpu.dcache.overall_hits::total            2395                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          167                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           167                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          344                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          344                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          511                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            511                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          511                       # number of overall misses
system.cpu.dcache.overall_misses::total           511                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     12709500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     12709500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     34219499                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     34219499                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     46928999                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     46928999                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     46928999                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     46928999                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         2005                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         2005                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2906                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2906                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2906                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2906                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.083292                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.083292                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.381798                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.381798                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.175843                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.175843                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.175843                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.175843                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 99475.287791                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 91837.571429                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 91837.571429                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 91837.571429                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 91837.571429                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          636                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                10                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    63.600000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           77                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          294                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          294                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          371                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          371                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          371                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          371                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           90                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           90                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           50                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          140                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          140                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          140                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          140                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8094500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      8094500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4915999                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      4915999                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13010499                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     13010499                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13010499                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     13010499                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.044888                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.044888                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055494                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.048176                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.048176                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.048176                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.048176                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98319.980000                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92932.135714                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 92932.135714                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                17                       # number of replacements
system.cpu.icache.tags.tagsinuse           160.115290                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                1613                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               332                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              4.858434                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   160.115290                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.078181                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.078181                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          315                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          183                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.153809                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              4432                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             4432                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst         1613                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            1613                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          1613                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             1613                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         1613                       # number of overall hits
system.cpu.icache.overall_hits::total            1613                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          437                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           437                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          437                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            437                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          437                       # number of overall misses
system.cpu.icache.overall_misses::total           437                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     35529000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     35529000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     35529000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     35529000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     35529000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     35529000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         2050                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         2050                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         2050                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         2050                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         2050                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         2050                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.213171                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.213171                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.213171                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.213171                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.213171                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.213171                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81302.059497                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 81302.059497                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 81302.059497                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 81302.059497                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 81302.059497                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 81302.059497                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks           17                       # number of writebacks
system.cpu.icache.writebacks::total                17                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          105                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          105                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          105                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          105                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          105                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          105                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          332                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          332                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          332                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          332                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          332                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          332                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     28112000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     28112000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     28112000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     28112000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     28112000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     28112000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.161951                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.161951                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.161951                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.161951                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.161951                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.161951                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84674.698795                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84674.698795                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84674.698795                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 84674.698795                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84674.698795                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 84674.698795                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          253.317649                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                 20                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              469                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.042644                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   162.143256                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    91.174392                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004948                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.002782                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.007731                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          469                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          171                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          298                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.014313                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             4381                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            4381                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks           17                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total           17                       # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            3                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total            3                       # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data           50                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           50                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          329                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          329                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data           90                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total           90                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          329                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          140                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           469                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          329                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          140                       # number of overall misses
system.cpu.l2cache.overall_misses::total          469                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4840000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      4840000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     27581000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     27581000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      7956500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total      7956500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     27581000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     12796500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     40377500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     27581000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     12796500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     40377500                       # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks           17                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total           17                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           50                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           50                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          332                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          332                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           90                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total           90                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          332                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          140                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          472                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          332                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          140                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          472                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.990964                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.990964                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.990964                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.993644                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.990964                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.993644                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        96800                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        96800                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83832.826748                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83832.826748                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83832.826748                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 86092.750533                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83832.826748                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 86092.750533                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           50                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          329                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          329                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           90                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total           90                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          329                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          140                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          469                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          329                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          140                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          469                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4340000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4340000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     24291000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     24291000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7056500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      7056500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24291000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11396500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     35687500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24291000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11396500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     35687500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.990964                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.990964                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.990964                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.993644                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.990964                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.993644                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        86800                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        86800                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73832.826748                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73832.826748                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73832.826748                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76092.750533                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73832.826748                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76092.750533                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests          489                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests           17                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp           422                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           50                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           50                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          332                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq           90                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          681                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          280                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               961                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22336                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8960                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              31296                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples          472                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                472    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            472                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         261500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        498000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        210000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests           469                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED     24405000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                419                       # Transaction distribution
system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           419                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          938                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    938                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30016                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   30016                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               469                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     469    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 469                       # Request fanout histogram
system.membus.reqLayer0.occupancy              581000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
system.membus.respLayer1.occupancy            2488500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             10.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
