
---------- Begin Simulation Statistics ----------
host_inst_rate                                3981428                       # Simulator instruction rate (inst/s)
host_mem_usage                                 333640                       # Number of bytes of host memory used
host_seconds                                    13.09                       # Real time elapsed on the host
host_tick_rate                             2017840381                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    52100192                       # Number of instructions simulated
sim_seconds                                  0.026406                       # Number of seconds simulated
sim_ticks                                 26405524500                       # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses::0       100461                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       100461                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits::0         95296                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        95296                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_rate::0     0.051413                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::0         5165                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total         5165                       # number of LoadLockedReq misses
system.cpu.dcache.ReadReq_accesses::0         7831528                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      7831528                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_hits::0             7594963                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7594963                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_rate::0       0.030207                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::0            236565                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        236565                       # number of ReadReq misses
system.cpu.dcache.StoreCondReq_accesses::0       100460                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       100460                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::0         100460                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       100460                       # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses::0        6676897                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6676897                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_hits::0            6504656                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        6504656                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_rate::0      0.025797                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::0           172241                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       172241                       # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                  34.690601                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses::0         14508425                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     14508425                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.cpu.dcache.demand_hits::0             14099619                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         14099619                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate::0        0.028177                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.dcache.demand_misses::0             408806                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         408806                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0            511.737186                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.999487                       # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses::0        14508425                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     14508425                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits::0            14099619                       # number of overall hits
system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
system.cpu.dcache.overall_hits::total        14099619                       # number of overall hits
system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate::0       0.028177                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.dcache.overall_misses::0            408806                       # number of overall misses
system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
system.cpu.dcache.overall_misses::total        408806                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses               0                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                 411623                       # number of replacements
system.cpu.dcache.sampled_refs                 412135                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                511.737186                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 14297211                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle               21760500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                   381909                       # number of writebacks
system.cpu.dtb.accesses                      15532989                       # DTB accesses
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries                     2238                       # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               33670                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits                          15527459                       # DTB hits
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.misses                            5530                       # DTB misses
system.cpu.dtb.perms_faults                       255                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults                    767                       # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses                  8743878                       # DTB read accesses
system.cpu.dtb.read_hits                      8739345                       # DTB read hits
system.cpu.dtb.read_misses                       4533                       # DTB read misses
system.cpu.dtb.write_accesses                 6789111                       # DTB write accesses
system.cpu.dtb.write_hits                     6788114                       # DTB write hits
system.cpu.dtb.write_misses                       997                       # DTB write misses
system.cpu.icache.ReadReq_accesses::0        41566870                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     41566870                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_hits::0            41133444                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        41133444                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_rate::0       0.010427                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::0            433426                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        433426                       # number of ReadReq misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                  94.903257                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses::0         41566870                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     41566870                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.cpu.icache.demand_hits::0             41133444                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         41133444                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate::0        0.010427                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu.icache.demand_misses::0             433426                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         433426                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0            476.427204                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.930522                       # Average percentage of cache occupancy
system.cpu.icache.overall_accesses::0        41566870                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     41566870                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits::0            41133444                       # number of overall hits
system.cpu.icache.overall_hits::1                   0                       # number of overall hits
system.cpu.icache.overall_hits::total        41133444                       # number of overall hits
system.cpu.icache.overall_miss_latency              0                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate::0       0.010427                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu.icache.overall_misses::0            433426                       # number of overall misses
system.cpu.icache.overall_misses::1                 0                       # number of overall misses
system.cpu.icache.overall_misses::total        433426                       # number of overall misses
system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses               0                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                 432913                       # number of replacements
system.cpu.icache.sampled_refs                 433425                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                476.427204                       # Cycle average of tags in use
system.cpu.icache.total_refs                 41133444                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle             4575402000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                    33681                       # number of writebacks
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.itb.accesses                      41567997                       # DTB accesses
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries                     1478                       # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               33670                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits                          41565169                       # DTB hits
system.cpu.itb.inst_accesses                 41567997                       # ITB inst accesses
system.cpu.itb.inst_hits                     41565169                       # ITB inst hits
system.cpu.itb.inst_misses                       2828                       # ITB inst misses
system.cpu.itb.misses                            2828                       # DTB misses
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.numCycles                         52811050                       # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.num_busy_cycles                   52811050                       # Number of busy cycles
system.cpu.num_conditional_control_insts      7028967                       # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses                   6058                       # Number of float alu accesses
system.cpu.num_fp_insts                          6058                       # number of float instructions
system.cpu.num_fp_register_reads                 4226                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                1834                       # number of times the floating registers were written
system.cpu.num_func_calls                     1109362                       # number of times a function call or return occured
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_insts                         52100192                       # Number of instructions executed
system.cpu.num_int_alu_accesses              42511691                       # Number of integer alu accesses
system.cpu.num_int_insts                     42511691                       # number of integer instructions
system.cpu.num_int_register_reads           131109932                       # number of times the integer registers were read
system.cpu.num_int_register_writes           34554918                       # number of times the integer registers were written
system.cpu.num_load_insts                     9209160                       # Number of load instructions
system.cpu.num_mem_refs                      16296226                       # number of memory refs
system.cpu.num_store_insts                    7087066                       # Number of store instructions
system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                    0                       # number of overall misses
system.iocache.overall_misses::total                0                       # number of overall misses
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.replacements                         0                       # number of replacements
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.writebacks                           0                       # number of writebacks
system.l2c.ReadExReq_accesses::0               170405                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           170405                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_hits::0                    60553                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                60553                       # number of ReadExReq hits
system.l2c.ReadExReq_miss_rate::0            0.644652                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0                 109852                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             109852                       # number of ReadExReq misses
system.l2c.ReadReq_accesses::0                 673057                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                   6142                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             679199                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_hits::0                     651904                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                       6117                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 658021                       # number of ReadReq hits
system.l2c.ReadReq_miss_rate::0              0.031428                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.004070                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.035499                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0                    21153                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                       25                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                21178                       # number of ReadReq misses
system.l2c.UpgradeReq_accesses::0                1836                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            1836                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_hits::0                      17                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  17                       # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_rate::0           0.990741                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0                  1819                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1819                       # number of UpgradeReq misses
system.l2c.Writeback_accesses::0               415590                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           415590                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0                   415590                       # number of Writeback hits
system.l2c.Writeback_hits::total               415590                       # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.avg_refs                          6.746349                       # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses::0                  843462                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                    6142                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              849604                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total            0                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
system.l2c.demand_hits::0                      712457                       # number of demand (read+write) hits
system.l2c.demand_hits::1                        6117                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  718574                       # number of demand (read+write) hits
system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0               0.155318                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.004070                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.159389                       # miss rate for demand accesses
system.l2c.demand_misses::0                    131005                       # number of demand (read+write) misses
system.l2c.demand_misses::1                        25                       # number of demand (read+write) misses
system.l2c.demand_misses::total                131030                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total             0                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.occ_blocks::0                  5042.918302                       # Average occupied blocks per context
system.l2c.occ_blocks::1                 31264.310783                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.076949                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.477056                       # Average percentage of cache occupancy
system.l2c.overall_accesses::0                 843462                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                   6142                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             849604                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total            0                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.l2c.overall_hits::0                     712457                       # number of overall hits
system.l2c.overall_hits::1                       6117                       # number of overall hits
system.l2c.overall_hits::total                 718574                       # number of overall hits
system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
system.l2c.overall_miss_rate::0              0.155318                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.004070                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.159389                       # miss rate for overall accesses
system.l2c.overall_misses::0                   131005                       # number of overall misses
system.l2c.overall_misses::1                       25                       # number of overall misses
system.l2c.overall_misses::total               131030                       # number of overall misses
system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1                0                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total            0                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.replacements                         97025                       # number of replacements
system.l2c.sampled_refs                        129753                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                     36307.229085                       # Cycle average of tags in use
system.l2c.total_refs                          875359                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                           90930                       # number of writebacks

---------- End Simulation Statistics   ----------
