
---------- Begin Simulation Statistics ----------
host_inst_rate                                 200493                       # Simulator instruction rate (inst/s)
host_mem_usage                                 217108                       # Number of bytes of host memory used
host_seconds                                   396.98                       # Real time elapsed on the host
host_tick_rate                               64404396                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    79591756                       # Number of instructions simulated
sim_seconds                                  0.025567                       # Number of seconds simulated
sim_ticks                                 25567234000                       # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits                  7985382                       # Number of BTB hits
system.cpu.BPredUnit.BTBLookups              13917590                       # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect               35809                       # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect             450273                       # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted           10401089                       # Number of conditional branches predicted
system.cpu.BPredUnit.lookups                 16008370                       # Number of BP lookups
system.cpu.BPredUnit.usedRAS                  1909965                       # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts            354109                       # The number of times a branch was mispredicted
system.cpu.commit.branches                   13754477                       # Number of branches committed
system.cpu.commit.bw_lim_events               3841167                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts       88340672                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts         6568373                       # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples     49654357                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.779112                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.457508                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     22596462     45.51%     45.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      9701520     19.54%     65.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4636863      9.34%     74.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2945074      5.93%     80.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2498358      5.03%     85.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1627223      3.28%     88.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       982509      1.98%     90.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       825181      1.66%     92.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      3841167      7.74%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     49654357                       # Number of insts commited each cycle
system.cpu.commit.count                      88340672                       # Number of instructions committed
system.cpu.commit.fp_insts                     267754                       # Number of committed floating point instructions.
system.cpu.commit.function_calls              1661057                       # Number of function calls committed.
system.cpu.commit.int_insts                  77942044                       # Number of committed integer instructions.
system.cpu.commit.loads                      20276638                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.refs                       34890015                       # Number of memory references committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
system.cpu.committedInsts_total              79591756                       # Number of Instructions Simulated
system.cpu.cpi                               0.642459                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.642459                       # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses           43                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits               43                       # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses           20559608                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 26896.308306                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20641.135763                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits               20399248                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency     4313092000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.007800                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses               160360                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits             98657                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency   1273620000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.003001                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses           61703                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 32551.967827                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33106.498522                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits              13581325                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency   33595323500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.070624                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses             1032052                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits           888604                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency   4749061000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.009816                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses         143448                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets        27000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                 165.637097                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        27000                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses            35172985                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 31791.373703                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 29357.307544                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                33980573                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency     37908415500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.033901                       # miss rate for demand accesses
system.cpu.dcache.demand_misses               1192412                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits             987261                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency   6022681000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.005833                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses           205151                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0           4076.644885                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.995275                       # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses           35172985                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 31791.373703                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 29357.307544                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits               33980573                       # number of overall hits
system.cpu.dcache.overall_miss_latency    37908415500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.033901                       # miss rate for overall accesses
system.cpu.dcache.overall_misses              1192412                       # number of overall misses
system.cpu.dcache.overall_mshr_hits            987261                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency   6022681000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.005833                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses          205151                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                 201055                       # number of replacements
system.cpu.dcache.sampled_refs                 205151                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               4076.644885                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 33980616                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle              177876000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                   161514                       # number of writebacks
system.cpu.decode.BlockedCycles               2460997                       # Number of cycles decode is blocked
system.cpu.decode.BranchMispred                 97681                       # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved              3594435                       # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts              100084760                       # Number of instructions handled by decode
system.cpu.decode.IdleCycles                 27762644                       # Number of cycles decode is idle
system.cpu.decode.RunCycles                  19396266                       # Number of cycles decode is running
system.cpu.decode.SquashCycles                1063649                       # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts                276834                       # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles                 34450                       # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses                 36973918                       # DTB accesses
system.cpu.dtb.data_acv                            20                       # DTB access violations
system.cpu.dtb.data_hits                     36772232                       # DTB hits
system.cpu.dtb.data_misses                     201686                       # DTB misses
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.read_accesses                 21748478                       # DTB read accesses
system.cpu.dtb.read_acv                            19                       # DTB read access violations
system.cpu.dtb.read_hits                     21577330                       # DTB read hits
system.cpu.dtb.read_misses                     171148                       # DTB read misses
system.cpu.dtb.write_accesses                15225440                       # DTB write accesses
system.cpu.dtb.write_acv                            1                       # DTB write access violations
system.cpu.dtb.write_hits                    15194902                       # DTB write hits
system.cpu.dtb.write_misses                     30538                       # DTB write misses
system.cpu.fetch.Branches                    16008370                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                  13158718                       # Number of cache lines fetched
system.cpu.fetch.Cycles                      19591284                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes                152584                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                      101571141                       # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles                26109                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles                  555760                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.313064                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles           13158718                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches            9895347                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        1.986354                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples           50718006                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.002664                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.959146                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 31126722     61.37%     61.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1893724      3.73%     65.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1511025      2.98%     68.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1863843      3.67%     71.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  3852588      7.60%     79.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1892655      3.73%     83.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   670633      1.32%     84.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1088115      2.15%     86.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  6818701     13.44%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             50718006                       # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads                    235864                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   240719                       # number of floating regfile writes
system.cpu.icache.ReadReq_accesses           13158718                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency  9582.065520                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency  6079.057819                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits               13070837                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency      842081500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.006679                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                87881                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits              2823                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency    517072500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.006464                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses           85058                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                 153.671503                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses            13158718                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency  9582.065520                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency  6079.057819                       # average overall mshr miss latency
system.cpu.icache.demand_hits                13070837                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency       842081500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.006679                       # miss rate for demand accesses
system.cpu.icache.demand_misses                 87881                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits               2823                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency    517072500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.006464                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses            85058                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0           1916.040169                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.935566                       # Average percentage of cache occupancy
system.cpu.icache.overall_accesses           13158718                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency  9582.065520                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency  6079.057819                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits               13070837                       # number of overall hits
system.cpu.icache.overall_miss_latency      842081500                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.006679                       # miss rate for overall accesses
system.cpu.icache.overall_misses                87881                       # number of overall misses
system.cpu.icache.overall_mshr_hits              2823                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency    517072500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.006464                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses           85058                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                  83010                       # number of replacements
system.cpu.icache.sampled_refs                  85057                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse               1916.040169                       # Cycle average of tags in use
system.cpu.icache.total_refs                 13070837                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                          416464                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts               395795                       # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches                 14700654                       # Number of branches executed
system.cpu.iew.exec_nop                       9311504                       # number of nop insts executed
system.cpu.iew.exec_rate                     1.660486                       # Inst execution rate
system.cpu.iew.exec_refs                     36975872                       # number of memory reference insts executed
system.cpu.iew.exec_stores                   15225695                       # Number of stores executed
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.iewBlockCycles                  429488                       # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts              22491432                       # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts               4739                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts            365032                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts             15781594                       # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts            97321762                       # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts              21750177                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            569916                       # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts              84908070                       # Number of executed instructions
system.cpu.iew.iewIQFullEvents                  23208                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents                  1058                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles                1063649                       # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles                 29880                       # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked            30                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads          1016178                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses         1322                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation         6217                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads         1472                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads      2214794                       # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores      1168217                       # Number of stores squashed
system.cpu.iew.memOrderViolationEvents           6217                       # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect       133065                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect         262730                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers                  40429267                       # num instructions consuming a value
system.cpu.iew.wb_count                      84366668                       # cumulative count of insts written-back
system.cpu.iew.wb_fanout                     0.767758                       # average fanout of values written-back
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers                  31039892                       # num instructions producing a value
system.cpu.iew.wb_rate                       1.649898                       # insts written-back per cycle
system.cpu.iew.wb_sent                       84634554                       # cumulative count of insts sent to commit
system.cpu.int_regfile_reads                112360564                       # number of integer regfile reads
system.cpu.int_regfile_writes                55786710                       # number of integer regfile writes
system.cpu.ipc                               1.556519                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.556519                       # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              47939957     56.08%     56.08% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                43473      0.05%     56.14% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd              122672      0.14%     56.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                  87      0.00%     56.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt              123541      0.14%     56.42% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 52      0.00%     56.42% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv               38558      0.05%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.47% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             21877865     25.59%     82.06% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            15331781     17.94%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               85477986                       # Type of FU issued
system.cpu.iq.fp_alu_accesses                  297653                       # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads              595198                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses       282834                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes             410179                       # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt                     1052413                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.012312                       # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   99607      9.46%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 509872     48.45%     57.91% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                442934     42.09%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses               86232746                       # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads          222155982                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses     84083834                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes          95743057                       # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded                   88005519                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                  85477986                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded                4739                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined         8137764                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued             24789                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved            156                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined      4541669                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples      50718006                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.685358                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.886898                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            18797586     37.06%     37.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            10551252     20.80%     57.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7740515     15.26%     73.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             3878311      7.65%     80.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             5219123     10.29%     91.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1973435      3.89%     94.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1302970      2.57%     97.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              789228      1.56%     99.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              465586      0.92%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        50718006                       # Number of insts issued each cycle
system.cpu.iq.rate                           1.671631                       # Inst issue rate
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.fetch_accesses                13184827                       # ITB accesses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_hits                    13158718                       # ITB hits
system.cpu.itb.fetch_misses                     26109                       # ITB misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses          143470                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.090113                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31253.171300                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits               12057                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency   4516151000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate       0.915962                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses            131413                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency   4107073000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.915962                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses       131413                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses            146739                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34243.505155                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31097.285223                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                103089                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency    1494729000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.297467                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses               43650                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency   1357396500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.297467                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses          43650                       # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses          161514                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits              161514                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.755289                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses             290209                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34335.524925                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31214.302851                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                 115146                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency     6010880000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.603231                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses               175063                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency   5464469500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.603231                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses          175063                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0          2983.162459                       # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1         15807.936259                       # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0            0.091039                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1            0.482420                       # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses            290209                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34335.524925                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31214.302851                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                115146                       # number of overall hits
system.cpu.l2cache.overall_miss_latency    6010880000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.603231                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses              175063                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency   5464469500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.603231                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses         175063                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                148713                       # number of replacements
system.cpu.l2cache.sampled_refs                174075                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse             18791.098718                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  131477                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                  120512                       # number of writebacks
system.cpu.memDep0.conflictingLoads           5725093                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          4370544                       # Number of conflicting stores.
system.cpu.memDep0.insertedLoads             22491432                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            15781594                       # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads                   37825                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.numCycles                         51134470                       # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.rename.BlockCycles                 1389160                       # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
system.cpu.rename.IQFullEvents                  11049                       # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles                 28153155                       # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents                921609                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents                    39                       # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups             119490611                       # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts               99297358                       # Number of instructions processed by rename
system.cpu.rename.RenamedOperands            59691366                       # Number of destination operands rename has renamed
system.cpu.rename.RunCycles                  19024050                       # Number of cycles rename is running
system.cpu.rename.SquashCycles                1063649                       # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles               1018413                       # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps                  7144485                       # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups            428893                       # Number of floating rename lookups
system.cpu.rename.int_rename_lookups        119061718                       # Number of integer rename lookups
system.cpu.rename.serializeStallCycles          69579                       # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts               5023                       # count of serializing insts renamed
system.cpu.rename.skidInsts                   2212492                       # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts           5020                       # count of temporary serializing insts renamed
system.cpu.rob.rob_reads                    139404893                       # The number of ROB reads
system.cpu.rob.rob_writes                   190882895                       # The number of ROB writes
system.cpu.timesIdled                           12185                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls                 4583                       # Number of system calls

---------- End Simulation Statistics   ----------
