
---------- Begin Simulation Statistics ----------
host_inst_rate                                 123746                       # Simulator instruction rate (inst/s)
host_mem_usage                                 223548                       # Number of bytes of host memory used
host_seconds                                 15235.59                       # Real time elapsed on the host
host_tick_rate                               57045555                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                  1885343131                       # Number of instructions simulated
sim_seconds                                  0.869123                       # Number of seconds simulated
sim_ticks                                869122614500                       # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits                306717434                       # Number of BTB hits
system.cpu.BPredUnit.BTBLookups             430322374                       # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect             4126641                       # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect           38509304                       # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted          414146262                       # Number of conditional branches predicted
system.cpu.BPredUnit.lookups                547821195                       # Number of BP lookups
system.cpu.BPredUnit.usedRAS                 52353944                       # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts          44034324                       # The number of times a branch was mispredicted
system.cpu.commit.branches                  291352101                       # Number of branches committed
system.cpu.commit.bw_lim_events              58391194                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts     1885354147                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls          211788                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts      1159545124                       # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples   1569639960                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.201138                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.832019                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    741490044     47.24%     47.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    428382990     27.29%     74.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    179836279     11.46%     85.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     75300710      4.80%     90.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     51350508      3.27%     94.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     14363186      0.92%     94.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     16626388      1.06%     96.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3898661      0.25%     96.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     58391194      3.72%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1569639960                       # Number of insts commited each cycle
system.cpu.commit.count                    1885354147                       # Number of instructions committed
system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
system.cpu.commit.int_insts                1660589568                       # Number of committed integer instructions.
system.cpu.commit.loads                     631390738                       # Number of loads committed
system.cpu.commit.membars                        9986                       # Number of memory barriers committed
system.cpu.commit.refs                      908389591                       # Number of memory references committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.committedInsts                  1885343131                       # Number of Instructions Simulated
system.cpu.committedInsts_total            1885343131                       # Number of Instructions Simulated
system.cpu.cpi                               0.921978                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.921978                       # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses        16563                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency        36000                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_hits            16560                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency       108000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate     0.000181                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.ReadReq_accesses          719743327                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 34434.084402                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34107.861435                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits              717811546                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency    66519110000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.002684                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses              1931781                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits            469020                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency  49891649500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.002032                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses         1462761                       # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses         13541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits             13541                       # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses         276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 35082.855730                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32466.582320                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits             276128872                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency   28305058500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.002913                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses              806806                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits           734090                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency   2360840000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.000263                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses          72716                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets        14000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                 647.337915                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        56000                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses           996679005                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 34625.216763                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34030.134935                       # average overall mshr miss latency
system.cpu.dcache.demand_hits               993940418                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency     94824168500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.002748                       # miss rate for demand accesses
system.cpu.dcache.demand_misses               2738587                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits            1203110                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency  52252489500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.001541                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses          1535477                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0           4094.913997                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.999735                       # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses          996679005                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 34625.216763                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34030.134935                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits              993940418                       # number of overall hits
system.cpu.dcache.overall_miss_latency    94824168500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.002748                       # miss rate for overall accesses
system.cpu.dcache.overall_misses              2738587                       # number of overall misses
system.cpu.dcache.overall_mshr_hits           1203110                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency  52252489500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.001541                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses         1535477                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                1531378                       # number of replacements
system.cpu.dcache.sampled_refs                1535474                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               4094.913997                       # Cycle average of tags in use
system.cpu.dcache.total_refs                993970537                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle              333433000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                   106994                       # number of writebacks
system.cpu.decode.BlockedCycles             146923379                       # Number of cycles decode is blocked
system.cpu.decode.BranchMispred                 10558                       # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved             87779592                       # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts             3387651447                       # Number of instructions handled by decode
system.cpu.decode.IdleCycles                772293047                       # Number of cycles decode is idle
system.cpu.decode.RunCycles                 647864668                       # Number of cycles decode is running
system.cpu.decode.SquashCycles              162682073                       # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts                 19702                       # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles               2558864                       # Number of cycles decode is unblocking
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.fetch.Branches                   547821195                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                 367105078                       # Number of cache lines fetched
system.cpu.fetch.Cycles                     665860659                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes              19277172                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                     2595469256                       # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles              1285897                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles                45421845                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.315158                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles          367105078                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches          359071378                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        1.493155                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples         1732322031                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.998705                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.975519                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0               1066497771     61.56%     61.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 40398523      2.33%     63.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                108471254      6.26%     70.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 62827060      3.63%     73.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 83015606      4.79%     78.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 56381906      3.25%     81.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 33027713      1.91%     83.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 49177401      2.84%     86.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                232524797     13.42%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1732322031                       # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads                  71543247                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 49528299                       # number of floating regfile writes
system.cpu.icache.ReadReq_accesses          367105078                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency  9381.938291                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency  6050.959331                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits              367080252                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency      232916000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000068                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                24826                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits               434                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency    147595000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000066                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses           24392                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs               15051.057895                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses           367105078                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency  9381.938291                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency  6050.959331                       # average overall mshr miss latency
system.cpu.icache.demand_hits               367080252                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency       232916000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000068                       # miss rate for demand accesses
system.cpu.icache.demand_misses                 24826                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                434                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency    147595000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000066                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses            24392                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0           1541.532802                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.752702                       # Average percentage of cache occupancy
system.cpu.icache.overall_accesses          367105078                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency  9381.938291                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency  6050.959331                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits              367080252                       # number of overall hits
system.cpu.icache.overall_miss_latency      232916000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000068                       # miss rate for overall accesses
system.cpu.icache.overall_misses                24826                       # number of overall misses
system.cpu.icache.overall_mshr_hits               434                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency    147595000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000066                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses           24392                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                  22805                       # number of replacements
system.cpu.icache.sampled_refs                  24389                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse               1541.532802                       # Cycle average of tags in use
system.cpu.icache.total_refs                367080251                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                         5923199                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts             46494560                       # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches                358605233                       # Number of branches executed
system.cpu.iew.exec_nop                       1350849                       # number of nop insts executed
system.cpu.iew.exec_rate                     1.388402                       # Inst execution rate
system.cpu.iew.exec_refs                   1176236253                       # number of memory reference insts executed
system.cpu.iew.exec_stores                  407328146                       # Number of stores executed
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.iewBlockCycles                11036637                       # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts             946299703                       # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts             229756                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts           7912481                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts            478952600                       # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts          3044913804                       # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts             768908107                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          79753358                       # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts            2413383308                       # Number of executed instructions
system.cpu.iew.iewIQFullEvents               10292588                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents                   325                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles              162682073                       # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles              10344235                       # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked            25                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads         36704375                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses         1640                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation      2659902                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads           95                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads    314908964                       # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores    201953747                       # Number of stores squashed
system.cpu.iew.memOrderViolationEvents        2659902                       # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect      7823566                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect       38670994                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers                2464876715                       # num instructions consuming a value
system.cpu.iew.wb_count                    2378604713                       # cumulative count of insts written-back
system.cpu.iew.wb_fanout                     0.531444                       # average fanout of values written-back
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers                1309943730                       # num instructions producing a value
system.cpu.iew.wb_rate                       1.368394                       # insts written-back per cycle
system.cpu.iew.wb_sent                     2386121679                       # cumulative count of insts sent to commit
system.cpu.int_regfile_reads               5694776843                       # number of integer regfile reads
system.cpu.int_regfile_writes              1751148886                       # number of integer regfile writes
system.cpu.ipc                               1.084624                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.084624                       # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1205851764     48.37%     48.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult             11238449      0.45%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                 8633      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     48.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     48.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     48.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         6876474      0.28%     49.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         5501201      0.22%     49.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     49.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       23385525      0.94%     50.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     50.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     50.31% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            797167964     31.97%     82.28% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           441731367     17.72%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2493136666                       # Type of FU issued
system.cpu.iq.fp_alu_accesses                66051736                       # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads           126602345                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses     59166260                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes           83365842                       # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt                    86890569                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.034852                       # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                     482      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  24113      0.03%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.03% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               55140629     63.46%     63.49% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              31725345     36.51%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses             2513975499                       # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads         6687198013                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses   2319438453                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes        4119676810                       # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded                 3043320801                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                2493136666                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded              242154                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined      1158104053                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued           8314426                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved          30366                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined   1709199023                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples    1732322031                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.439188                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.577350                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           668978981     38.62%     38.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           360959007     20.84%     59.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           315091353     18.19%     77.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           182075740     10.51%     88.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           118045462      6.81%     94.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            56433729      3.26%     98.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            19322035      1.12%     99.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             5840762      0.34%     99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             5574962      0.32%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1732322031                       # Number of insts issued each cycle
system.cpu.iq.rate                           1.434284                       # Inst issue rate
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses           72713                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.933176                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.414866                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits                6629                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency   2279827500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate       0.908833                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses             66084                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency   2048697500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908833                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses        66084                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses           1487150                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34256.254935                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.334021                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                 72547                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency   48459001000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.951217                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses             1414603                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits               23                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency  43852452500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.951202                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses        1414580                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses              3                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_hits                  2                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_miss_rate      0.333333                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.333333                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses          106994                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits              106994                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.053475                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses            1559863                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34267.085819                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.382261                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                  79176                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency    50738828500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.949242                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses              1480687                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                23                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency  45901150000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.949227                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses         1480664                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0         28976.452018                       # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1          2993.413242                       # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0            0.884291                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1            0.091352                       # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses           1559863                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34267.085819                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.382261                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                 79176                       # number of overall hits
system.cpu.l2cache.overall_miss_latency   50738828500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.949242                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses             1480687                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits               23                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency  45901150000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.949227                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses        1480664                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements               1479500                       # number of replacements
system.cpu.l2cache.sampled_refs               1512220                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse             31969.865261                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                   80866                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                   66099                       # number of writebacks
system.cpu.memDep0.conflictingLoads          75887530                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         97070199                       # Number of conflicting stores.
system.cpu.memDep0.insertedLoads            946299703                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           478952600                       # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads              3932819871                       # number of misc regfile reads
system.cpu.misc_regfile_writes               13780014                       # number of misc regfile writes
system.cpu.numCycles                       1738245230                       # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.rename.BlockCycles                26815429                       # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps            1523726473                       # Number of HB maps that are committed
system.cpu.rename.IQFullEvents               13358705                       # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles                804669593                       # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents              12419294                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups            8858159876                       # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts             3258876297                       # Number of instructions processed by rename
system.cpu.rename.RenamedOperands          2595747724                       # Number of destination operands rename has renamed
system.cpu.rename.RunCycles                 616670755                       # Number of cycles rename is running
system.cpu.rename.SquashCycles              162682073                       # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles              32941123                       # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps               1072021248                       # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups         417025150                       # Number of floating rename lookups
system.cpu.rename.int_rename_lookups       8441134726                       # Number of integer rename lookups
system.cpu.rename.serializeStallCycles       88543058                       # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts            8500262                       # count of serializing insts renamed
system.cpu.rename.skidInsts                  93807403                       # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts         250407                       # count of temporary serializing insts renamed
system.cpu.rob.rob_reads                   4556129692                       # The number of ROB reads
system.cpu.rob.rob_writes                  6252480772                       # The number of ROB writes
system.cpu.timesIdled                         1346475                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls                 1411                       # Number of system calls

---------- End Simulation Statistics   ----------
