
---------- Begin Simulation Statistics ----------
host_inst_rate                                 121226                       # Simulator instruction rate (inst/s)
host_mem_usage                                 203988                       # Number of bytes of host memory used
host_seconds                                     0.05                       # Real time elapsed on the host
host_tick_rate                              446414211                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                        5827                       # Number of instructions simulated
sim_seconds                                  0.000022                       # Number of seconds simulated
sim_ticks                                    21538000                       # Number of ticks simulated
system.cpu.activity                         13.954082                       # Percentage of cycles cpu is active
system.cpu.agen_unit.agens                       2404                       # Number of Address Generations
system.cpu.branch_predictor.BTBHitPct       14.054054                       # BTB Hit Percentage
system.cpu.branch_predictor.BTBHits                26                       # Number of BTB hits
system.cpu.branch_predictor.BTBLookups            185                       # Number of BTB lookups
system.cpu.branch_predictor.RASInCorrect           30                       # Number of incorrect RAS predictions.
system.cpu.branch_predictor.condIncorrect          844                       # Number of conditional branches incorrect
system.cpu.branch_predictor.condPredicted          778                       # Number of conditional branches predicted
system.cpu.branch_predictor.lookups              1066                       # Number of BP lookups
system.cpu.branch_predictor.predictedNotTaken          949                       # Number of Branches Predicted As Not Taken (False).
system.cpu.branch_predictor.predictedTaken          117                       # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.usedRAS                86                       # Number of times the RAS was used to get a target.
system.cpu.comBranches                            916                       # Number of Branches instructions committed
system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
system.cpu.comInts                               2155                       # Number of Integer instructions committed
system.cpu.comLoads                              1164                       # Number of Load instructions committed
system.cpu.comNonSpec                              10                       # Number of Non-Speculative instructions committed
system.cpu.comNops                                657                       # Number of Nop instructions committed
system.cpu.comStores                              925                       # Number of Store instructions committed
system.cpu.committedInsts                        5827                       # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total                  5827                       # Number of Instructions Simulated (Total)
system.cpu.contextSwitches                          1                       # Number of context switches
system.cpu.cpi                               7.392655                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi_total                         7.392655                       # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses               1164                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56676.136364                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53678.160920                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits                   1076                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency        4987500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.075601                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                   88                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits                 1                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency      4670000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.074742                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses              87                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses               925                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55935.483871                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53637.254902                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits                   832                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency       5202000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.100541                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                  93                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits               42                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency      2735500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.055135                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses             51                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets        53100                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                  13.826087                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               5                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       265500                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses                2089                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56295.580110                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53663.043478                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                    1908                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency        10189500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.086644                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                   181                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                 43                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency      7405500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.066060                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses              138                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0             89.067186                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.021745                       # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses               2089                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56295.580110                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53663.043478                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits                   1908                       # number of overall hits
system.cpu.dcache.overall_miss_latency       10189500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.086644                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                  181                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                43                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency      7405500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.066060                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses             138                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                 89.067186                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     1908                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                        0                       # number of writebacks
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.execution_unit.executions             3261                       # Number of Instructions Executed.
system.cpu.execution_unit.mispredictPct     92.139738                       # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.mispredicted            844                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted                72                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predictedNotTakenIncorrect          812                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.predictedTakenIncorrect           32                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.icache.ReadReq_accesses                853                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55527.559055                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53156.739812                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits                    472                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency       21156000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.446659                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  381                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits                62                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency     16957000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.373974                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             319                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets        31000                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                   1.479624                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets        62000                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses                 853                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 55527.559055                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53156.739812                       # average overall mshr miss latency
system.cpu.icache.demand_hits                     472                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency        21156000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.446659                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   381                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                 62                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency     16957000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.373974                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              319                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0            145.295903                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.070945                       # Average percentage of cache occupancy
system.cpu.icache.overall_accesses                853                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55527.559055                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53156.739812                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits                    472                       # number of overall hits
system.cpu.icache.overall_miss_latency       21156000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.446659                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  381                       # number of overall misses
system.cpu.icache.overall_mshr_hits                62                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency     16957000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.373974                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             319                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                     13                       # number of replacements
system.cpu.icache.sampled_refs                    319                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                145.295903                       # Cycle average of tags in use
system.cpu.icache.total_refs                      472                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                           37066                       # Number of cycles cpu's stages were not processed
system.cpu.ipc                               0.135269                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.ipc_total                         0.135269                       # IPC: Total IPC of All Threads
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses              51                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52470.588235                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40235.294118                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency      2676000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses                51                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency      2052000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses           51                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses               406                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52357.673267                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40153.465347                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency      21152500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.995074                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                 404                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency     16222000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.995074                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses            404                       # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.004950                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses                457                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52370.329670                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40162.637363                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency       23828500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.995624                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                  455                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency     18274000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.995624                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses             455                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0           202.151439                       # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0            0.006169                       # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses               457                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52370.329670                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40162.637363                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                     2                       # number of overall hits
system.cpu.l2cache.overall_miss_latency      23828500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.995624                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                 455                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency     18274000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.995624                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses            455                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.sampled_refs                   404                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse               202.151439                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.mult_div_unit.divides                    1                       # Number of Divide Operations Executed
system.cpu.mult_div_unit.multiplies                 3                       # Number of Multipy Operations Executed
system.cpu.numCycles                            43077                       # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.regfile_manager.regFileAccesses        10004                       # Number of Total Accesses (Read+Write) to the Register File
system.cpu.regfile_manager.regFileReads          6594                       # Number of Reads from Register File
system.cpu.regfile_manager.regFileWrites         3410                       # Number of Writes to Register File
system.cpu.regfile_manager.regForwards           1378                       # Number of Registers Read Through Forwarding Logic
system.cpu.runCycles                             6011                       # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
system.cpu.stage0.idleCycles                    39203                       # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles                      3874                       # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization                8.993198                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles                    40159                       # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles                      2918                       # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization                6.773916                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles                    40245                       # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles                      2832                       # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization                6.574274                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles                    41757                       # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles                      1320                       # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization                3.064280                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles                    39874                       # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles                      3203                       # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization                7.435522                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.threadCycles                         10193                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.timesIdled                             427                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls                    8                       # Number of system calls

---------- End Simulation Statistics   ----------
