
---------- Begin Simulation Statistics ----------
host_inst_rate                                  99680                       # Simulator instruction rate (inst/s)
host_mem_usage                                 212240                       # Number of bytes of host memory used
host_seconds                                     0.10                       # Real time elapsed on the host
host_tick_rate                              115331857                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                        9809                       # Number of instructions simulated
sim_seconds                                  0.000011                       # Number of seconds simulated
sim_ticks                                    11371000                       # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits                      931                       # Number of BTB hits
system.cpu.BPredUnit.BTBLookups                  2531                       # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect                485                       # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted               2758                       # Number of conditional branches predicted
system.cpu.BPredUnit.lookups                     2758                       # Number of BP lookups
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts               485                       # The number of times a branch was mispredicted
system.cpu.commit.branches                       1214                       # Number of branches committed
system.cpu.commit.bw_lim_events                   141                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts           9809                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts            9222                       # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples        11809                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.830638                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.597584                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0         8189     69.35%     69.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         1225     10.37%     79.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2          582      4.93%     84.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          958      8.11%     92.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          396      3.35%     96.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5          132      1.12%     97.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6          128      1.08%     98.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7           58      0.49%     98.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8          141      1.19%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        11809                       # Number of insts commited each cycle
system.cpu.commit.count                          9809                       # Number of instructions committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.int_insts                      9714                       # Number of committed integer instructions.
system.cpu.commit.loads                          1056                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.refs                           1990                       # Number of memory references committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.committedInsts                        9809                       # Number of Instructions Simulated
system.cpu.committedInsts_total                  9809                       # Number of Instructions Simulated
system.cpu.cpi                               2.318585                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.318585                       # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses               1531                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 34504.424779                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35141.791045                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits                   1418                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency        3899000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.073808                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                  113                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits                46                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency      2354500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.043762                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses              67                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses               934                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 34084.664537                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency        36000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits                   621                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency      10668500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.335118                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                 313                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits              236                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency      2772000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.082441                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses             77                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                  14.258741                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses                2465                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 34196.009390                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35600.694444                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                    2039                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency        14567500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.172819                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                   426                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                282                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency      5126500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.058418                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses              144                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0             85.873455                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.020965                       # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses               2465                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 34196.009390                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35600.694444                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits                   2039                       # number of overall hits
system.cpu.dcache.overall_miss_latency       14567500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.172819                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                  426                       # number of overall misses
system.cpu.dcache.overall_mshr_hits               282                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency      5126500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.058418                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses             144                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.sampled_refs                    143                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                 85.873455                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     2039                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                        0                       # number of writebacks
system.cpu.decode.BlockedCycles                  1369                       # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts                  22088                       # Number of instructions handled by decode
system.cpu.decode.IdleCycles                     7085                       # Number of cycles decode is idle
system.cpu.decode.RunCycles                      3278                       # Number of cycles decode is running
system.cpu.decode.SquashCycles                   1477                       # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles                    77                       # Number of cycles decode is unblocking
system.cpu.fetch.Branches                        2758                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                      1703                       # Number of cache lines fetched
system.cpu.fetch.Cycles                          3590                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes                   238                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                          12847                       # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles                     497                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.121268                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles               1703                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches                931                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        0.564877                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples              13286                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.734834                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.110520                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                     9786     73.66%     73.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                      161      1.21%     74.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      122      0.92%     75.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                      227      1.71%     77.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                      192      1.45%     78.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                      168      1.26%     80.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                      257      1.93%     82.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      171      1.29%     83.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                     2202     16.57%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                13286                       # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
system.cpu.icache.ReadReq_accesses               1703                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36577.562327                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency        35100                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits                   1342                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency       13204500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.211979                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  361                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits                66                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency     10354500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.173224                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             295                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                   4.549153                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses                1703                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 36577.562327                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency        35100                       # average overall mshr miss latency
system.cpu.icache.demand_hits                    1342                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency        13204500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.211979                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   361                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                 66                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency     10354500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.173224                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              295                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0            144.881554                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.070743                       # Average percentage of cache occupancy
system.cpu.icache.overall_accesses               1703                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 36577.562327                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency        35100                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits                   1342                       # number of overall hits
system.cpu.icache.overall_miss_latency       13204500                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.211979                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  361                       # number of overall misses
system.cpu.icache.overall_mshr_hits                66                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency     10354500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.173224                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             295                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                      0                       # number of replacements
system.cpu.icache.sampled_refs                    295                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                144.881554                       # Cycle average of tags in use
system.cpu.icache.total_refs                     1342                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                            9457                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts                  566                       # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches                     1545                       # Number of branches executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_rate                     0.675461                       # Inst execution rate
system.cpu.iew.exec_refs                         2952                       # number of memory reference insts executed
system.cpu.iew.exec_stores                       1295                       # Number of stores executed
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.iewBlockCycles                     187                       # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts                  2082                       # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts                 33                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts               207                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts                 1617                       # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts               19032                       # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts                  1657                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               693                       # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts                 15362                       # Number of executed instructions
system.cpu.iew.iewIQFullEvents                     12                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles                   1477                       # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles                    20                       # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads               69                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses           12                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation           14                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads         1026                       # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores          683                       # Number of stores squashed
system.cpu.iew.memOrderViolationEvents             14                       # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect          497                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect             69                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers                     14668                       # num instructions consuming a value
system.cpu.iew.wb_count                         15056                       # cumulative count of insts written-back
system.cpu.iew.wb_fanout                     0.677734                       # average fanout of values written-back
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers                      9941                       # num instructions producing a value
system.cpu.iew.wb_rate                       0.662006                       # insts written-back per cycle
system.cpu.iew.wb_sent                          15179                       # cumulative count of insts sent to commit
system.cpu.int_regfile_reads                    22959                       # number of integer regfile reads
system.cpu.int_regfile_writes                   13993                       # number of integer regfile writes
system.cpu.ipc                               0.431298                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.431298                       # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass                 4      0.02%      0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                 12893     80.31%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.33% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 1771     11.03%     91.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1387      8.64%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                  16055                       # Type of FU issued
system.cpu.iq.fp_alu_accesses                       5                       # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads                   9                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt                         147                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.009156                       # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                     101     68.71%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     68.71% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                     27     18.37%     87.07% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                    19     12.93%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses                  16193                       # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads              45588                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses        15052                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes             27650                       # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded                      18999                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                     16055                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded                  33                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined            8610                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued                54                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved             20                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined        10851                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples         13286                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.208415                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.917020                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0                8201     61.73%     61.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                1290      9.71%     71.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                 986      7.42%     78.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                 726      5.46%     84.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                 782      5.89%     90.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 580      4.37%     94.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 507      3.82%     98.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                 167      1.26%     99.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                  47      0.35%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           13286                       # Number of insts issued each cycle
system.cpu.iq.rate                           0.705931                       # Inst issue rate
system.cpu.l2cache.ReadExReq_accesses              77                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34603.896104                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31396.103896                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency      2664500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses                77                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency      2417500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses           77                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses               362                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34244.444444                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency      12328000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.994475                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                 360                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency     11174500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994475                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses            360                       # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.005571                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses                439                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34307.780320                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.974828                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency       14992500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.995444                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                  437                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency     13592000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.995444                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses             437                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0           178.188786                       # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0            0.005438                       # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses               439                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34307.780320                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.974828                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                     2                       # number of overall hits
system.cpu.l2cache.overall_miss_latency      14992500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.995444                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                 437                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency     13592000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.995444                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses            437                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.sampled_refs                   359                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse               178.188786                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.memDep0.conflictingLoads                14                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores                3                       # Number of conflicting stores.
system.cpu.memDep0.insertedLoads                 2082                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1617                       # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads                    6812                       # number of misc regfile reads
system.cpu.numCycles                            22743                       # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.rename.BlockCycles                     565                       # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps                  9368                       # Number of HB maps that are committed
system.cpu.rename.IQFullEvents                     52                       # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles                     7327                       # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents                   248                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups                 44292                       # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts                  21008                       # Number of instructions processed by rename
system.cpu.rename.RenamedOperands               19746                       # Number of destination operands rename has renamed
system.cpu.rename.RunCycles                      3097                       # Number of cycles rename is running
system.cpu.rename.SquashCycles                   1477                       # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles                   380                       # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps                    10378                       # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
system.cpu.rename.int_rename_lookups            44276                       # Number of integer rename lookups
system.cpu.rename.serializeStallCycles            440                       # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts                 32                       # count of serializing insts renamed
system.cpu.rename.skidInsts                      1483                       # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts             31                       # count of temporary serializing insts renamed
system.cpu.rob.rob_reads                        30699                       # The number of ROB reads
system.cpu.rob.rob_writes                       39564                       # The number of ROB writes
system.cpu.timesIdled                             184                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls                   11                       # Number of system calls

---------- End Simulation Statistics   ----------
