
---------- Begin Simulation Statistics ----------
host_inst_rate                                 146685                       # Simulator instruction rate (inst/s)
host_mem_usage                                 297796                       # Number of bytes of host memory used
host_seconds                                   389.14                       # Real time elapsed on the host
host_tick_rate                             4887032789                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    57080594                       # Number of instructions simulated
sim_seconds                                  1.901725                       # Number of seconds simulated
sim_ticks                                1901725056500                       # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.BTBHits                 5478793                       # Number of BTB hits
system.cpu0.BPredUnit.BTBLookups             10568954                       # Number of BTB lookups
system.cpu0.BPredUnit.RASInCorrect              28086                       # Number of incorrect RAS predictions.
system.cpu0.BPredUnit.condIncorrect            455851                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.condPredicted           9912652                       # Number of conditional branches predicted
system.cpu0.BPredUnit.lookups                11764241                       # Number of BP lookups
system.cpu0.BPredUnit.usedRAS                  785162                       # Number of times the RAS was used to get a target.
system.cpu0.commit.branchMispredicts           606344                       # The number of times a branch was mispredicted
system.cpu0.commit.branches                   7026012                       # Number of branches committed
system.cpu0.commit.bw_lim_events               938799                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.commit.commitCommittedInsts      47025846                       # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls         585526                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.commitSquashedInsts        5969393                       # The number of squashed insts skipped by commit
system.cpu0.commit.committed_per_cycle::samples     72953049                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.644604                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.459058                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     53597246     73.47%     73.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      8417746     11.54%     85.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      4840163      6.63%     91.64% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      2111570      2.89%     94.54% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1587453      2.18%     96.71% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       575078      0.79%     97.50% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       337488      0.46%     97.96% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       547506      0.75%     98.71% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8       938799      1.29%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     72953049                       # Number of insts commited each cycle
system.cpu0.commit.count                     47025846                       # Number of instructions committed
system.cpu0.commit.fp_insts                    287589                       # Number of committed floating point instructions.
system.cpu0.commit.function_calls              606692                       # Number of function calls committed.
system.cpu0.commit.int_insts                 43528406                       # Number of committed integer instructions.
system.cpu0.commit.loads                      7569996                       # Number of loads committed
system.cpu0.commit.membars                     198353                       # Number of memory barriers committed
system.cpu0.commit.refs                      12959088                       # Number of memory references committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.committedInsts                   44336308                       # Number of Instructions Simulated
system.cpu0.committedInsts_total             44336308                       # Number of Instructions Simulated
system.cpu0.cpi                              2.365714                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.365714                       # CPI: Total CPI of All Threads
system.cpu0.dcache.LoadLockedReq_accesses::0       187921                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       187921                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 13445.030972                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10250.543228                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_hits::0       169356                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       169356                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_latency    249607000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.098792                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses::0        18565                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        18565                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_mshr_hits         3378                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    155675000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.080816                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_misses        15187                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.ReadReq_accesses::0        7569121                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      7569121                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency::0 24067.489407                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26547.034409                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_hits::0            6281230                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6281230                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency   30996303000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate::0      0.170151                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses::0          1287891                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1287891                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_hits           494238                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency  21069133500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.104854                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses         793653                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    636739500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_accesses::0       196148                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       196148                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 12580.258745                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  9578.581696                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_hits::0        191974                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       191974                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_latency     52510000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_rate::0     0.021280                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses::0         4174                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         4174                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_mshr_miss_latency     39981000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.021280                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_misses         4174                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.WriteReq_accesses::0       5179136                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5179136                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency::0 31904.477186                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30396.485851                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_hits::0           3600390                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3600390                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency  50369065740                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate::0     0.304828                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses::0         1578746                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1578746                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_hits         1328268                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_miss_latency   7613650983                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.048363                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses        250478                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1111159498                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8752.803276                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                  9.840448                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs            95418                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs    835174983                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses::0        12748257                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12748257                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency::0 28383.561902                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 27470.484530                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits::0             9881620                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         9881620                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency    81365368740                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate::0       0.224865                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses::0           2866637                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2866637                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits           1822506                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency  28682784483                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate::0     0.081904                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses         1044131                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.occ_blocks::0           489.863061                       # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
system.cpu0.dcache.occ_percent::0            0.956764                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::1           -0.001953                       # Average percentage of cache occupancy
system.cpu0.dcache.overall_accesses::0       12748257                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12748257                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency::0 28383.561902                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 27470.484530                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits::0            9881620                       # number of overall hits
system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu0.dcache.overall_hits::total        9881620                       # number of overall hits
system.cpu0.dcache.overall_miss_latency   81365368740                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate::0      0.224865                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses::0          2866637                       # number of overall misses
system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2866637                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits          1822506                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency  28682784483                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate::0     0.081904                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses        1044131                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency   1747898998                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements               1041325                       # number of replacements
system.cpu0.dcache.sampled_refs               1041715                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               488.863062                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                10250942                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                  532971                       # number of writebacks
system.cpu0.decode.BlockedCycles             30335443                       # Number of cycles decode is blocked
system.cpu0.decode.BranchMispred                32433                       # Number of times decode detected a branch misprediction
system.cpu0.decode.BranchResolved              467445                       # Number of times decode resolved a branch
system.cpu0.decode.DecodedInsts              58302731                       # Number of instructions handled by decode
system.cpu0.decode.IdleCycles                31236137                       # Number of cycles decode is idle
system.cpu0.decode.RunCycles                 10506640                       # Number of cycles decode is running
system.cpu0.decode.SquashCycles               1085015                       # Number of cycles decode is squashing
system.cpu0.decode.SquashedInsts                96992                       # Number of squashed instructions handled by decode
system.cpu0.decode.UnblockCycles               874828                       # Number of cycles decode is unblocking
system.cpu0.dtb.data_accesses                  755162                       # DTB accesses
system.cpu0.dtb.data_acv                          768                       # DTB access violations
system.cpu0.dtb.data_hits                    13777358                       # DTB hits
system.cpu0.dtb.data_misses                     33542                       # DTB misses
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.read_accesses                  569569                       # DTB read accesses
system.cpu0.dtb.read_acv                          514                       # DTB read access violations
system.cpu0.dtb.read_hits                     8255195                       # DTB read hits
system.cpu0.dtb.read_misses                     26791                       # DTB read misses
system.cpu0.dtb.write_accesses                 185593                       # DTB write accesses
system.cpu0.dtb.write_acv                         254                       # DTB write access violations
system.cpu0.dtb.write_hits                    5522163                       # DTB write hits
system.cpu0.dtb.write_misses                     6751                       # DTB write misses
system.cpu0.fetch.Branches                   11764241                       # Number of branches that fetch encountered
system.cpu0.fetch.CacheLines                  7276849                       # Number of cache lines fetched
system.cpu0.fetch.Cycles                     11546182                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.IcacheSquashes               354114                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.Insts                      59401999                       # Number of instructions fetch has processed
system.cpu0.fetch.MiscStallCycles               28935                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.SquashCycles                 709322                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.branchRate                 0.112161                       # Number of branch fetches per cycle
system.cpu0.fetch.icacheStallCycles           7276849                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.predictedBranches           6263955                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.rate                       0.566343                       # Number of inst fetches per cycle
system.cpu0.fetch.rateDist::samples          74038064                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.802317                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.109343                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                62491882     84.41%     84.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  859667      1.16%     85.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1580756      2.14%     87.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  707840      0.96%     88.66% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2540715      3.43%     92.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  543724      0.73%     92.82% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  599348      0.81%     93.63% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  933324      1.26%     94.89% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 3780808      5.11%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            74038064                       # Number of instructions fetched each cycle (Total)
system.cpu0.fp_regfile_reads                   141418                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  143630                       # number of floating regfile writes
system.cpu0.icache.ReadReq_accesses::0        7276849                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      7276849                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency::0 14969.786485                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11880.005982                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits::0            6407354                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        6407354                       # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency   13016154500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate::0      0.119488                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses::0           869495                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       869495                       # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_hits            30374                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_miss_latency   9968762500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.115314                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses         839121                       # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs 11944.444444                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                  7.637231                       # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs               36                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs       430000                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses::0         7276849                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      7276849                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency::0 14969.786485                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 11880.005982                       # average overall mshr miss latency
system.cpu0.icache.demand_hits::0             6407354                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         6407354                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency    13016154500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate::0       0.119488                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_misses::0            869495                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        869495                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits             30374                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency   9968762500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate::0     0.115314                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses          839121                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.occ_blocks::0           509.875783                       # Average occupied blocks per context
system.cpu0.icache.occ_percent::0            0.995851                       # Average percentage of cache occupancy
system.cpu0.icache.overall_accesses::0        7276849                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      7276849                       # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency::0 14969.786485                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 11880.005982                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits::0            6407354                       # number of overall hits
system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
system.cpu0.icache.overall_hits::total        6407354                       # number of overall hits
system.cpu0.icache.overall_miss_latency   13016154500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_rate::0      0.119488                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_misses::0           869495                       # number of overall misses
system.cpu0.icache.overall_misses::1                0                       # number of overall misses
system.cpu0.icache.overall_misses::total       869495                       # number of overall misses
system.cpu0.icache.overall_mshr_hits            30374                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency   9968762500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate::0     0.115314                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses         839121                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements                838452                       # number of replacements
system.cpu0.icache.sampled_refs                838963                       # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse               509.875783                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 6407354                       # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle           23816238000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks                     147                       # number of writebacks
system.cpu0.idleCycles                       30848962                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.branchMispredicts              654991                       # Number of branch mispredicts detected at execute
system.cpu0.iew.exec_branches                 7463719                       # Number of branches executed
system.cpu0.iew.exec_nop                      2952874                       # number of nop insts executed
system.cpu0.iew.exec_rate                    0.449724                       # Inst execution rate
system.cpu0.iew.exec_refs                    13848442                       # number of memory reference insts executed
system.cpu0.iew.exec_stores                   5542976                       # Number of stores executed
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.iewBlockCycles                7417251                       # Number of cycles IEW is blocking
system.cpu0.iew.iewDispLoadInsts              8574378                       # Number of dispatched load instructions
system.cpu0.iew.iewDispNonSpecInsts           1551984                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewDispSquashedInsts           727686                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispStoreInsts             5707393                       # Number of dispatched store instructions
system.cpu0.iew.iewDispatchedInsts           53103916                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewExecLoadInsts              8305466                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           392048                       # Number of squashed instructions skipped in execute
system.cpu0.iew.iewExecutedInsts             47170169                       # Number of executed instructions
system.cpu0.iew.iewIQFullEvents                 90492                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewLSQFullEvents                 5675                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.iewSquashCycles               1085015                       # Number of cycles IEW is squashing
system.cpu0.iew.iewUnblockCycles               526785                       # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.cacheBlocked       157871                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.lsq.thread0.forwLoads          427137                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.ignoredResponses         7542                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.memOrderViolation        14768                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.rescheduledLoads        12869                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.squashedLoads      1004382                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.squashedStores       318301                       # Number of stores squashed
system.cpu0.iew.memOrderViolationEvents         14768                       # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect       331464                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect        323527                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.wb_consumers                 29600256                       # num instructions consuming a value
system.cpu0.iew.wb_count                     46794498                       # cumulative count of insts written-back
system.cpu0.iew.wb_fanout                    0.755402                       # average fanout of values written-back
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.iew.wb_producers                 22360092                       # num instructions producing a value
system.cpu0.iew.wb_rate                      0.446142                       # insts written-back per cycle
system.cpu0.iew.wb_sent                      46875004                       # cumulative count of insts sent to commit
system.cpu0.int_regfile_reads                61873527                       # number of integer regfile reads
system.cpu0.int_regfile_writes               33807346                       # number of integer regfile writes
system.cpu0.ipc                              0.422705                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.422705                       # IPC: Total IPC of All Threads
system.cpu0.iq.FU_type_0::No_OpClass             3310      0.01%      0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             32518161     68.37%     68.38% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               52150      0.11%     68.49% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.49% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd              15557      0.03%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv               1653      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead             8591465     18.06%     86.59% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            5582440     11.74%     98.32% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess            797481      1.68%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              47562217                       # Type of FU issued
system.cpu0.iq.fp_alu_accesses                 318343                       # Number of floating point alu accesses
system.cpu0.iq.fp_inst_queue_reads             608219                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_wakeup_accesses       289004                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_writes            292979                       # Number of floating instruction queue writes
system.cpu0.iq.fu_busy_cnt                     465945                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.009797                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  32168      6.90%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                239318     51.36%     58.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               194459     41.73%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.int_alu_accesses              47706509                       # Number of integer alu accesses
system.cpu0.iq.int_inst_queue_reads         169046393                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_wakeup_accesses     46505494                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.int_inst_queue_writes         55364625                       # Number of integer instruction queue writes
system.cpu0.iq.iqInstsAdded                  48386629                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsIssued                 47562217                       # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded            1764413                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqSquashedInstsExamined        5493402                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedInstsIssued            26169                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved       1178887                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined      2580822                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.issued_per_cycle::samples     74038064                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.642402                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.245120                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           51535584     69.61%     69.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10789742     14.57%     84.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4855288      6.56%     90.74% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3076859      4.16%     94.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            2068166      2.79%     97.69% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             951116      1.28%     98.97% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             576531      0.78%     99.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             134332      0.18%     99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              50446      0.07%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       74038064                       # Number of insts issued each cycle
system.cpu0.iq.rate                          0.453461                       # Inst issue rate
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.fetch_accesses                 933233                       # ITB accesses
system.cpu0.itb.fetch_acv                         717                       # ITB acv
system.cpu0.itb.fetch_hits                     905545                       # ITB hits
system.cpu0.itb.fetch_misses                    27688                       # ITB misses
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  371      0.22%      0.22% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.22% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.22% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.22% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3671      2.19%      2.42% # number of callpals executed
system.cpu0.kern.callpal::tbi                      42      0.03%      2.44% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.45% # number of callpals executed
system.cpu0.kern.callpal::swpipl               151594     90.58%     93.02% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6330      3.78%     96.81% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.81% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     2      0.00%     96.81% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     7      0.00%     96.81% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.81% # number of callpals executed
system.cpu0.kern.callpal::rti                    4884      2.92%     99.73% # number of callpals executed
system.cpu0.kern.callpal::callsys                 315      0.19%     99.92% # number of callpals executed
system.cpu0.kern.callpal::imb                     135      0.08%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                167365                       # number of callpals executed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.hwrei                    180838                       # number of hwrei instructions executed
system.cpu0.kern.inst.quiesce                    5105                       # number of quiesce instructions executed
system.cpu0.kern.ipl_count::0                   63498     39.95%     39.95% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    238      0.15%     40.10% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1926      1.21%     41.31% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    288      0.18%     41.50% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  92981     58.50%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              158931                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    62140     49.14%     49.14% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     238      0.19%     49.33% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1926      1.52%     50.86% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     288      0.23%     51.08% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   61852     48.92%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               126444                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1864722249000     98.07%     98.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               96095500      0.01%     98.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              397148000      0.02%     98.10% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30              112025000      0.01%     98.10% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            36054288500      1.90%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1901381806000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.978613                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.665211                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_good::kernel               1076                      
system.cpu0.kern.mode_good::user                 1076                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch::kernel             7211                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1076                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_switch_good::kernel     0.149216                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1899282367000     99.91%     99.91% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1748332500      0.09%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3672                       # number of times the context was actually changed
system.cpu0.kern.syscall::2                         6      3.17%      3.17% # number of syscalls executed
system.cpu0.kern.syscall::3                        16      8.47%     11.64% # number of syscalls executed
system.cpu0.kern.syscall::4                         3      1.59%     13.23% # number of syscalls executed
system.cpu0.kern.syscall::6                        26     13.76%     26.98% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.53%     27.51% # number of syscalls executed
system.cpu0.kern.syscall::17                        8      4.23%     31.75% # number of syscalls executed
system.cpu0.kern.syscall::19                        6      3.17%     34.92% # number of syscalls executed
system.cpu0.kern.syscall::20                        4      2.12%     37.04% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.53%     37.57% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.59%     39.15% # number of syscalls executed
system.cpu0.kern.syscall::33                        6      3.17%     42.33% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      1.06%     43.39% # number of syscalls executed
system.cpu0.kern.syscall::45                       33     17.46%     60.85% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.59%     62.43% # number of syscalls executed
system.cpu0.kern.syscall::48                        7      3.70%     66.14% # number of syscalls executed
system.cpu0.kern.syscall::54                        9      4.76%     70.90% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.53%     71.43% # number of syscalls executed
system.cpu0.kern.syscall::59                        5      2.65%     74.07% # number of syscalls executed
system.cpu0.kern.syscall::71                       23     12.17%     86.24% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.59%     87.83% # number of syscalls executed
system.cpu0.kern.syscall::74                        6      3.17%     91.01% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.53%     91.53% # number of syscalls executed
system.cpu0.kern.syscall::90                        1      0.53%     92.06% # number of syscalls executed
system.cpu0.kern.syscall::92                        7      3.70%     95.77% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      1.06%     96.83% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      1.06%     97.88% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.53%     98.41% # number of syscalls executed
system.cpu0.kern.syscall::144                       1      0.53%     98.94% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      1.06%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   189                       # number of syscalls executed
system.cpu0.memDep0.conflictingLoads          1239149                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1190008                       # Number of conflicting stores.
system.cpu0.memDep0.insertedLoads             8574378                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5707393                       # Number of stores inserted to the mem dependence unit.
system.cpu0.misc_regfile_reads                1734015                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                822223                       # number of misc regfile writes
system.cpu0.numCycles                       104887026                       # number of cpu cycles simulated
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.rename.BlockCycles               10226952                       # Number of cycles rename is blocking
system.cpu0.rename.CommittedMaps             32010277                       # Number of HB maps that are committed
system.cpu0.rename.IQFullEvents                742771                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.IdleCycles                32554760                       # Number of cycles rename is idle
system.cpu0.rename.LSQFullEvents              1133948                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.ROBFullEvents                 1272                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.RenameLookups             67011150                       # Number of register rename lookups that rename has made
system.cpu0.rename.RenamedInsts              55116446                       # Number of instructions processed by rename
system.cpu0.rename.RenamedOperands           36911598                       # Number of destination operands rename has renamed
system.cpu0.rename.RunCycles                 10340148                       # Number of cycles rename is running
system.cpu0.rename.SquashCycles               1085015                       # Number of cycles rename is squashing
system.cpu0.rename.UnblockCycles              3374476                       # Number of cycles rename is unblocking
system.cpu0.rename.UndoneMaps                 4901321                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.fp_rename_lookups           420638                       # Number of floating rename lookups
system.cpu0.rename.int_rename_lookups        66590512                       # Number of integer rename lookups
system.cpu0.rename.serializeStallCycles      16456711                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.serializingInsts           1432211                       # count of serializing insts renamed
system.cpu0.rename.skidInsts                  8924178                       # count of insts added to the skid buffer
system.cpu0.rename.tempSerializingInsts        217463                       # count of temporary serializing insts renamed
system.cpu0.rob.rob_reads                   124831913                       # The number of ROB reads
system.cpu0.rob.rob_writes                  107074537                       # The number of ROB writes
system.cpu0.timesIdled                        1083848                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.BTBHits                 1509705                       # Number of BTB hits
system.cpu1.BPredUnit.BTBLookups              3127444                       # Number of BTB lookups
system.cpu1.BPredUnit.RASInCorrect               7361                       # Number of incorrect RAS predictions.
system.cpu1.BPredUnit.condIncorrect            156935                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.condPredicted           2982175                       # Number of conditional branches predicted
system.cpu1.BPredUnit.lookups                 3622579                       # Number of BP lookups
system.cpu1.BPredUnit.usedRAS                  265553                       # Number of times the RAS was used to get a target.
system.cpu1.commit.branchMispredicts           207236                       # The number of times a branch was mispredicted
system.cpu1.commit.branches                   2030517                       # Number of branches committed
system.cpu1.commit.bw_lim_events               301379                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.commit.commitCommittedInsts      13448285                       # The number of committed instructions
system.cpu1.commit.commitNonSpecStalls         143621                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.commitSquashedInsts        2329974                       # The number of squashed insts skipped by commit
system.cpu1.commit.committed_per_cycle::samples     21012360                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.640018                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.474919                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     15563519     74.07%     74.07% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      2436778     11.60%     85.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1200178      5.71%     91.38% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       640529      3.05%     94.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       421093      2.00%     96.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       209093      1.00%     97.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       129842      0.62%     98.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       109949      0.52%     98.57% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       301379      1.43%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     21012360                       # Number of insts commited each cycle
system.cpu1.commit.count                     13448285                       # Number of instructions committed
system.cpu1.commit.fp_insts                     77652                       # Number of committed floating point instructions.
system.cpu1.commit.function_calls              196980                       # Number of function calls committed.
system.cpu1.commit.int_insts                 12472477                       # Number of committed integer instructions.
system.cpu1.commit.loads                      2329401                       # Number of loads committed
system.cpu1.commit.membars                      46552                       # Number of memory barriers committed
system.cpu1.commit.refs                       3759357                       # Number of memory references committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.committedInsts                   12744286                       # Number of Instructions Simulated
system.cpu1.committedInsts_total             12744286                       # Number of Instructions Simulated
system.cpu1.cpi                              1.922547                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.922547                       # CPI: Total CPI of All Threads
system.cpu1.dcache.LoadLockedReq_accesses::0        34084                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        34084                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 12032.319953                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  7746.929907                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_hits::0        27308                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        27308                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_latency     81531000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.198803                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses::0         6776                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         6776                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_mshr_hits         1483                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     41004500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.155293                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_misses         5293                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.ReadReq_accesses::0        2478047                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2478047                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency::0 15160.837325                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12203.806584                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_hits::0            2047581                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        2047581                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency    6526225000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate::0      0.173712                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses::0           430466                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       430466                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_hits           150924                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_miss_latency   3411476500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.112807                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses         279542                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency    299904000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.StoreCondReq_accesses::0        32610                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        32610                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13453.081410                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10450.798884                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_hits::0         28667                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        28667                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_latency     53045500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_rate::0     0.120914                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses::0         3943                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         3943                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_mshr_miss_latency     41207500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.120914                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_misses         3943                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.WriteReq_accesses::0       1389552                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1389552                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency::0 29195.465224                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26358.387662                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_hits::0           1086825                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1086825                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency   8838255601                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate::0     0.217859                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses::0          302727                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       302727                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits          250029                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_miss_latency   1389034313                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.037924                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses         52698                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    600087500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12134.424364                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets        11000                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs                  9.983135                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs             9506                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              1                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs    115349838                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets        11000                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses::0         3867599                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      3867599                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency::0 20955.574591                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 14448.924913                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits::0             3134406                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         3134406                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency    15364480601                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate::0       0.189573                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses::0            733193                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        733193                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits            400953                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency   4800510813                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate::0     0.085903                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses          332240                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.occ_blocks::0           478.607338                       # Average occupied blocks per context
system.cpu1.dcache.occ_percent::0            0.934780                       # Average percentage of cache occupancy
system.cpu1.dcache.overall_accesses::0        3867599                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      3867599                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency::0 20955.574591                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 14448.924913                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits::0            3134406                       # number of overall hits
system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu1.dcache.overall_hits::total        3134406                       # number of overall hits
system.cpu1.dcache.overall_miss_latency   15364480601                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate::0      0.189573                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses::0           733193                       # number of overall misses
system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
system.cpu1.dcache.overall_misses::total       733193                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits           400953                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency   4800510813                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate::0     0.085903                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses         332240                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency    899991500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements                320146                       # number of replacements
system.cpu1.dcache.sampled_refs                320658                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse               478.607338                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 3201172                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           38945924000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                  258747                       # number of writebacks
system.cpu1.decode.BlockedCycles              8810954                       # Number of cycles decode is blocked
system.cpu1.decode.BranchMispred                10399                       # Number of times decode detected a branch misprediction
system.cpu1.decode.BranchResolved              165542                       # Number of times decode resolved a branch
system.cpu1.decode.DecodedInsts              17654641                       # Number of instructions handled by decode
system.cpu1.decode.IdleCycles                 8825966                       # Number of cycles decode is idle
system.cpu1.decode.RunCycles                  3267842                       # Number of cycles decode is running
system.cpu1.decode.SquashCycles                401676                       # Number of cycles decode is squashing
system.cpu1.decode.SquashedInsts                25654                       # Number of squashed instructions handled by decode
system.cpu1.decode.UnblockCycles               107597                       # Number of cycles decode is unblocking
system.cpu1.dtb.data_accesses                  513633                       # DTB accesses
system.cpu1.dtb.data_acv                          185                       # DTB access violations
system.cpu1.dtb.data_hits                     4112878                       # DTB hits
system.cpu1.dtb.data_misses                     16265                       # DTB misses
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.read_accesses                  363334                       # DTB read accesses
system.cpu1.dtb.read_acv                           74                       # DTB read access violations
system.cpu1.dtb.read_hits                     2619291                       # DTB read hits
system.cpu1.dtb.read_misses                     12612                       # DTB read misses
system.cpu1.dtb.write_accesses                 150299                       # DTB write accesses
system.cpu1.dtb.write_acv                         111                       # DTB write access violations
system.cpu1.dtb.write_hits                    1493587                       # DTB write hits
system.cpu1.dtb.write_misses                     3653                       # DTB write misses
system.cpu1.fetch.Branches                    3622579                       # Number of branches that fetch encountered
system.cpu1.fetch.CacheLines                  2099932                       # Number of cache lines fetched
system.cpu1.fetch.Cycles                      3426887                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.IcacheSquashes               116518                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.Insts                      18019858                       # Number of instructions fetch has processed
system.cpu1.fetch.MiscStallCycles               11061                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.SquashCycles                 232369                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.branchRate                 0.147851                       # Number of branch fetches per cycle
system.cpu1.fetch.icacheStallCycles           2099931                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.predictedBranches           1775258                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.rate                       0.735460                       # Number of inst fetches per cycle
system.cpu1.fetch.rateDist::samples          21414036                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.841498                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.178120                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                17987149     84.00%     84.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  213365      1.00%     84.99% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  513318      2.40%     87.39% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  281609      1.32%     88.71% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  570957      2.67%     91.37% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  173244      0.81%     92.18% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  240049      1.12%     93.30% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  130072      0.61%     93.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 1304273      6.09%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            21414036                       # Number of instructions fetched each cycle (Total)
system.cpu1.fp_regfile_reads                    44611                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   43862                       # number of floating regfile writes
system.cpu1.icache.ReadReq_accesses::0        2099932                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      2099932                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency::0 15131.623612                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12110.189366                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits::0            1856598                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1856598                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency    3682038500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate::0      0.115877                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses::0           243334                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       243334                       # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_hits             9659                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_miss_latency   2829848500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.111277                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses         233675                       # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs 10681.818182                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                  7.947119                       # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs               22                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs       235000                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses::0         2099932                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      2099932                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency::0 15131.623612                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 12110.189366                       # average overall mshr miss latency
system.cpu1.icache.demand_hits::0             1856598                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1856598                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency     3682038500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate::0       0.115877                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_misses::0            243334                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        243334                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits              9659                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency   2829848500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate::0     0.111277                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses          233675                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.occ_blocks::0           501.781584                       # Average occupied blocks per context
system.cpu1.icache.occ_percent::0            0.980042                       # Average percentage of cache occupancy
system.cpu1.icache.overall_accesses::0        2099932                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      2099932                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency::0 15131.623612                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 12110.189366                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits::0            1856598                       # number of overall hits
system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
system.cpu1.icache.overall_hits::total        1856598                       # number of overall hits
system.cpu1.icache.overall_miss_latency    3682038500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate::0      0.115877                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_misses::0           243334                       # number of overall misses
system.cpu1.icache.overall_misses::1                0                       # number of overall misses
system.cpu1.icache.overall_misses::total       243334                       # number of overall misses
system.cpu1.icache.overall_mshr_hits             9659                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency   2829848500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate::0     0.111277                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses         233675                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements                233107                       # number of replacements
system.cpu1.icache.sampled_refs                233619                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse               501.781584                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 1856598                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1710247615000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                      27                       # number of writebacks
system.cpu1.idleCycles                        3087450                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.branchMispredicts              229368                       # Number of branch mispredicts detected at execute
system.cpu1.iew.exec_branches                 2215124                       # Number of branches executed
system.cpu1.iew.exec_nop                       807214                       # number of nop insts executed
system.cpu1.iew.exec_rate                    0.568172                       # Inst execution rate
system.cpu1.iew.exec_refs                     4143059                       # number of memory reference insts executed
system.cpu1.iew.exec_stores                   1503378                       # Number of stores executed
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.iewBlockCycles                1971298                       # Number of cycles IEW is blocking
system.cpu1.iew.iewDispLoadInsts              2745592                       # Number of dispatched load instructions
system.cpu1.iew.iewDispNonSpecInsts            455487                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewDispSquashedInsts           238559                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispStoreInsts             1578351                       # Number of dispatched store instructions
system.cpu1.iew.iewDispatchedInsts           15868399                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewExecLoadInsts              2639681                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           166261                       # Number of squashed instructions skipped in execute
system.cpu1.iew.iewExecutedInsts             13921060                       # Number of executed instructions
system.cpu1.iew.iewIQFullEvents                 10672                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewLSQFullEvents                 5665                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.iewSquashCycles                401676                       # Number of cycles IEW is squashing
system.cpu1.iew.iewUnblockCycles                76714                       # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.cacheBlocked        25188                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.lsq.thread0.forwLoads           88996                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.ignoredResponses         4435                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.memOrderViolation         4299                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.rescheduledLoads         5923                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.squashedLoads       416191                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.squashedStores       148395                       # Number of stores squashed
system.cpu1.iew.memOrderViolationEvents          4299                       # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect       105547                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect        123821                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.wb_consumers                  9185033                       # num instructions consuming a value
system.cpu1.iew.wb_count                     13765716                       # cumulative count of insts written-back
system.cpu1.iew.wb_fanout                    0.723664                       # average fanout of values written-back
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.iew.wb_producers                  6646874                       # num instructions producing a value
system.cpu1.iew.wb_rate                      0.561832                       # insts written-back per cycle
system.cpu1.iew.wb_sent                      13802747                       # cumulative count of insts sent to commit
system.cpu1.int_regfile_reads                18282773                       # number of integer regfile reads
system.cpu1.int_regfile_writes                9947337                       # number of integer regfile writes
system.cpu1.ipc                              0.520143                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.520143                       # IPC: Total IPC of All Threads
system.cpu1.iq.FU_type_0::No_OpClass             3979      0.03%      0.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu              9510353     67.51%     67.54% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               21826      0.15%     67.69% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.69% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd              11300      0.08%     67.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv               1989      0.01%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead             2724274     19.34%     87.13% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            1523321     10.81%     97.94% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess            290281      2.06%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              14087323                       # Type of FU issued
system.cpu1.iq.fp_alu_accesses                  84267                       # Number of floating point alu accesses
system.cpu1.iq.fp_inst_queue_reads             163543                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_wakeup_accesses        78913                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_writes             80927                       # Number of floating instruction queue writes
system.cpu1.iq.fu_busy_cnt                     199599                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.014169                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  10735      5.38%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                110682     55.45%     60.83% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                78182     39.17%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.int_alu_accesses              14198676                       # Number of integer alu accesses
system.cpu1.iq.int_inst_queue_reads          49640351                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_wakeup_accesses     13686803                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.int_inst_queue_writes         17182956                       # Number of integer instruction queue writes
system.cpu1.iq.iqInstsAdded                  14556864                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqInstsIssued                 14087323                       # Number of instructions issued
system.cpu1.iq.iqNonSpecInstsAdded             504321                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqSquashedInstsExamined        2199611                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedInstsIssued            15615                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved        360700                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.iqSquashedOperandsExamined      1165068                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.issued_per_cycle::samples     21414036                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.657855                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.314285                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           15246065     71.20%     71.20% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            2762432     12.90%     84.10% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            1149877      5.37%     89.47% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3             942390      4.40%     93.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             699267      3.27%     97.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5             379191      1.77%     98.90% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             160390      0.75%     99.65% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7              52788      0.25%     99.90% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              21636      0.10%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       21414036                       # Number of insts issued each cycle
system.cpu1.iq.rate                          0.574958                       # Inst issue rate
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.fetch_accesses                 456053                       # ITB accesses
system.cpu1.itb.fetch_acv                         249                       # ITB acv
system.cpu1.itb.fetch_hits                     445822                       # ITB hits
system.cpu1.itb.fetch_misses                    10231                       # ITB misses
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  288      0.55%      0.56% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.56% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.56% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1111      2.14%      2.70% # number of callpals executed
system.cpu1.kern.callpal::tbi                      11      0.02%      2.72% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      2.73% # number of callpals executed
system.cpu1.kern.callpal::swpipl                44860     86.39%     89.12% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2426      4.67%     93.79% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.79% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     5      0.01%     93.80% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     2      0.00%     93.81% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     93.81% # number of callpals executed
system.cpu1.kern.callpal::rti                    2967      5.71%     99.53% # number of callpals executed
system.cpu1.kern.callpal::callsys                 200      0.39%     99.91% # number of callpals executed
system.cpu1.kern.callpal::imb                      45      0.09%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 51930                       # number of callpals executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.hwrei                     60321                       # number of hwrei instructions executed
system.cpu1.kern.inst.quiesce                    4094                       # number of quiesce instructions executed
system.cpu1.kern.ipl_count::0                   19374     38.65%     38.65% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1924      3.84%     42.49% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    371      0.74%     43.23% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  28454     56.77%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               50123                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    19355     47.63%     47.63% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1924      4.73%     52.37% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     371      0.91%     53.28% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   18984     46.72%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                40634                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1871185338500     98.39%     98.39% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              350210000      0.02%     98.41% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              149885000      0.01%     98.42% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            30038792500      1.58%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1901724226000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.999019                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.667182                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.mode_good::kernel                994                      
system.cpu1.kern.mode_good::user                  661                      
system.cpu1.kern.mode_good::idle                  333                      
system.cpu1.kern.mode_switch::kernel             1487                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                661                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2593                       # number of protection mode switches
system.cpu1.kern.mode_switch_good::kernel     0.668460                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.128423                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     1.796883                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel       37276082000      1.96%      1.96% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user          1059454000      0.06%      2.02% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1863388682000     97.98%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1112                       # number of times the context was actually changed
system.cpu1.kern.syscall::2                         2      1.46%      1.46% # number of syscalls executed
system.cpu1.kern.syscall::3                        14     10.22%     11.68% # number of syscalls executed
system.cpu1.kern.syscall::4                         1      0.73%     12.41% # number of syscalls executed
system.cpu1.kern.syscall::6                        16     11.68%     24.09% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.73%     24.82% # number of syscalls executed
system.cpu1.kern.syscall::17                        7      5.11%     29.93% # number of syscalls executed
system.cpu1.kern.syscall::19                        4      2.92%     32.85% # number of syscalls executed
system.cpu1.kern.syscall::20                        2      1.46%     34.31% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.19%     36.50% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.19%     38.69% # number of syscalls executed
system.cpu1.kern.syscall::33                        5      3.65%     42.34% # number of syscalls executed
system.cpu1.kern.syscall::45                       21     15.33%     57.66% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.19%     59.85% # number of syscalls executed
system.cpu1.kern.syscall::48                        3      2.19%     62.04% # number of syscalls executed
system.cpu1.kern.syscall::54                        1      0.73%     62.77% # number of syscalls executed
system.cpu1.kern.syscall::59                        2      1.46%     64.23% # number of syscalls executed
system.cpu1.kern.syscall::71                       31     22.63%     86.86% # number of syscalls executed
system.cpu1.kern.syscall::74                       10      7.30%     94.16% # number of syscalls executed
system.cpu1.kern.syscall::90                        2      1.46%     95.62% # number of syscalls executed
system.cpu1.kern.syscall::92                        2      1.46%     97.08% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.19%     99.27% # number of syscalls executed
system.cpu1.kern.syscall::144                       1      0.73%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   137                       # number of syscalls executed
system.cpu1.memDep0.conflictingLoads           315526                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          194379                       # Number of conflicting stores.
system.cpu1.memDep0.insertedLoads             2745592                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1578351                       # Number of stores inserted to the mem dependence unit.
system.cpu1.misc_regfile_reads                 493874                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                221749                       # number of misc regfile writes
system.cpu1.numCycles                        24501486                       # number of cpu cycles simulated
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.rename.BlockCycles                2575160                       # Number of cycles rename is blocking
system.cpu1.rename.CommittedMaps              9194083                       # Number of HB maps that are committed
system.cpu1.rename.IQFullEvents                253610                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.IdleCycles                 9125188                       # Number of cycles rename is idle
system.cpu1.rename.LSQFullEvents                96900                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.ROBFullEvents                  103                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.RenameLookups             20382349                       # Number of register rename lookups that rename has made
system.cpu1.rename.RenamedInsts              16583054                       # Number of instructions processed by rename
system.cpu1.rename.RenamedOperands           11154403                       # Number of destination operands rename has renamed
system.cpu1.rename.RunCycles                  2970670                       # Number of cycles rename is running
system.cpu1.rename.SquashCycles                401676                       # Number of cycles rename is squashing
system.cpu1.rename.UnblockCycles               911632                       # Number of cycles rename is unblocking
system.cpu1.rename.UndoneMaps                 1960318                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.fp_rename_lookups           113596                       # Number of floating rename lookups
system.cpu1.rename.int_rename_lookups        20268753                       # Number of integer rename lookups
system.cpu1.rename.serializeStallCycles       5429708                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.serializingInsts            475094                       # count of serializing insts renamed
system.cpu1.rename.skidInsts                  2839642                       # count of insts added to the skid buffer
system.cpu1.rename.tempSerializingInsts         40509                       # count of temporary serializing insts renamed
system.cpu1.rob.rob_reads                    36377887                       # The number of ROB reads
system.cpu1.rob.rob_writes                   31956605                       # The number of ROB writes
system.cpu1.timesIdled                         286877                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iocache.ReadReq_accesses::1                175                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1 115257.131429                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_mshr_miss_latency 63257.131429                       # average ReadReq mshr miss latency
system.iocache.ReadReq_miss_latency          20169998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_misses::1                  175                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
system.iocache.ReadReq_mshr_miss_latency     11069998                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_misses                175                       # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 137655.487245                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85651.857817                       # average WriteReq mshr miss latency
system.iocache.WriteReq_miss_latency       5719860806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.WriteReq_mshr_miss_latency   3559005996                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
system.iocache.avg_blocked_cycles::no_mshrs  6179.103844                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs                10458                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs      64621068                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1               41727                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41727                       # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1 137561.550171                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency 85557.935965                       # average overall mshr miss latency
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.demand_miss_latency         5740030804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                 41727                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency    3570075994                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses               41727                       # number of demand (read+write) MSHR misses
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.iocache.occ_blocks::1                 0.207263                       # Average occupied blocks per context
system.iocache.occ_percent::1                0.012954                       # Average percentage of cache occupancy
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1              41727                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1 137561.550171                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency 85557.935965                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.overall_miss_latency        5740030804                       # number of overall miss cycles
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                41727                       # number of overall misses
system.iocache.overall_misses::total            41727                       # number of overall misses
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency   3570075994                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses              41727                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.replacements                     41695                       # number of replacements
system.iocache.sampled_refs                     41711                       # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse                     0.207263                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.warmup_cycle              1710304111000                       # Cycle when the warmup percentage was hit.
system.iocache.writebacks                       41520                       # number of writebacks
system.l2c.ReadExReq_accesses::0               243081                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                47227                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           290308                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 61154.932642                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 368564.170526                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40302.705557                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_hits::0                   135076                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::1                    29306                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               164382                       # number of ReadExReq hits
system.l2c.ReadExReq_miss_latency          6605038500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0            0.444317                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1            0.379465                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0                 108005                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                  17921                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             125926                       # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency     5075158500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0       0.518041                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1       2.666398                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses               125926                       # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0                1634357                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 503467                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2137824                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0   53314.961165                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   2119707.492415                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40003.636264                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits::0                    1332950                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     495886                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1828836                       # number of ReadReq hits
system.l2c.ReadReq_miss_latency           16069502500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0              0.184419                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.015058                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0                   301407                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                     7581                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               308988                       # number of ReadReq misses
system.l2c.ReadReq_mshr_hits                       17                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency      12359963500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.189047                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.613687                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses                 308971                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency    838535000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.SCUpgradeReq_accesses::0               620                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::1               656                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1276                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_avg_miss_latency::0 18379.965458                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1 17109.324759                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40002.081599                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_hits::0                    41                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::1                    34                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                75                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_miss_latency         10642000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_rate::0         0.933871                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1         0.948171                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_misses::0                 579                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::1                 622                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1201                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_mshr_miss_latency     48042500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.937097                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.830793                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_misses              1201                       # number of SCUpgradeReq MSHR misses
system.l2c.UpgradeReq_accesses::0                3788                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                 897                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4685                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0  1321.100917                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1  5809.290954                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.698754                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_hits::0                     191                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::1                      79                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 270                       # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_latency            4752000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0           0.949578                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1           0.911929                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0                  3597                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                   818                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              4415                       # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency     176607500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0      1.165523                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1      4.921962                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses                4415                       # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency   1545168498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses::0               791892                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           791892                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0                   791892                       # number of Writeback hits
system.l2c.Writeback_hits::total               791892                       # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.avg_refs                          5.551399                       # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses::0                 1877438                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  550694                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2428132                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0    55383.186130                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    889127.950749                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency  40090.232860                       # average overall mshr miss latency
system.l2c.demand_hits::0                     1468026                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      525192                       # number of demand (read+write) hits
system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1993218                       # number of demand (read+write) hits
system.l2c.demand_miss_latency            22674541000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0               0.218070                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.046309                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
system.l2c.demand_misses::0                    409412                       # number of demand (read+write) misses
system.l2c.demand_misses::1                     25502                       # number of demand (read+write) misses
system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
system.l2c.demand_misses::total                434914                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                        17                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency       17435122000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0          0.231644                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          0.789725                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                  434897                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.occ_blocks::0                 10408.866153                       # Average occupied blocks per context
system.l2c.occ_blocks::1                  2398.359333                       # Average occupied blocks per context
system.l2c.occ_blocks::2                 23061.577659                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.158827                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.036596                       # Average percentage of cache occupancy
system.l2c.occ_percent::2                    0.351892                       # Average percentage of cache occupancy
system.l2c.overall_accesses::0                1877438                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 550694                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2428132                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0   55383.186130                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   889127.950749                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40090.232860                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.overall_hits::0                    1468026                       # number of overall hits
system.l2c.overall_hits::1                     525192                       # number of overall hits
system.l2c.overall_hits::2                          0                       # number of overall hits
system.l2c.overall_hits::total                1993218                       # number of overall hits
system.l2c.overall_miss_latency           22674541000                       # number of overall miss cycles
system.l2c.overall_miss_rate::0              0.218070                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.046309                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
system.l2c.overall_misses::0                   409412                       # number of overall misses
system.l2c.overall_misses::1                    25502                       # number of overall misses
system.l2c.overall_misses::2                        0                       # number of overall misses
system.l2c.overall_misses::total               434914                       # number of overall misses
system.l2c.overall_mshr_hits                       17                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency      17435122000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0         0.231644                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         0.789725                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                 434897                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency   2383703498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.replacements                        397174                       # number of replacements
system.l2c.sampled_refs                        433601                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                     35868.803144                       # Cycle average of tags in use
system.l2c.total_refs                         2407092                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                    9258990000                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                          122449                       # number of writebacks
system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR

---------- End Simulation Statistics   ----------
