
---------- Begin Simulation Statistics ----------
host_inst_rate                                2031292                       # Simulator instruction rate (inst/s)
host_mem_usage                                 221580                       # Number of bytes of host memory used
host_seconds                                    49.13                       # Real time elapsed on the host
host_tick_rate                             2709639216                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    99791663                       # Number of instructions simulated
sim_seconds                                  0.133117                       # Number of seconds simulated
sim_ticks                                133117442000                       # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses        15919                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits            15919                       # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses           27140334                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits               27087368                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency     1862630000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.001952                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                52966                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency   1703732000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.001952                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses           52966                       # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses         15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits             15919                       # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses          19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits              19742869                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency    5808782000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.005392                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses              107032                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency   5487686000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.005392                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses         107032                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                 292.891630                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses            46990235                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 47946.924337                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                46830237                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency      7671412000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.003405                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                159998                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency   7191418000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.003405                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses           159998                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0           4076.934010                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.995345                       # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses           46990235                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 47946.924337                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits               46830237                       # number of overall hits
system.cpu.dcache.overall_miss_latency     7671412000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.003405                       # miss rate for overall accesses
system.cpu.dcache.overall_misses               159998                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency   7191418000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.003405                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses          159998                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                 155902                       # number of replacements
system.cpu.dcache.sampled_refs                 159998                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               4076.934010                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 46862075                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle             1079641000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                   122808                       # number of writebacks
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.icache.ReadReq_accesses           78145078                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 24211.233340                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits               78126170                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency      457786000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000242                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                18908                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency    401062000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000242                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses           18908                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                4131.910831                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses            78145078                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 24211.233340                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
system.cpu.icache.demand_hits                78126170                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency       457786000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000242                       # miss rate for demand accesses
system.cpu.icache.demand_misses                 18908                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency    401062000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000242                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses            18908                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0           1736.182852                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.847746                       # Average percentage of cache occupancy
system.cpu.icache.overall_accesses           78145078                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 24211.233340                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits               78126170                       # number of overall hits
system.cpu.icache.overall_miss_latency      457786000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000242                       # miss rate for overall accesses
system.cpu.icache.overall_misses                18908                       # number of overall misses
system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency    401062000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000242                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses           18908                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                  16890                       # number of replacements
system.cpu.icache.sampled_refs                  18908                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse               1736.182852                       # Cycle average of tags in use
system.cpu.icache.total_refs                 78126170                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses          107032                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits                4405                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency   5336604000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate       0.958844                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses            102627                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency   4105080000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.958844                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses       102627                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses             71874                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                 40584                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency    1627080000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.435345                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses               31290                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency   1251600000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.435345                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses          31290                       # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses          122808                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits              122808                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.466454                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses             178906                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                  44989                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency     6963684000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.748533                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses               133917                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency   5356680000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.748533                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses          133917                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0          2165.921088                       # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1         16025.699940                       # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0            0.066099                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1            0.489066                       # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses            178906                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                 44989                       # number of overall hits
system.cpu.l2cache.overall_miss_latency    6963684000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.748533                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses              133917                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency   5356680000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.748533                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses         133917                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                113660                       # number of replacements
system.cpu.l2cache.sampled_refs                132489                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse             18191.621028                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                   61800                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                   88449                       # number of writebacks
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.numCycles                        266234884                       # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.num_busy_cycles                  266234884                       # Number of busy cycles
system.cpu.num_conditional_control_insts      8920660                       # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
system.cpu.num_fp_insts                            56                       # number of float instructions
system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
system.cpu.num_func_calls                     3287514                       # number of times a function call or return occured
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_insts                         99791663                       # Number of instructions executed
system.cpu.num_int_alu_accesses              91472788                       # Number of integer alu accesses
system.cpu.num_int_insts                     91472788                       # number of integer instructions
system.cpu.num_int_register_reads           288972903                       # number of times the integer registers were read
system.cpu.num_int_register_writes           73126599                       # number of times the integer registers were written
system.cpu.num_load_insts                    27307109                       # Number of load instructions
system.cpu.num_mem_refs                      47862848                       # number of memory refs
system.cpu.num_store_insts                   20555739                       # Number of store instructions
system.cpu.workload.num_syscalls                 1946                       # Number of system calls

---------- End Simulation Statistics   ----------
