
---------- Begin Simulation Statistics ----------
host_inst_rate                                 116803                       # Simulator instruction rate (inst/s)
host_mem_usage                                 223612                       # Number of bytes of host memory used
host_seconds                                  4908.63                       # Real time elapsed on the host
host_tick_rate                               67784916                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                   573342397                       # Number of instructions simulated
sim_seconds                                  0.332731                       # Number of seconds simulated
sim_ticks                                332731219000                       # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits                157170154                       # Number of BTB hits
system.cpu.BPredUnit.BTBLookups             189971474                       # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect             2546633                       # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect           18809964                       # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted          186338321                       # Number of conditional branches predicted
system.cpu.BPredUnit.lookups                233659814                       # Number of BP lookups
system.cpu.BPredUnit.usedRAS                 11860569                       # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts          20926821                       # The number of times a branch was mispredicted
system.cpu.commit.branches                  120192362                       # Number of branches committed
system.cpu.commit.bw_lim_events               6858146                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts      574686281                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls         3877893                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts       381923221                       # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples    603587786                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.952117                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.448029                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    310030081     51.36%     51.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    161983498     26.84%     78.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     68757792     11.39%     89.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     25709435      4.26%     93.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     17326011      2.87%     96.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      5210197      0.86%     97.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      6149685      1.02%     98.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1562941      0.26%     98.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6858146      1.14%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    603587786                       # Number of insts commited each cycle
system.cpu.commit.count                     574686281                       # Number of instructions committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.int_insts                 473702185                       # Number of committed integer instructions.
system.cpu.commit.loads                     126773177                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.refs                      184377275                       # Number of memory references committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.committedInsts                   573342397                       # Number of Instructions Simulated
system.cpu.committedInsts_total             573342397                       # Number of Instructions Simulated
system.cpu.cpi                               1.160672                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.160672                       # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses      2604457                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency  7857.142857                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_hits          2604422                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency       275000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate     0.000013                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses             35                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits           35                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.ReadReq_accesses          143454074                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 10689.937494                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7026.878867                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits              142382969                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency    11450045500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.007467                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses              1071105                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits            217572                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency   5997673000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.005950                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses          853533                       # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses       2232162                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits           2232162                       # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses          54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 15503.883790                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12993.978894                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits              52863588                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency   21328972000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.025364                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses             1375718                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits          1033256                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency   4449944000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.006314                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses         342462                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                 167.338700                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses           197693380                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13396.562604                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency  8735.502239                       # average overall mshr miss latency
system.cpu.dcache.demand_hits               195246557                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency     32779017500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.012377                       # miss rate for demand accesses
system.cpu.dcache.demand_misses               2446823                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits            1250828                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency  10447617000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.006050                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses          1195995                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0           4061.060335                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.991470                       # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses          197693380                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13396.562604                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency  8735.502239                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits              195246557                       # number of overall hits
system.cpu.dcache.overall_miss_latency    32779017500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.012377                       # miss rate for overall accesses
system.cpu.dcache.overall_misses              2446823                       # number of overall misses
system.cpu.dcache.overall_mshr_hits           1250828                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency  10447617000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.006050                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses         1195995                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                1191585                       # number of replacements
system.cpu.dcache.sampled_refs                1195681                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               4061.060335                       # Cycle average of tags in use
system.cpu.dcache.total_refs                200083704                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle             6358781000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                  1064793                       # number of writebacks
system.cpu.decode.BlockedCycles              85842380                       # Number of cycles decode is blocked
system.cpu.decode.BranchMispred                 76871                       # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved             34367828                       # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts             1126968144                       # Number of instructions handled by decode
system.cpu.decode.IdleCycles                277630014                       # Number of cycles decode is idle
system.cpu.decode.RunCycles                 236143765                       # Number of cycles decode is running
system.cpu.decode.SquashCycles               57332647                       # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts                218235                       # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles               3971626                       # Number of cycles decode is unblocking
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.fetch.Branches                   233659814                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                 132169265                       # Number of cache lines fetched
system.cpu.fetch.Cycles                     250543993                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes               4563312                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                     1003583241                       # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles                 3753                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles                21196803                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.351124                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles          132169265                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches          169030723                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        1.508099                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples          660920432                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.774764                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.719580                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                410388026     62.09%     62.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 20297992      3.07%     65.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 37708836      5.71%     70.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 39874346      6.03%     76.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 40511205      6.13%     83.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 16776062      2.54%     85.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 18545890      2.81%     88.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 14106044      2.13%     90.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 62712031      9.49%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            660920432                       # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.icache.ReadReq_accesses          132169265                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 14331.781024                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10612.450522                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits              132154341                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency      213887500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000113                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                14924                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits              1029                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency    147460000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000105                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses           13895                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                9748.051560                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses           132169265                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 14331.781024                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 10612.450522                       # average overall mshr miss latency
system.cpu.icache.demand_hits               132154341                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency       213887500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000113                       # miss rate for demand accesses
system.cpu.icache.demand_misses                 14924                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits               1029                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency    147460000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000105                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses            13895                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0           1053.520934                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.514415                       # Average percentage of cache occupancy
system.cpu.icache.overall_accesses          132169265                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 14331.781024                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 10612.450522                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits              132154341                       # number of overall hits
system.cpu.icache.overall_miss_latency      213887500                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000113                       # miss rate for overall accesses
system.cpu.icache.overall_misses                14924                       # number of overall misses
system.cpu.icache.overall_mshr_hits              1029                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency    147460000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000105                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses           13895                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                  11791                       # number of replacements
system.cpu.icache.sampled_refs                  13557                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse               1053.520934                       # Cycle average of tags in use
system.cpu.icache.total_refs                132154335                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        4                       # number of writebacks
system.cpu.idleCycles                         4542007                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts             25100140                       # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches                142399885                       # Number of branches executed
system.cpu.iew.exec_nop                       9420990                       # number of nop insts executed
system.cpu.iew.exec_rate                     1.051214                       # Inst execution rate
system.cpu.iew.exec_refs                    220838036                       # number of memory reference insts executed
system.cpu.iew.exec_stores                   66554903                       # Number of stores executed
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.iewBlockCycles                 2947924                       # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts             196892006                       # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts            2816035                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts          18822753                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts            114373867                       # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts           956606524                       # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts             154283133                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          25300490                       # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts             699543688                       # Number of executed instructions
system.cpu.iew.iewIQFullEvents                 130928                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents                  7156                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles               57332647                       # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles                209223                       # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked            75                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads          5626597                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses        13730                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation       241250                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads        24511                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads     70118828                       # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores     56769769                       # Number of stores squashed
system.cpu.iew.memOrderViolationEvents         241250                       # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect      6965983                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect       18134157                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers                 782273717                       # num instructions consuming a value
system.cpu.iew.wb_count                     680637923                       # cumulative count of insts written-back
system.cpu.iew.wb_fanout                     0.486169                       # average fanout of values written-back
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers                 380317186                       # num instructions producing a value
system.cpu.iew.wb_rate                       1.022804                       # insts written-back per cycle
system.cpu.iew.wb_sent                      691183006                       # cumulative count of insts sent to commit
system.cpu.int_regfile_reads               1609052037                       # number of integer regfile reads
system.cpu.int_regfile_writes               524399004                       # number of integer regfile writes
system.cpu.ipc                               0.861570                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.861570                       # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             491156775     67.76%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               386013      0.05%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 106      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.81% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            162458896     22.41%     90.23% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            70842385      9.77%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              724844178                       # Type of FU issued
system.cpu.iq.fp_alu_accesses                     126                       # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads                 248                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes                340                       # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt                     8619148                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.011891                       # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   25536      0.30%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                5445227     63.18%     63.47% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3148385     36.53%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses              733463200                       # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads         2121563604                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses    680637907                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes        1319150008                       # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded                  942508573                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                 724844178                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded             4676961                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined       371760121                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued           2335916                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved         799068                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined    680735331                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples     660920432                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.096719                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.355430                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           305964281     46.29%     46.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           148313904     22.44%     68.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           112740957     17.06%     85.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            49799071      7.53%     93.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            29063149      4.40%     97.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             8262993      1.25%     98.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             4169807      0.63%     99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1785416      0.27%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              820854      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       660920432                       # Number of insts issued each cycle
system.cpu.iq.rate                           1.089234                       # Inst issue rate
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses          342473                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34244.416047                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.822429                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits              231351                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency   3805308000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate       0.324469                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses            111122                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency   3445429000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.324469                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses       111122                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses            866749                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34192.097787                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31026.522397                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                741784                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency    4272815500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.144177                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses              124965                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits               14                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency   3876795000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.144161                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses         124951                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses            298                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency  4635.416667                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31057.291667                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_hits                202                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_miss_latency       445000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate      0.322148                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses               96                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency      2981500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.322148                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses           96                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses         1064797                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits             1064797                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  6.452091                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses            1209222                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34216.723072                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31016.778708                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                 973135                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency     8078123500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.195239                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses               236087                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency   7322224000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.195227                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses          236073                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0          7099.133966                       # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1         13800.334539                       # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0            0.216648                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1            0.421153                       # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses           1209222                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34216.723072                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31016.778708                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                973135                       # number of overall hits
system.cpu.l2cache.overall_miss_latency    8078123500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.195239                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses              236087                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits               14                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency   7322224000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.195227                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses         236073                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                217008                       # number of replacements
system.cpu.l2cache.sampled_refs                237229                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse             20899.468505                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1530623                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          239794586000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                  171527                       # number of writebacks
system.cpu.memDep0.conflictingLoads          54793834                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         61680450                       # Number of conflicting stores.
system.cpu.memDep0.insertedLoads            196892006                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           114373867                       # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads              1238278234                       # number of misc regfile reads
system.cpu.misc_regfile_writes                4464326                       # number of misc regfile writes
system.cpu.numCycles                        665462439                       # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.rename.BlockCycles                11783884                       # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps             448493735                       # Number of HB maps that are committed
system.cpu.rename.IQFullEvents                9081964                       # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles                293899856                       # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents              10512591                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents                   133                       # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups            2673538298                       # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts             1068521543                       # Number of instructions processed by rename
system.cpu.rename.RenamedOperands           798521782                       # Number of destination operands rename has renamed
system.cpu.rename.RunCycles                 223635059                       # Number of cycles rename is running
system.cpu.rename.SquashCycles               57332647                       # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles              24492193                       # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps                350028044                       # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups              1141                       # Number of floating rename lookups
system.cpu.rename.int_rename_lookups       2673537157                       # Number of integer rename lookups
system.cpu.rename.serializeStallCycles       49776793                       # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts            2837350                       # count of serializing insts renamed
system.cpu.rename.skidInsts                  62579735                       # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts        2837280                       # count of temporary serializing insts renamed
system.cpu.rob.rob_reads                   1553332004                       # The number of ROB reads
system.cpu.rob.rob_writes                  1970603439                       # The number of ROB writes
system.cpu.timesIdled                          108463                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls                  548                       # Number of system calls

---------- End Simulation Statistics   ----------
