
---------- Begin Simulation Statistics ----------
host_inst_rate                                 539149                       # Simulator instruction rate (inst/s)
host_mem_usage                                 203248                       # Number of bytes of host memory used
host_seconds                                     0.01                       # Real time elapsed on the host
host_tick_rate                             2800713812                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                        5340                       # Number of instructions simulated
sim_seconds                                  0.000028                       # Number of seconds simulated
sim_ticks                                    28206000                       # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses                716                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits                    662                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency        2982000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.075419                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                   54                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency      2820000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.075419                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses              54                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses               673                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits                   592                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency       4536000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.120357                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                  81                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency      4293000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.120357                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses             81                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                   9.288889                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses                1389                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 55688.888889                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52688.888889                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                    1254                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency         7518000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.097192                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                   135                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency      7113000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.097192                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses              135                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0             82.065697                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.020036                       # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses               1389                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55688.888889                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52688.888889                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits                   1254                       # number of overall hits
system.cpu.dcache.overall_miss_latency        7518000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.097192                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                  135                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency      7113000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.097192                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses             135                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.sampled_refs                    135                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                 82.065697                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     1254                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                        0                       # number of writebacks
system.cpu.icache.ReadReq_accesses               5384                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55673.151751                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits                   5127                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency       14308000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.047734                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  257                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency     13537000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.047734                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             257                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                  19.949416                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses                5384                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 55673.151751                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751                       # average overall mshr miss latency
system.cpu.icache.demand_hits                    5127                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency        14308000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.047734                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   257                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency     13537000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.047734                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              257                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0            116.975932                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.057117                       # Average percentage of cache occupancy
system.cpu.icache.overall_accesses               5384                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55673.151751                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits                   5127                       # number of overall hits
system.cpu.icache.overall_miss_latency       14308000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.047734                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  257                       # number of overall misses
system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency     13537000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.047734                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             257                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                      0                       # number of replacements
system.cpu.icache.sampled_refs                    257                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                116.975932                       # Cycle average of tags in use
system.cpu.icache.total_refs                     5127                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses              81                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency      4212000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses                81                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency      3240000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses           81                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses               311                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                     3                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency      16016000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.990354                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                 308                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency     12320000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.990354                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses            308                       # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.009740                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses                392                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                      3                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency       20228000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.992347                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                  389                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency     15560000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.992347                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses             389                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0           142.102892                       # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0            0.004337                       # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses               392                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                     3                       # number of overall hits
system.cpu.l2cache.overall_miss_latency      20228000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.992347                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                 389                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency     15560000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.992347                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses            389                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.sampled_refs                   308                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse               142.102892                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.numCycles                            56412                       # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.num_busy_cycles                      56412                       # Number of busy cycles
system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_func_calls                           0                       # number of times a function call or return occured
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_insts                             5340                       # Number of instructions executed
system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
system.cpu.num_int_insts                         4517                       # number of integer instructions
system.cpu.num_int_register_reads               10620                       # number of times the integer registers were read
system.cpu.num_int_register_writes               4858                       # number of times the integer registers were written
system.cpu.num_load_insts                         724                       # Number of load instructions
system.cpu.num_mem_refs                          1402                       # number of memory refs
system.cpu.num_store_insts                        678                       # Number of store instructions
system.cpu.workload.num_syscalls                   11                       # Number of system calls

---------- End Simulation Statistics   ----------
