
---------- Begin Simulation Statistics ----------
sim_seconds                                 51.688741                       # Number of seconds simulated
sim_ticks                                51688741391000                       # Number of ticks simulated
final_tick                               51688741391000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 269524                       # Simulator instruction rate (inst/s)
host_op_rate                                   316717                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            14692427127                       # Simulator tick rate (ticks/s)
host_mem_usage                                 686428                       # Number of bytes of host memory used
host_seconds                                  3518.05                       # Real time elapsed on the host
sim_insts                                   948199503                       # Number of instructions simulated
sim_ops                                    1114227092                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker       396416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       330752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst          10254464                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          65885128                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        402816                       # Number of bytes read from this memory
system.physmem.bytes_read::total             77269576                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst     10254464                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total        10254464                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     94159808                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          94180388                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         6194                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         5168                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             160226                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1029468                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6294                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1207350                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1471247                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1473820                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           7669                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           6399                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               198389                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1274651                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7793                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1494901                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          198389                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             198389                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1821670                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1822068                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1821670                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          7669                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          6399                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              198389                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1275050                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7793                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3316969                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1207350                       # Number of read requests accepted
system.physmem.writeReqs                      1473820                       # Number of write requests accepted
system.physmem.readBursts                     1207350                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1473820                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 77222592                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     47808                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  94178368                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  77269576                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               94180388                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      747                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2262                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               73856                       # Per bank write bursts
system.physmem.perBankRdBursts::1               76732                       # Per bank write bursts
system.physmem.perBankRdBursts::2               71137                       # Per bank write bursts
system.physmem.perBankRdBursts::3               69219                       # Per bank write bursts
system.physmem.perBankRdBursts::4               73839                       # Per bank write bursts
system.physmem.perBankRdBursts::5               75948                       # Per bank write bursts
system.physmem.perBankRdBursts::6               69505                       # Per bank write bursts
system.physmem.perBankRdBursts::7               70913                       # Per bank write bursts
system.physmem.perBankRdBursts::8               66486                       # Per bank write bursts
system.physmem.perBankRdBursts::9              126372                       # Per bank write bursts
system.physmem.perBankRdBursts::10              74130                       # Per bank write bursts
system.physmem.perBankRdBursts::11              75275                       # Per bank write bursts
system.physmem.perBankRdBursts::12              69111                       # Per bank write bursts
system.physmem.perBankRdBursts::13              75650                       # Per bank write bursts
system.physmem.perBankRdBursts::14              65166                       # Per bank write bursts
system.physmem.perBankRdBursts::15              73264                       # Per bank write bursts
system.physmem.perBankWrBursts::0               92929                       # Per bank write bursts
system.physmem.perBankWrBursts::1               92717                       # Per bank write bursts
system.physmem.perBankWrBursts::2               91280                       # Per bank write bursts
system.physmem.perBankWrBursts::3               89601                       # Per bank write bursts
system.physmem.perBankWrBursts::4               92792                       # Per bank write bursts
system.physmem.perBankWrBursts::5               94531                       # Per bank write bursts
system.physmem.perBankWrBursts::6               90574                       # Per bank write bursts
system.physmem.perBankWrBursts::7               91937                       # Per bank write bursts
system.physmem.perBankWrBursts::8               87601                       # Per bank write bursts
system.physmem.perBankWrBursts::9               94297                       # Per bank write bursts
system.physmem.perBankWrBursts::10              91232                       # Per bank write bursts
system.physmem.perBankWrBursts::11              93669                       # Per bank write bursts
system.physmem.perBankWrBursts::12              91213                       # Per bank write bursts
system.physmem.perBankWrBursts::13              96164                       # Per bank write bursts
system.physmem.perBankWrBursts::14              87189                       # Per bank write bursts
system.physmem.perBankWrBursts::15              93811                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         476                       # Number of times write queue was full causing retry
system.physmem.totGap                    51688739531000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1207335                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1471247                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1136082                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     64384                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       825                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       340                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       489                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       447                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       571                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       478                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       974                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       532                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      276                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      271                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      189                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      153                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      119                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       98                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       87                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       74                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    29717                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    37973                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    79220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    85555                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    88116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    84810                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    88690                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    87321                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    89133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    85642                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    88726                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    90107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    87724                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    84525                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    83639                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    82667                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    80351                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    80396                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2860                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2434                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1987                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1580                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1363                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1367                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1052                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      913                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      764                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      795                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      922                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      870                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      796                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      741                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      769                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                     1121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      726                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                     1082                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                     1526                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                     1562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      596                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                     1031                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       665465                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      257.565125                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     154.597276                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     293.769616                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         284377     42.73%     42.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       171033     25.70%     68.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        61820      9.29%     77.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        34355      5.16%     82.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        24207      3.64%     86.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        15228      2.29%     88.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        11511      1.73%     90.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9122      1.37%     91.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        53812      8.09%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         665465                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         77525                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        15.563805                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      141.518145                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          77523    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           77525                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         77525                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.981451                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.132244                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        8.585951                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           65037     83.89%     83.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            3875      5.00%     88.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            3091      3.99%     92.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31            2418      3.12%     96.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35            1125      1.45%     97.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             202      0.26%     97.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             259      0.33%     98.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47             156      0.20%     98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             148      0.19%     98.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              64      0.08%     98.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              86      0.11%     98.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              78      0.10%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             560      0.72%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              82      0.11%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75             101      0.13%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              77      0.10%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              43      0.06%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               5      0.01%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               4      0.01%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.00%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.00%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.00%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             4      0.01%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            18      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             5      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             7      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            20      0.03%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             6      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143            10      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             6      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             8      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           77525                       # Writes before turning the bus around for reads
system.physmem.totQLat                    38963077638                       # Total ticks spent queuing
system.physmem.totMemAccLat               61586883888                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6033015000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       32291.55                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  51041.55                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.49                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.82                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.49                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.82                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        27.17                       # Average write queue length when enqueuing
system.physmem.readRowHits                     937085                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1075589                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.66                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.09                       # Row buffer hit rate for writes
system.physmem.avgGap                     19278426.78                       # Average gap between requests
system.physmem.pageHitRate                      75.15                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2387508900                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1268991075                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4149403860                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3843804420                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           50777254320.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            43920274980                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             3215166720                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       97172465130                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy       73954032000                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       12292934061825                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             12573646841220                       # Total energy per rank (pJ)
system.physmem_0.averagePower              243.256974                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           51583978414040                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE     5941628250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     21591460000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   51178312983500                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 192588592528                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     77208837210                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 213097889512                       # Time in different power states
system.physmem_1.actEnergy                 2363918340                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1256448600                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4465741560                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3837618720                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           51996700080.000015                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            45282427920                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             3208431840                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       99358559340                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy       75199350240                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       12290630942340                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             12577622785650                       # Total energy per rank (pJ)
system.physmem_1.averagePower              243.333895                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           51581032449783                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE     5840657750                       # Time in different power states
system.physmem_1.memoryStateTime::REF     22110720000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   51167308964000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 195831815407                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     79757518717                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 217891715126                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           11                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             16                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst            14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               14                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           14                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               261998834                       # Number of BP lookups
system.cpu.branchPred.condPredicted         182856277                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12304668                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            193336179                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               130354436                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             67.423716                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                31812925                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2139415                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         7174940                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            5106056                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses          2068884                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       846506                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                    578626                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                578626                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        22326                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       190823                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples       578626                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0          578626    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       578626                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       213149                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 25594.731854                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 21754.484647                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 18075.189624                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       210684     98.84%     98.84% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         2067      0.97%     99.81% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607           93      0.04%     99.86% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143          125      0.06%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679          100      0.05%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           32      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751            7      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287            4      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359           34      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       213149                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    316311704                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       316311704    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    316311704                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        190824     89.53%     89.53% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         22326     10.47%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       213150                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       578626                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       578626                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       213150                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       213150                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       791776                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    182986827                       # DTB read hits
system.cpu.dtb.read_misses                     476580                       # DTB read misses
system.cpu.dtb.write_hits                   162437421                       # DTB write hits
system.cpu.dtb.write_misses                    102046                       # DTB write misses
system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               47208                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    80100                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                      1397                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                  15136                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     23302                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                183463407                       # DTB read accesses
system.cpu.dtb.write_accesses               162539467                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         345424248                       # DTB hits
system.cpu.dtb.misses                          578626                       # DTB misses
system.cpu.dtb.accesses                     346002874                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                    136092                       # Table walker walks requested
system.cpu.itb.walker.walksLong                136092                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1064                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       118204                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       136092                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          136092    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       136092                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       119268                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 28638.176208                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24049.001367                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 28797.920728                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       116455     97.64%     97.64% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071         2388      2.00%     99.64% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607          112      0.09%     99.74% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143           99      0.08%     99.82% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679           27      0.02%     99.84% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           23      0.02%     99.86% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751            4      0.00%     99.87% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            4      0.00%     99.87% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359          153      0.13%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       119268                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    315425204                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       315425204    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    315425204                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        118204     99.11%     99.11% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1064      0.89%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       119268                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       136092                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       136092                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       119268                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       119268                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       255360                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    453450761                       # ITB inst hits
system.cpu.itb.inst_misses                     136092                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               47208                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1111                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    57496                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    333218                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                453586853                       # ITB inst accesses
system.cpu.itb.hits                         453450761                       # DTB hits
system.cpu.itb.misses                          136092                       # DTB misses
system.cpu.itb.accesses                     453586853                       # DTB accesses
system.cpu.numPwrStateTransitions               33202                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples         16601                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     3037201042.152340                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    59610606886.622597                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows         7303     43.99%     43.99% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10         9263     55.80%     99.79% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.82% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            2      0.01%     99.83% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            2      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::6e+11-6.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::8.5e+11-9e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 1988777738856                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total           16601                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    1268166890229                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 50420574500771                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                       2536387791                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   948199503                       # Number of instructions committed
system.cpu.committedOps                    1114227092                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      98303819                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                      7741                       # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles                 100842203450                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi                               2.674952                       # CPI: cycles per instruction
system.cpu.ipc                               0.373839                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                   1      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu               772296777     69.31%     69.31% # Class of committed instruction
system.cpu.op_class_0::IntMult                2306158      0.21%     69.52% # Class of committed instruction
system.cpu.op_class_0::IntDiv                   98958      0.01%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     8      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                    13      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                    21      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc                 0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     69.53% # Class of committed instruction
system.cpu.op_class_0::FloatMisc               108924      0.01%     69.54% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     69.54% # Class of committed instruction
system.cpu.op_class_0::MemRead              177418599     15.92%     85.46% # Class of committed instruction
system.cpu.op_class_0::MemWrite             161212850     14.47%     99.93% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead            115060      0.01%     99.94% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite           669723      0.06%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total               1114227092                       # Class of committed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16601                       # number of quiesce instructions executed
system.cpu.tickCycles                      1794953387                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                       741434404                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements          11118153                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.954086                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           329643971                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          11118665                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.647801                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4655908500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.954086                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999910                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999910                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          391                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1383364255                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1383364255                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    168779255                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       168779255                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    151620030                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      151620030                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       521599                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        521599                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       337919                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       337919                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      4018497                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      4018497                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      4332994                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      4332994                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     320737204                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        320737204                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    321258803                       # number of overall hits
system.cpu.dcache.overall_hits::total       321258803                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      6105244                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       6105244                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      4304073                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      4304073                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1482683                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1482683                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1242865                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1242865                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       316228                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       316228                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     11652182                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       11652182                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     13134865                       # number of overall misses
system.cpu.dcache.overall_misses::total      13134865                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 107444842500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 107444842500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 170230992500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 170230992500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  27308613500                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  27308613500                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5074922000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   5074922000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        83000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        83000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 304984448500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 304984448500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 304984448500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 304984448500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    174884499                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    174884499                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    155924103                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    155924103                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      2004282                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      2004282                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1580784                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1580784                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4334725                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      4334725                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      4332995                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      4332995                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    332389386                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    332389386                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    334393668                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    334393668                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.034910                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.034910                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027604                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.027604                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.739758                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.739758                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786233                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.786233                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.072952                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.072952                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.035056                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.035056                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.039280                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.039280                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17598.779426                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.779426                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39551.139700                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39551.139700                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 21972.308738                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 21972.308738                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16048.300593                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16048.300593                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26174.020325                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26174.020325                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23219.458175                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23219.458175                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            5                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs            5                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      8530547                       # number of writebacks
system.cpu.dcache.writebacks::total           8530547                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       315482                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       315482                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1904891                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1904891                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          158                       # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total          158                       # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70720                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        70720                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2220531                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2220531                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2220531                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2220531                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5789762                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5789762                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2399182                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2399182                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1475215                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1475215                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1242707                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1242707                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       245508                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       245508                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9431651                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9431651                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data     10906866                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total     10906866                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33696                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33696                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67403                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  94938379000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  94938379000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  89047691000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  89047691000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  25686251500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  25686251500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  26061179000                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  26061179000                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3474287500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3474287500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        82000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        82000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 210047249000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 210047249000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 235733500500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 235733500500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6230847500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6230847500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6230847500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6230847500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033106                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033106                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015387                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015387                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.736032                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.736032                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786133                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786133                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.056638                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056638                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028375                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.028375                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032617                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.032617                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16397.630680                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16397.630680                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37115.854904                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37115.854904                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17411.869795                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17411.869795                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20971.298142                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20971.298142                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14151.422764                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14151.422764                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.464524                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.464524                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21613.312248                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21613.312248                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184913.565408                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184913.565408                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92441.693990                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92441.693990                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements          24600209                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.926335                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           428505873                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          24600721                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             17.418427                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       21430954500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.926335                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999856                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999856                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          118                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         477707334                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        477707334                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    428505873                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       428505873                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     428505873                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        428505873                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    428505873                       # number of overall hits
system.cpu.icache.overall_hits::total       428505873                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     24600731                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      24600731                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     24600731                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       24600731                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     24600731                       # number of overall misses
system.cpu.icache.overall_misses::total      24600731                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 330486746500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 330486746500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 330486746500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 330486746500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 330486746500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 330486746500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    453106604                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    453106604                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    453106604                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    453106604                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    453106604                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    453106604                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054293                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.054293                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.054293                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.054293                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.054293                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.054293                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13434.021391                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13434.021391                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13434.021391                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13434.021391                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13434.021391                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13434.021391                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks     24600209                       # number of writebacks
system.cpu.icache.writebacks::total          24600209                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24600731                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     24600731                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     24600731                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     24600731                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     24600731                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     24600731                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52291                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        52291                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52291                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        52291                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305886016500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 305886016500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305886016500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 305886016500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305886016500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 305886016500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   4421533000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   4421533000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   4421533000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   4421533000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054293                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054293                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054293                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.054293                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054293                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.054293                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12434.021432                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12434.021432                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12434.021432                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12434.021432                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12434.021432                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12434.021432                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 84556.290757                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 84556.290757                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 84556.290757                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 84556.290757                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements          1601564                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65405.294347                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           69675530                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1664947                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            41.848497                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       6255171000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  9201.337762                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   431.981496                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   403.879639                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  8049.770162                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 47318.325288                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.140401                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.006592                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006163                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.122830                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.722020                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.998006                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          257                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63126                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          257                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          260                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          803                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5965                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56053                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003922                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.963226                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        583673795                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       583673795                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       921476                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       260236                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1181712                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks      8530547                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      8530547                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks     24596465                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total     24596465                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data        29651                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        29651                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1663600                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1663600                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24492767                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     24492767                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7181719                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      7181719                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       699060                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       699060                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       921476                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       260236                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     24492767                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      8845319                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        34519798                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       921476                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       260236                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     24492767                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      8845319                       # number of overall hits
system.cpu.l2cache.overall_hits::total       34519798                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6194                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5168                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        11362                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         4020                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         4020                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       702193                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       702193                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       107963                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total       107963                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       328484                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       328484                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       543647                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       543647                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         6194                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         5168                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst       107963                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1030677                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1150002                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         6194                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         5168                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst       107963                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1030677                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1150002                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    927255500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    692143500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1619399000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     72892500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     72892500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        80500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total        80500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  67521066500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  67521066500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  11586638500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total  11586638500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  37187085000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  37187085000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    927255500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    692143500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  11586638500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 104708151500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 117914189000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    927255500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    692143500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  11586638500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 104708151500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 117914189000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       927670                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       265404                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1193074                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks      8530547                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      8530547                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks     24596465                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total     24596465                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        33671                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        33671                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2365793                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2365793                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24600730                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     24600730                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7510203                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      7510203                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1242707                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1242707                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       927670                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       265404                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     24600730                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9875996                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     35669800                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       927670                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       265404                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     24600730                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9875996                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     35669800                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006677                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.019472                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.009523                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.119391                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.119391                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.296811                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.296811                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004389                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004389                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043738                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043738                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.437470                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.437470                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006677                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.019472                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004389                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.104362                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.032240                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006677                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.019472                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004389                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.104362                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.032240                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 149702.211818                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133928.695820                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 142527.635980                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18132.462687                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18132.462687                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96157.418972                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96157.418972                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107320.457008                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107320.457008                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 113208.208010                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 113208.208010                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 149702.211818                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133928.695820                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107320.457008                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101591.625213                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 102533.899071                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 149702.211818                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133928.695820                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107320.457008                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101591.625213                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 102533.899071                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks      1364616                       # number of writebacks
system.cpu.l2cache.writebacks::total          1364616                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           23                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           23                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6194                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5168                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        11362                       # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            3                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total            3                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4020                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         4020                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       702193                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       702193                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       107961                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total       107961                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       328463                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       328463                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       543647                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       543647                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6194                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5168                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst       107961                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1030656                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1149979                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6194                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5168                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst       107961                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1030656                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1149979                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52291                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33696                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        85987                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52291                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119694                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    865315500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    640463500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1505779000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     76760000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     76760000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        70500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        70500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60499136001                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60499136001                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10506850003                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10506850003                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33899524045                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33899524045                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  11224464501                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  11224464501                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    865315500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    640463500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10506850003                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  94398660046                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 106411289049                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    865315500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    640463500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10506850003                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  94398660046                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 106411289049                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3611009000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5809544500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   9420553500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3611009000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5809544500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9420553500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006677                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.019472                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.009523                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.119391                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.119391                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.296811                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.296811                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004389                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004389                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043736                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043736                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.437470                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.437470                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006677                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.019472                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004389                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.104360                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.032240                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006677                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.019472                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004389                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.104360                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.032240                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123928.695820                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132527.635980                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19094.527363                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19094.527363                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86157.418261                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86157.418261                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97320.791795                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97320.791795                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103206.522637                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103206.522637                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20646.604324                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20646.604324                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123928.695820                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97320.791795                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91590.850920                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92533.245432                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123928.695820                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97320.791795                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91590.850920                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92533.245432                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69056.032587                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172410.508666                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109557.880842                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69056.032587                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86191.185852                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78705.311043                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests     72189026                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     36469595                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4452                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1946                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1946                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq        1780354                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      33892071                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33707                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33707                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      9895163                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean     24600209                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2824554                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        33674                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        33675                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2365793                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2365793                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     24600731                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      7513010                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1271678                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1242738                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     73906251                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     33558527                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       672286                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2215155                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total         110352219                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3152206656                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1178259346                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2123232                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7421360                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         4340010594                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     2135457                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic              91396008                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples     39200512                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.018468                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.134637                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           38476553     98.15%     98.15% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             723959      1.85%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       39200512                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    69790374998                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1501881                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   36983722099                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   15503705051                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     406910942                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1287502964                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40334                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40334                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231026                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231026                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353810                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492456                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             37695500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               339500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               16000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25148500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36444000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           569308376                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147786000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115495                       # number of replacements
system.iocache.tags.tagsinuse               10.448162                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115511                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13141692173000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.519394                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.928768                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219962                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.433048                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653010                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039974                       # Number of tag accesses
system.iocache.tags.data_accesses             1039974                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8849                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8886                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115513                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115553                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115513                       # number of overall misses
system.iocache.overall_misses::total           115553                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5085500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   2011459152                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   2016544652                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13390572724                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13390572724                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5436500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  15402031876                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  15407468376                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5436500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  15402031876                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  15407468376                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8849                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8886                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115513                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115553                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115513                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115553                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 227309.204656                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 226935.027234                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125539.757781                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125539.757781                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 133335.917827                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 133336.809741                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 133335.917827                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 133336.809741                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         51202                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3365                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    15.216048                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8849                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8886                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115513                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115553                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115513                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115553                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3235500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1569009152                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1572244652                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8051866391                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8051866391                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3436500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9620875543                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9624312043                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3436500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9620875543                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9624312043                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177309.204656                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 176935.027234                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75488.134619                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75488.134619                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 83288.249314                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 83289.157728                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 83288.249314                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 83289.157728                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests       3529625                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      1749962                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3622                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               85987                       # Transaction distribution
system.membus.trans_dist::ReadResp             542659                       # Transaction distribution
system.membus.trans_dist::WriteReq              33707                       # Transaction distribution
system.membus.trans_dist::WriteResp             33707                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1471247                       # Transaction distribution
system.membus.trans_dist::CleanEvict           244702                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4583                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               7                       # Transaction distribution
system.membus.trans_dist::ReadExReq            701633                       # Transaction distribution
system.membus.trans_dist::ReadExResp           701633                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        456672                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        650311                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        28814                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4556598                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4686250                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237342                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237342                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4923592                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13832                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    164222764                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    164393170                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7227200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7227200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               171620370                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            32071                       # Total snoops (count)
system.membus.snoopTraffic                     208000                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           1932895                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.016796                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.128505                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 1900431     98.32%     98.32% # Request fanout histogram
system.membus.snoop_fanout::1                   32464      1.68%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             1932895                       # Request fanout histogram
system.membus.reqLayer0.occupancy            99728500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18828                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5568000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9720767792                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         6477610584                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           75150025                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------
