
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.517298                       # Number of seconds simulated
sim_ticks                                517297855500                       # Number of ticks simulated
final_tick                               517297855500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1075622                       # Simulator instruction rate (inst/s)
host_op_rate                                  1291325                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2040106124                       # Simulator tick rate (ticks/s)
host_mem_usage                                 278152                       # Number of bytes of host memory used
host_seconds                                   253.56                       # Real time elapsed on the host
sim_insts                                   272739286                       # Number of instructions simulated
sim_ops                                     327433744                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            166912                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            270336                       # Number of bytes read from this memory
system.physmem.bytes_read::total               437248                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       166912                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          166912                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               2608                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               4224                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  6832                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst               322661                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               522593                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                  845254                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          322661                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             322661                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              322661                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              522593                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                 845254                       # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  191                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    517297855500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                       1034595711                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   272739286                       # Number of instructions committed
system.cpu.committedOps                     327433744                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             258331537                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
system.cpu.num_func_calls                    12448615                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     15799349                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    258331537                       # number of integer instructions
system.cpu.num_fp_insts                     114216705                       # number of float instructions
system.cpu.num_int_register_reads           979511506                       # number of times the integer registers were read
system.cpu.num_int_register_writes          162499693                       # number of times the integer registers were written
system.cpu.num_fp_register_reads            180262959                       # number of times the floating registers were read
system.cpu.num_fp_register_writes           126152315                       # number of times the floating registers were written
system.cpu.num_cc_register_reads           1242915503                       # number of times the CC registers were read
system.cpu.num_cc_register_writes            76361814                       # number of times the CC registers were written
system.cpu.num_mem_refs                     168107847                       # number of memory refs
system.cpu.num_load_insts                    85732248                       # Number of load instructions
system.cpu.num_store_insts                   82375599                       # Number of store instructions
system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
system.cpu.num_busy_cycles               1034595710.998000                       # Number of busy cycles
system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
system.cpu.Branches                          30563503                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                 104312544     31.82%     31.82% # Class of executed instruction
system.cpu.op_class::IntMult                  2145905      0.65%     32.48% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatMultAcc                   0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatMisc                      0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     32.48% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd             6594343      2.01%     34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp             7943502      2.42%     36.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt             3118180      0.95%     37.86% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv             1563217      0.48%     38.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc           19652356      6.00%     44.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMult            7136937      2.18%     46.51% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc         7062098      2.15%     48.66% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt             175285      0.05%     48.72% # Class of executed instruction
system.cpu.op_class::MemRead                 44185174     13.48%     62.20% # Class of executed instruction
system.cpu.op_class::MemWrite                55008381     16.78%     78.98% # Class of executed instruction
system.cpu.op_class::FloatMemRead            41547074     12.67%     91.65% # Class of executed instruction
system.cpu.op_class::FloatMemWrite           27367218      8.35%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                  327812214                       # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements              1332                       # number of replacements
system.cpu.dcache.tags.tagsinuse          3078.320204                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           168359617                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              4478                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          37597.056052                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  3078.320204                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.751543                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.751543                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         3146                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           10                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3          677                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         2428                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.768066                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         336732670                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        336732670                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     86233963                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        86233963                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     82049805                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       82049805                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        54059                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         54059                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     168283768                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168283768                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    168337827                       # number of overall hits
system.cpu.dcache.overall_hits::total       168337827                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         1604                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          1604                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         2872                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         2872                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data            3                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total            3                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data         4476                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           4476                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         4479                       # number of overall misses
system.cpu.dcache.overall_misses::total          4479                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     89418000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     89418000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    180278500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    180278500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    269696500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    269696500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    269696500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    269696500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     86235567                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     86235567                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data        54062                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total        54062                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    168288244                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    168288244                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    168342306                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    168342306                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000019                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000019                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000035                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000035                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000055                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.000055                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000027                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000027                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000027                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000027                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55746.882793                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55746.882793                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62771.065460                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 62771.065460                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60253.909741                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 60253.909741                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60213.552132                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60213.552132                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks          998                       # number of writebacks
system.cpu.dcache.writebacks::total               998                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1603                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total         1603                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2872                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         2872                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         4475                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         4475                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         4478                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         4478                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     87767000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     87767000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    177406500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    177406500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       186000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       186000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    265173500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    265173500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    265359500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    265359500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000055                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000055                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54751.715533                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54751.715533                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61771.065460                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61771.065460                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        62000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        62000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59256.648045                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59256.648045                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59258.485931                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59258.485931                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements             13796                       # number of replacements
system.cpu.icache.tags.tagsinuse          1765.939670                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           348644750                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             15603                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          22344.725373                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1765.939670                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.862275                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.862275                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1807                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          161                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1524                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.882324                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         697336309                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        697336309                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    348644750                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       348644750                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     348644750                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        348644750                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    348644750                       # number of overall hits
system.cpu.icache.overall_hits::total       348644750                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        15603                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         15603                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        15603                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          15603                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        15603                       # number of overall misses
system.cpu.icache.overall_misses::total         15603                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    341054000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    341054000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    341054000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    341054000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    341054000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    341054000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    348660353                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    348660353                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    348660353                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    348660353                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    348660353                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    348660353                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000045                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000045                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21858.232391                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21858.232391                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21858.232391                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21858.232391                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21858.232391                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21858.232391                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks        13796                       # number of writebacks
system.cpu.icache.writebacks::total             13796                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15603                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        15603                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        15603                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        15603                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        15603                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        15603                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    325451000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    325451000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    325451000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    325451000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    325451000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    325451000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20858.232391                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20858.232391                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20858.232391                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20858.232391                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20858.232391                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20858.232391                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         5901.352793                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              20712                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             6832                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             3.031616                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2407.314356                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  3494.038437                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073465                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.106630                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.180095                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         6832                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          758                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         5967                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.208496                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses           227184                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses          227184                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks          998                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total          998                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks         6212                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total         6212                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           16                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        12995                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        12995                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data          238                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total          238                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        12995                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data          254                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           13249                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        12995                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data          254                       # number of overall hits
system.cpu.l2cache.overall_hits::total          13249                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data         2856                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2856                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2608                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         2608                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1368                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total         1368                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2608                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         4224                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          6832                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2608                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         4224                       # number of overall misses
system.cpu.l2cache.overall_misses::total         6832                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    172926500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    172926500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    157900000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    157900000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     82959000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total     82959000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    157900000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    255885500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    413785500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    157900000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    255885500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    413785500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks          998                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total          998                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks         6212                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total         6212                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         2872                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         2872                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        15603                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        15603                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data         1606                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total         1606                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        15603                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         4478                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        20081                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        15603                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         4478                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        20081                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994429                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.994429                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.167147                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.167147                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.851806                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.851806                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.167147                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.943278                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.340222                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.167147                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.943278                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.340222                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60548.494398                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60548.494398                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60544.478528                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60544.478528                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60642.543860                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60642.543860                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60544.478528                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60578.953598                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 60565.793326                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60544.478528                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60578.953598                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 60565.793326                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2856                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         2856                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2608                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2608                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1368                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1368                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2608                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         4224                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         6832                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2608                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         4224                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         6832                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    144366500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    144366500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    131820000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    131820000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     69279000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     69279000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    131820000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    213645500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    345465500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    131820000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    213645500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    345465500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994429                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994429                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.167147                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.851806                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.851806                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943278                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.340222                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943278                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.340222                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50548.494398                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50548.494398                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50544.478528                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50544.478528                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50642.543860                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50642.543860                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50544.478528                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50578.953598                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50565.793326                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50544.478528                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50578.953598                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50565.793326                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests        35209                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests        15221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7665                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp         17209                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty          998                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        13796                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict          334                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         2872                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         2872                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        15603                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq         1606                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        45002                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10288                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             55290                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1881536                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       350464                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total            2232000                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples        20081                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.386335                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.486921                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0              12323     61.37%     61.37% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               7758     38.63%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total          20081                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy       32398500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      23404500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       6717000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests          6833                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 517297855500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp               3976                       # Transaction distribution
system.membus.trans_dist::ReadExReq              2856                       # Transaction distribution
system.membus.trans_dist::ReadExResp             2856                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq          3976                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        13664                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  13664                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       437248                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  437248                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples              6833                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    6833    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                6833                       # Request fanout histogram
system.membus.reqLayer0.occupancy             7281500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           34160000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
