
---------- Begin Simulation Statistics ----------
sim_seconds                                  5.898831                       # Number of seconds simulated
sim_ticks                                5898831348500                       # Number of ticks simulated
final_tick                               5898831348500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1175665                       # Simulator instruction rate (inst/s)
host_op_rate                                  1831792                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2305472192                       # Simulator tick rate (ticks/s)
host_mem_usage                                 275096                       # Number of bytes of host memory used
host_seconds                                  2558.62                       # Real time elapsed on the host
sim_insts                                  3008081022                       # Number of instructions simulated
sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             43200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         126068992                       # Number of bytes read from this memory
system.physmem.bytes_read::total            126112192                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        43200                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           43200                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     66108032                       # Number of bytes written to this memory
system.physmem.bytes_written::total          66108032                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                675                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1969828                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1970503                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1032938                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1032938                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                 7323                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             21371859                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                21379183                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst            7323                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total               7323                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          11206971                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               11206971                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          11206971                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst                7323                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            21371859                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               32586154                       # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    5898831348500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                      11797662697                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  3008081022                       # Number of instructions committed
system.cpu.committedOps                    4686862596                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses            4684368009                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                    33534539                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    182173300                       # number of instructions that are conditional controls
system.cpu.num_int_insts                   4684368009                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads         10688755601                       # number of times the integer registers were read
system.cpu.num_int_register_writes         3999841477                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads           1226718827                       # number of times the CC registers were read
system.cpu.num_cc_register_writes          1355930461                       # number of times the CC registers were written
system.cpu.num_mem_refs                    1677713084                       # number of memory refs
system.cpu.num_load_insts                  1239184746                       # Number of load instructions
system.cpu.num_store_insts                  438528338                       # Number of store instructions
system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
system.cpu.num_busy_cycles               11797662696.997999                       # Number of busy cycles
system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
system.cpu.Branches                         248500691                       # Number of branches fetched
system.cpu.op_class::No_OpClass               2494522      0.05%      0.05% # Class of executed instruction
system.cpu.op_class::IntAlu                3006647871     64.15%     64.20% # Class of executed instruction
system.cpu.op_class::IntMult                     6215      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::IntDiv                       904      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::FloatMultAcc                   0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::FloatMisc                      0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.20% # Class of executed instruction
system.cpu.op_class::MemRead               1239184746     26.44%     90.64% # Class of executed instruction
system.cpu.op_class::MemWrite               438528338      9.36%    100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite                  0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                 4686862596                       # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           9108581                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4084.589706                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs          1668600407                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9112677                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            183.107599                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle       58922805500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4084.589706                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997214                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997214                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          898                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2768                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3          329                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4            2                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        3364538845                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       3364538845                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data   1231961896                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total      1231961896                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    436638511                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      436638511                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data    1668600407                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total       1668600407                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data   1668600407                       # number of overall hits
system.cpu.dcache.overall_hits::total      1668600407                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      7222850                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       7222850                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1889827                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1889827                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      9112677                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9112677                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9112677                       # number of overall misses
system.cpu.dcache.overall_misses::total       9112677                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 152690255000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  64265951000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  64265951000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 216956206000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 216956206000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 216956206000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 216956206000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data   1239184746                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total   1239184746                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    438528338                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    438528338                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data   1677713084                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total   1677713084                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data   1677713084                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total   1677713084                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.005829                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.005829                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.004309                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.004309                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.005432                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.005432                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.005432                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.005432                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23808.174700                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23808.174700                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      3669049                       # number of writebacks
system.cpu.dcache.writebacks::total           3669049                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222850                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7222850                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889827                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1889827                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9112677                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9112677                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9112677                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9112677                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  62376124000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  62376124000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 207843529000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 207843529000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.005829                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.005829                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.004309                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.004309                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005432                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.005432                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005432                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.005432                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                10                       # number of replacements
system.cpu.icache.tags.tagsinuse           555.760511                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs          4013232207                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               675                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          5945529.195556                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   555.760511                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.271367                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.271367                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          665                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          632                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.324707                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses        8026466439                       # Number of tag accesses
system.cpu.icache.tags.data_accesses       8026466439                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst   4013232207                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total      4013232207                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst    4013232207                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total       4013232207                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst   4013232207                       # number of overall hits
system.cpu.icache.overall_hits::total      4013232207                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          675                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           675                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          675                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            675                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          675                       # number of overall misses
system.cpu.icache.overall_misses::total           675                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     42528500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     42528500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     42528500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     42528500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     42528500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     42528500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst   4013232882                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total   4013232882                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst   4013232882                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total   4013232882                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst   4013232882                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total   4013232882                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 63005.185185                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 63005.185185                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks           10                       # number of writebacks
system.cpu.icache.writebacks::total                10                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          675                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          675                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          675                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          675                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          675                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     41853500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     41853500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     41853500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     41853500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     41853500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     41853500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements          1938075                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        31745.660470                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           16250887                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1970843                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             8.245653                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     320350195000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks    11.856683                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.308015                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.000362                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000772                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.967666                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.968801                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          435                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3097                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          786                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        28399                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        147746387                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       147746387                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks      3669049                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      3669049                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks           10                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total           10                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1095863                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1095863                       # number of ReadExReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6046986                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      6046986                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data      7142849                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7142849                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data      7142849                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7142849                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       793964                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       793964                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          675                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          675                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1175864                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total      1175864                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          675                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1969828                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1970503                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          675                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1969828                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1970503                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  48034822000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  48034822000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     40839500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     40839500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  71139776000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  71139776000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     40839500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 119215437500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     40839500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 119215437500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      3669049                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      3669049                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks           10                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total           10                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889827                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1889827                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          675                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          675                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7222850                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      7222850                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          675                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9112677                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9113352                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          675                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9112677                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9113352                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.420125                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.420125                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162798                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162798                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.216163                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.216222                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.216163                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.216222                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        60500                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        60500                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.962963                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks      1032938                       # number of writebacks
system.cpu.l2cache.writebacks::total          1032938                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          213                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          213                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       793964                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       793964                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          675                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          675                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1175864                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1175864                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          675                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1969828                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1970503                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1969828                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1970503                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  40095182000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  40095182000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     34089500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     34089500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  59381136000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  59381136000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     34089500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  99476318000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  99510407500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     34089500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  99476318000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  99510407500                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.420125                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.420125                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162798                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162798                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216163                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.216222                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216163                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.216222                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        50500                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        50500                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests     18221943                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      9108591                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1186                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1186                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp       7223525                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      4701987                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean           10                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      6344669                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1889827                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1889827                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          675                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      7222850                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1360                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27333935                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          27335295                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        43840                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    818030464                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          818074304                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     1938075                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic              66108032                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples     11051427                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.000107                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.010359                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           11050241     99.99%     99.99% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               1186      0.01%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       11051427                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    12780030500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1012500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13669015500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests       3907605                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      1937102                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp            1176539                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1032938                       # Transaction distribution
system.membus.trans_dist::CleanEvict           904164                       # Transaction distribution
system.membus.trans_dist::ReadExReq            793964                       # Transaction distribution
system.membus.trans_dist::ReadExResp           793964                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq       1176539                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5878108                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5878108                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5878108                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    192220224                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    192220224                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               192220224                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           1970503                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 1970503    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total             1970503                       # Request fanout histogram
system.membus.reqLayer0.occupancy          8039359500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         9852515000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
