# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder.  You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black

microcode = '''
def macroop BSR_R_R {
    # Determine if the input was zero, and also move it to a temp reg.
    mov t1, t1, t0, dataSize=8
    and t1, regm, regm, flags=(ZF,)
    br label("end"), flags=(CZF,)

    # Zero out the result register
    movi reg, reg, 0x0

    # Bit 6
    srli t3, t1, 32, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x20
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 5
    srli t3, t1, 16, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x10
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 4
    srli t3, t1, 8, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x8
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 3
    srli t3, t1, 4, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x4
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 2
    srli t3, t1, 2, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x2
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 1
    srli t3, t1, 1, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x1
    mov reg, reg, t4, flags=(nCEZF,)

end:
    fault "NoFault"
};

def macroop BSR_R_M {

    mov t1, t1, t0, dataSize=8
    ld t1, seg, sib, disp

    # Determine if the input was zero, and also move it to a temp reg.
    and t1, t1, t1, flags=(ZF,)
    br label("end"), flags=(CZF,)

    # Zero out the result register
    movi reg, reg, 0x0

    # Bit 6
    srli t3, t1, 32, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x20
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 5
    srli t3, t1, 16, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x10
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 4
    srli t3, t1, 8, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x8
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 3
    srli t3, t1, 4, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x4
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 2
    srli t3, t1, 2, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x2
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 1
    srli t3, t1, 1, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x1
    mov reg, reg, t4, flags=(nCEZF,)

end:
    fault "NoFault"
};

def macroop BSR_R_P {

    rdip t7
    mov t1, t1, t0, dataSize=8
    ld t1, seg, riprel, disp

    # Determine if the input was zero, and also move it to a temp reg.
    and t1, t1, t1, flags=(ZF,)
    br label("end"), flags=(CZF,)

    # Zero out the result register
    movi reg, reg, 0x0

    # Bit 6
    srli t3, t1, 32, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x20
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 5
    srli t3, t1, 16, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x10
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 4
    srli t3, t1, 8, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x8
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 3
    srli t3, t1, 4, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x4
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 2
    srli t3, t1, 2, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x2
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 1
    srli t3, t1, 1, dataSize=8, flags=(EZF,)
    ori t4, reg, 0x1
    mov reg, reg, t4, flags=(nCEZF,)

end:
    fault "NoFault"
};

def macroop BSF_R_R {
    # Determine if the input was zero, and also move it to a temp reg.
    mov t1, t1, t0, dataSize=8
    and t1, regm, regm, flags=(ZF,)
    br label("end"), flags=(CZF,)

    # Zero out the result register
    movi reg, reg, 0

    subi t2, t1, 1
    xor t1, t2, t1


    # Bit 6
    srli t3, t1, 32, dataSize=8, flags=(EZF,)
    ori t4, reg, 32
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 5
    srli t3, t1, 16, dataSize=8, flags=(EZF,)
    ori t4, reg, 16
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 4
    srli t3, t1, 8, dataSize=8, flags=(EZF,)
    ori t4, reg, 8
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 3
    srli t3, t1, 4, dataSize=8, flags=(EZF,)
    ori t4, reg, 4
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 2
    srli t3, t1, 2, dataSize=8, flags=(EZF,)
    ori t4, reg, 2
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 1
    srli t3, t1, 1, dataSize=8, flags=(EZF,)
    ori t4, reg, 1
    mov reg, reg, t4, flags=(nCEZF,)

end:
    fault "NoFault"
};

def macroop BSF_R_M {

    mov t1, t1, t0, dataSize=8
    ld t1, seg, sib, disp

    # Determine if the input was zero, and also move it to a temp reg.
    and t1, t1, t1, flags=(ZF,)
    br label("end"), flags=(CZF,)

    # Zero out the result register
    mov reg, reg, t0

    subi t2, t1, 1
    xor t1, t2, t1

    # Bit 6
    srli t3, t1, 32, dataSize=8, flags=(EZF,)
    ori t4, reg, 32
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 5
    srli t3, t1, 16, dataSize=8, flags=(EZF,)
    ori t4, reg, 16
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 4
    srli t3, t1, 8, dataSize=8, flags=(EZF,)
    ori t4, reg, 8
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 3
    srli t3, t1, 4, dataSize=8, flags=(EZF,)
    ori t4, reg, 4
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 2
    srli t3, t1, 2, dataSize=8, flags=(EZF,)
    ori t4, reg, 2
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 1
    srli t3, t1, 1, dataSize=8, flags=(EZF,)
    ori t4, reg, 1
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

end:
    fault "NoFault"
};

def macroop BSF_R_P {

    rdip t7
    mov t1, t1, t0, dataSize=8
    ld t1, seg, riprel, disp

    # Determine if the input was zero, and also move it to a temp reg.
    and t1, t1, t1, flags=(ZF,)
    br label("end"), flags=(CZF,)

    # Zero out the result register
    mov reg, reg, t0

    subi t2, t1, 1
    xor t1, t2, t1

    # Bit 6
    srli t3, t1, 32, dataSize=8, flags=(EZF,)
    ori t4, reg, 32
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 5
    srli t3, t1, 16, dataSize=8, flags=(EZF,)
    ori t4, reg, 16
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 4
    srli t3, t1, 8, dataSize=8, flags=(EZF,)
    ori t4, reg, 8
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 3
    srli t3, t1, 4, dataSize=8, flags=(EZF,)
    ori t4, reg, 4
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 2
    srli t3, t1, 2, dataSize=8, flags=(EZF,)
    ori t4, reg, 2
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

    # Bit 1
    srli t3, t1, 1, dataSize=8, flags=(EZF,)
    ori t4, reg, 1
    mov reg, reg, t4, flags=(nCEZF,)
    mov t1, t1, t3, flags=(nCEZF,)

end:
    fault "NoFault"
};
'''
