
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.065833                       # Number of seconds simulated
sim_ticks                                 65832730500                       # Number of ticks simulated
final_tick                                65832730500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 190384                       # Simulator instruction rate (inst/s)
host_op_rate                                   335236                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               79331786                       # Simulator tick rate (ticks/s)
host_mem_usage                                 416808                       # Number of bytes of host memory used
host_seconds                                   829.84                       # Real time elapsed on the host
sim_insts                                   157988547                       # Number of instructions simulated
sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             69952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           1892544                       # Number of bytes read from this memory
system.physmem.bytes_read::total              1962496                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        69952                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           69952                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks        19776                       # Number of bytes written to this memory
system.physmem.bytes_written::total             19776                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               1093                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              29571                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 30664                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks             309                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                  309                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              1062572                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             28747767                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                29810339                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1062572                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1062572                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks            300398                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                 300398                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks            300398                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1062572                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            28747767                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               30110736                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         30664                       # Number of read requests accepted
system.physmem.writeReqs                          309                       # Number of write requests accepted
system.physmem.readBursts                       30664                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                        309                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  1954304                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8192                       # Total number of bytes read from write queue
system.physmem.bytesWritten                     18368                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   1962496                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                  19776                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      128                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                1947                       # Per bank write bursts
system.physmem.perBankRdBursts::1                2076                       # Per bank write bursts
system.physmem.perBankRdBursts::2                2053                       # Per bank write bursts
system.physmem.perBankRdBursts::3                1954                       # Per bank write bursts
system.physmem.perBankRdBursts::4                2067                       # Per bank write bursts
system.physmem.perBankRdBursts::5                1911                       # Per bank write bursts
system.physmem.perBankRdBursts::6                1975                       # Per bank write bursts
system.physmem.perBankRdBursts::7                1868                       # Per bank write bursts
system.physmem.perBankRdBursts::8                1952                       # Per bank write bursts
system.physmem.perBankRdBursts::9                1938                       # Per bank write bursts
system.physmem.perBankRdBursts::10               1805                       # Per bank write bursts
system.physmem.perBankRdBursts::11               1794                       # Per bank write bursts
system.physmem.perBankRdBursts::12               1792                       # Per bank write bursts
system.physmem.perBankRdBursts::13               1799                       # Per bank write bursts
system.physmem.perBankRdBursts::14               1826                       # Per bank write bursts
system.physmem.perBankRdBursts::15               1779                       # Per bank write bursts
system.physmem.perBankWrBursts::0                  25                       # Per bank write bursts
system.physmem.perBankWrBursts::1                 120                       # Per bank write bursts
system.physmem.perBankWrBursts::2                  28                       # Per bank write bursts
system.physmem.perBankWrBursts::3                  32                       # Per bank write bursts
system.physmem.perBankWrBursts::4                  54                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   2                       # Per bank write bursts
system.physmem.perBankWrBursts::6                  17                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   6                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  3                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     65832525500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   30664                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                    309                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     29955                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       437                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       101                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         2862                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      688.995108                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     484.121076                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     395.829774                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            415     14.50%     14.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          275      9.61%     24.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383          149      5.21%     29.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511          128      4.47%     33.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          140      4.89%     38.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          122      4.26%     42.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           77      2.69%     45.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           86      3.00%     48.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         1470     51.36%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           2862                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples            16                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      1905.625000                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       24.516989                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     7552.373489                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023             15     93.75%     93.75% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::29696-30719            1      6.25%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total              16                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples            16                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.937500                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.914548                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.928709                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16                  2     12.50%     12.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                 12     75.00%     87.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                  1      6.25%     93.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                  1      6.25%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total              16                       # Writes before turning the bus around for reads
system.physmem.totQLat                      411710000                       # Total ticks spent queuing
system.physmem.totMemAccLat                 984260000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    152680000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13482.77                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  32232.77                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          29.69                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.28                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       29.81                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.30                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.23                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.23                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        14.03                       # Average write queue length when enqueuing
system.physmem.readRowHits                      27751                       # Number of row buffer hits during reads
system.physmem.writeRowHits                       206                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.88                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  66.67                       # Row buffer hit rate for writes
system.physmem.avgGap                      2125481.08                       # Average gap between requests
system.physmem.pageHitRate                      90.64                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                   11059860                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    5878455                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 113176140                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                  1451160                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           315310320.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy              256763340                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy               17698560                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy         981638610                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy         270128640                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy        15008515620                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy              16981623105                       # Total energy per rank (pJ)
system.physmem_0.averagePower              257.950589                       # Core power per rank (mW)
system.physmem_0.totalIdleTime            65223686000                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE       24830750                       # Time in different power states
system.physmem_0.memoryStateTime::REF       133713250                       # Time in different power states
system.physmem_0.memoryStateTime::SREF    62367507500                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN    703478750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT       450500500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN   2152699750                       # Time in different power states
system.physmem_1.actEnergy                    9403380                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    4982835                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 104850900                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                    46980                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           389067120.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy              256987920                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy               20546880                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy        1156119600                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy         409490400                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy        14841811380                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy              17194149375                       # Total energy per rank (pJ)
system.physmem_1.averagePower              261.179341                       # Core power per rank (mW)
system.physmem_1.totalIdleTime            65212352000                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE       31901000                       # Time in different power states
system.physmem_1.memoryStateTime::REF       165222000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF    61612056250                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN   1066374000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT       421666750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN   2535510500                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                40426123                       # Number of BP lookups
system.cpu.branchPred.condPredicted          40426123                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1402729                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             26580139                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 6011508                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              87453                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups        26580139                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits           21161652                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses          5418487                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       517301                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls                  444                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON     65832730500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        131665462                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           30553171                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      219967171                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    40426123                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           27173160                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      99460538                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2919977                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                        306                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                 5927                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        105822                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles           73                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          157                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  29763575                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                354176                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                      15                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          131585982                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.941987                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.406730                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 65985920     50.15%     50.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  4028379      3.06%     53.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  3611314      2.74%     55.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  6113229      4.65%     60.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  7745533      5.89%     66.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  5553246      4.22%     70.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  3377028      2.57%     73.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  2847646      2.16%     75.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 32323687     24.56%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            131585982                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.307037                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.670652                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 15243618                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              64765794                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  40224064                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               9892518                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1459988                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              362269877                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                1459988                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 20789530                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                11237370                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          18362                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  44279240                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              53801492                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              352719757                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 16498                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 793095                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               46882908                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                5193491                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           355158766                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             934950269                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        575705414                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             24139                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 75946019                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                487                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            484                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  64820498                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            112428453                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            38501164                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          51645718                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          9056873                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  344114716                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                4351                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 317908509                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            166833                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        65926603                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    102202913                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           3906                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     131585982                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.415976                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.164934                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            35686444     27.12%     27.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            20105227     15.28%     42.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            17162197     13.04%     55.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            17623881     13.39%     68.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            15350950     11.67%     80.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            12863479      9.78%     90.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             6692822      5.09%     95.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             4078738      3.10%     98.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             2022244      1.54%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       131585982                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  364988      8.91%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc                    0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.91% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                3541451     86.44%     95.35% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                188937      4.61%     99.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead                10      0.00%     99.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite             1524      0.04%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass             33340      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             181836417     57.20%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                11458      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                   362      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 334      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     57.21% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            101309174     31.87%     89.08% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            34711229     10.92%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead             553      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite           5642      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              317908509                       # Type of FU issued
system.cpu.iq.rate                           2.414517                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     4096910                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.012887                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          771648435                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         410069961                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    313720076                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               18308                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              36184                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         4316                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              321964016                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                    8063                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         57535034                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     21649068                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        67666                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        63141                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      7061412                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         4025                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        141941                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1459988                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 8072611                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               3068372                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           344119067                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            127232                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             112428453                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             38501164                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               1782                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   2921                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               3074772                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          63141                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         534039                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      1041947                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1575986                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             315496434                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             100557512                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2412075                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    134869578                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 32108537                       # Number of branches executed
system.cpu.iew.exec_stores                   34312066                       # Number of stores executed
system.cpu.iew.exec_rate                     2.396197                       # Inst execution rate
system.cpu.iew.wb_sent                      314359591                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     313724392                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 237724315                       # num instructions producing a value
system.cpu.iew.wb_consumers                 343443925                       # num instructions consuming a value
system.cpu.iew.wb_rate                       2.382739                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.692178                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        66051294                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1408834                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    122136825                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.277712                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     3.048100                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     57021615     46.69%     46.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     16508640     13.52%     60.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     11210798      9.18%     69.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      8746505      7.16%     76.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2078517      1.70%     78.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1759712      1.44%     79.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       926228      0.76%     80.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       725763      0.59%     81.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     23159047     18.96%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    122136825                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      122219137                       # Number of memory references committed
system.cpu.commit.loads                      90779385                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   29309705                       # Number of branches committed
system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 278169481                       # Number of committed integer instructions.
system.cpu.commit.function_calls              4237596                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass        16695      0.01%      0.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        155945353     56.06%     56.06% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           10938      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv              329      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd             12      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc             0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.07% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        90779371     32.63%     88.70% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       31439738     11.30%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead           14      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite           14      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
system.cpu.commit.bw_lim_events              23159047                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    443221536                       # The number of ROB reads
system.cpu.rob.rob_writes                   698006714                       # The number of ROB writes
system.cpu.timesIdled                             877                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           79480                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.833386                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.833386                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.199924                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.199924                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                502917784                       # number of integer regfile reads
system.cpu.int_regfile_writes               247848787                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      4075                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      819                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 109098841                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 65494445                       # number of cc regfile writes
system.cpu.misc_regfile_reads               201957201                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           2073306                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4067.354566                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            71520008                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2077402                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             34.427621                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle       21024099500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4067.354566                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993006                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993006                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          500                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         3447                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         150691296                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        150691296                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     40173982                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        40173982                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     31346026                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       31346026                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      71520008                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         71520008                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     71520008                       # number of overall hits
system.cpu.dcache.overall_hits::total        71520008                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2693213                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2693213                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        93726                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        93726                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2786939                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2786939                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2786939                       # number of overall misses
system.cpu.dcache.overall_misses::total       2786939                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  32416728500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  32416728500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   3181034987                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   3181034987                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  35597763487                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  35597763487                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  35597763487                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  35597763487                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     42867195                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     42867195                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     74306947                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     74306947                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     74306947                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     74306947                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.062827                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.062827                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002981                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.002981                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037506                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037506                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037506                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037506                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12036.451814                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 12036.451814                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33939.728432                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33939.728432                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12773.068764                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 12773.068764                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12773.068764                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12773.068764                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       220832                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          385                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             43178                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.114456                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    96.250000                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      2066926                       # number of writebacks
system.cpu.dcache.writebacks::total           2066926                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       697625                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       697625                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11912                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        11912                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       709537                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       709537                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       709537                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       709537                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1995588                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1995588                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        81814                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        81814                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2077402                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2077402                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2077402                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2077402                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24271228500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  24271228500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3023849487                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   3023849487                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27295077987                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  27295077987                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27295077987                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  27295077987                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046553                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046553                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002602                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002602                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027957                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.027957                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027957                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.027957                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.444603                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.444603                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36960.049466                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36960.049466                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13139.044820                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13139.044820                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13139.044820                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13139.044820                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                93                       # number of replacements
system.cpu.icache.tags.tagsinuse           878.108473                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            29762089                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              1121                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          26549.588760                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   878.108473                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.428764                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.428764                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1028                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           38                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          910                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.501953                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          59528269                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         59528269                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     29762089                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        29762089                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      29762089                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         29762089                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     29762089                       # number of overall hits
system.cpu.icache.overall_hits::total        29762089                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         1485                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          1485                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         1485                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           1485                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         1485                       # number of overall misses
system.cpu.icache.overall_misses::total          1485                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    149774999                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    149774999                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    149774999                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    149774999                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    149774999                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    149774999                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     29763574                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     29763574                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     29763574                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     29763574                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     29763574                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     29763574                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000050                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000050                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000050                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000050                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000050                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000050                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100858.585185                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 100858.585185                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 100858.585185                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 100858.585185                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 100858.585185                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 100858.585185                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         2965                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                14                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs   211.785714                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks           93                       # number of writebacks
system.cpu.icache.writebacks::total                93                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          364                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          364                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          364                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          364                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          364                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          364                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1121                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         1121                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         1121                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         1121                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         1121                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         1121                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    114880499                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    114880499                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    114880499                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    114880499                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    114880499                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    114880499                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000038                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000038                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000038                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000038                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000038                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000038                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 102480.373773                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 102480.373773                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 102480.373773                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 102480.373773                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 102480.373773                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 102480.373773                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements              694                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        21678.088627                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4121221                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs            30681                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs           134.324859                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks     2.638364                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   712.370564                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 20963.079700                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.000081                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.021740                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.639742                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.661563                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        29987                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          186                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29624                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.915131                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         33245897                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        33245897                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks      2066926                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      2066926                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks           93                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total           93                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data        52858                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total        52858                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           28                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total           28                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1994973                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1994973                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst           28                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2047831                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2047859                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           28                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2047831                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2047859                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data        28990                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        28990                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1093                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         1093                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data          581                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total          581                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         1093                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        29571                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         30664                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         1093                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        29571                       # number of overall misses
system.cpu.l2cache.overall_misses::total        30664                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2345791000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   2345791000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    112890000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    112890000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     92689500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total     92689500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    112890000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   2438480500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   2551370500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    112890000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   2438480500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   2551370500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      2066926                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      2066926                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks           93                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total           93                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        81848                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        81848                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1121                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total         1121                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1995554                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1995554                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         1121                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2077402                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2078523                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         1121                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2077402                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2078523                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.354193                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.354193                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.975022                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.975022                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000291                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000291                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.975022                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.014235                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.014753                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.975022                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.014235                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.014753                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80917.247327                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80917.247327                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103284.537969                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103284.537969                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 159534.423408                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 159534.423408                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103284.537969                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82461.888337                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 83204.099270                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103284.537969                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82461.888337                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 83204.099270                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks          309                       # number of writebacks
system.cpu.l2cache.writebacks::total              309                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28990                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        28990                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1093                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1093                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          581                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total          581                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         1093                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        29571                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        30664                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         1093                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        29571                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        30664                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2055891000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2055891000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    101960000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    101960000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     86879500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     86879500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    101960000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   2142770500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   2244730500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    101960000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   2142770500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   2244730500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.354193                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.354193                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.975022                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.975022                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000291                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000291                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.975022                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014235                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.014753                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.975022                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014235                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.014753                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70917.247327                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70917.247327                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93284.537969                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93284.537969                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 149534.423408                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 149534.423408                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93284.537969                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72461.888337                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73204.099270                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93284.537969                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72461.888337                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73204.099270                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      4151922                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2073402                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests           20                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          335                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          335                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp       1996675                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      2067235                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean           93                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict         6765                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        81848                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        81848                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq         1121                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1995554                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2335                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6228110                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           6230445                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77696                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265236992                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          265314688                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                         694                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                 19776                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      2079217                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.000172                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.013121                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2078859     99.98%     99.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                358      0.02%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2079217                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4142980000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          6.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1681500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3116103000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          4.7                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests         31023                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests          359                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp               1674                       # Transaction distribution
system.membus.trans_dist::WritebackDirty          309                       # Transaction distribution
system.membus.trans_dist::CleanEvict               50                       # Transaction distribution
system.membus.trans_dist::ReadExReq             28990                       # Transaction distribution
system.membus.trans_dist::ReadExResp            28990                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq          1674                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61687                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61687                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  61687                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1982272                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1982272                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                 1982272                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples             30664                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                   30664    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total               30664                       # Request fanout histogram
system.membus.reqLayer0.occupancy            43676000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy          161581250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
