// -*- mode:c++ -*-
// Copyright (c) 2010-2014 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines

def operand_types {{
    'sb' : 'int8_t',
    'ub' : 'uint8_t',
    'sh' : 'int16_t',
    'uh' : 'uint16_t',
    'sw' : 'int32_t',
    'uw' : 'uint32_t',
    'ud' : 'uint64_t',
    'tud' : 'Twin64_t',
    'sf' : 'float',
    'df' : 'double'
}};

let {{
    maybePCRead = '''
        ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
    '''
    maybeAlignedPCRead = '''
        ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
         xc->%(func)s(this, %(op_idx)s))
    '''
    maybePCWrite = '''
        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
    '''
    maybeIWPCWrite = '''
        ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
    '''
    maybeAIWPCWrite = '''
        if (%(reg_idx)s == PCReg) {
            bool thumb = THUMB;
            if (thumb) {
                setNextPC(xc, %(final_val)s);
            } else {
                setIWNextPC(xc, %(final_val)s);
            }
        } else {
            xc->%(func)s(this, %(op_idx)s, %(final_val)s);
        }
    '''
    aarch64Read = '''
        ((xc->%(func)s(this, %(op_idx)s)) & mask(intWidth))
    '''
    aarch64Write = '''
        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(intWidth))
    '''
    aarchX64Read = '''
        ((xc->%(func)s(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32))
    '''
    aarchX64Write = '''
        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(aarch64 ? 64 : 32))
    '''
    aarchW64Read = '''
        ((xc->%(func)s(this, %(op_idx)s)) & mask(32))
    '''
    aarchW64Write = '''
        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
    '''
    cntrlNsBankedWrite = '''
        xc->setMiscReg(flattenMiscRegNsBanked(dest, xc->tcBase()), %(final_val)s)
    '''

    cntrlNsBankedRead = '''
        xc->readMiscReg(flattenMiscRegNsBanked(op1, xc->tcBase()))
    '''

    #PCState operands need to have a sorting index (the number at the end)
    #less than all the integer registers which might update the PC. That way
    #if the flag bits of the pc state are updated and a branch happens through
    #R15, the updates are layered properly and the R15 update isn't lost.
    srtNormal = 5
    srtCpsr = 4
    srtBase = 3
    srtPC = 2
    srtMode = 1
    srtEPC = 0

    def floatReg(idx):
        return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)

    def intReg(idx):
        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
                maybePCRead, maybePCWrite)

    def intReg64(idx):
        return ('IntReg', 'ud', idx, 'IsInteger', srtNormal,
                aarch64Read, aarch64Write)

    def intRegX64(idx, id = srtNormal):
        return ('IntReg', 'ud', idx, 'IsInteger', id,
                aarchX64Read, aarchX64Write)

    def intRegW64(idx, id = srtNormal):
        return ('IntReg', 'ud', idx, 'IsInteger', id,
                aarchW64Read, aarchW64Write)

    def intRegNPC(idx):
        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)

    def intRegAPC(idx, id = srtNormal):
        return ('IntReg', 'uw', idx, 'IsInteger', id,
                maybeAlignedPCRead, maybePCWrite)

    def intRegIWPC(idx):
        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
                maybePCRead, maybeIWPCWrite)

    def intRegAIWPC(idx):
        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
                maybePCRead, maybeAIWPCWrite)

    def ccReg(idx):
        return ('CCReg', 'uw', idx, None, srtNormal)

    def cntrlReg(idx, id = srtNormal, type = 'uw'):
        return ('ControlReg', type, idx, None, id)

    def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
        return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)

    def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):
        return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)

    def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
        return ('ControlReg', type, idx, None, id)

    def pcStateReg(idx, id):
        return ('PCState', 'ud', idx, (None, None, 'IsControl'), id)
}};

def operands {{
    #Abstracted integer reg operands
    'Dest': intReg('dest'),
    'Dest64': intReg64('dest'),
    'XDest': intRegX64('dest'),
    'WDest': intRegW64('dest'),
    'IWDest': intRegIWPC('dest'),
    'AIWDest': intRegAIWPC('dest'),
    'Dest2': intReg('dest2'),
    'XDest2': intRegX64('dest2'),
    'FDest2': floatReg('dest2'),
    'Result': intReg('result'),
    'XResult': intRegX64('result'),
    'XBase': intRegX64('base', id = srtBase),
    'Base': intRegAPC('base', id = srtBase),
    'XOffset': intRegX64('offset'),
    'Index': intReg('index'),
    'Shift': intReg('shift'),
    'Op1': intReg('op1'),
    'Op2': intReg('op2'),
    'Op3': intReg('op3'),
    'Op164': intReg64('op1'),
    'Op264': intReg64('op2'),
    'Op364': intReg64('op3'),
    'XOp1': intRegX64('op1'),
    'XOp2': intRegX64('op2'),
    'XOp3': intRegX64('op3'),
    'WOp1': intRegW64('op1'),
    'WOp2': intRegW64('op2'),
    'WOp3': intRegW64('op3'),
    'Reg0': intReg('reg0'),
    'Reg1': intReg('reg1'),
    'Reg2': intReg('reg2'),
    'Reg3': intReg('reg3'),

    #Fixed index integer reg operands
    'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
    'DecodedBankedIntReg': intRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
    'LR': intRegNPC('INTREG_LR'),
    'XLR': intRegX64('INTREG_X30'),
    'R7': intRegNPC('7'),
    # First four arguments are passed in registers
    'R0': intRegNPC('0'),
    'R1': intRegNPC('1'),
    'R2': intRegNPC('2'),
    'R3': intRegNPC('3'),
    'X0': intRegX64('0'),
    'X1': intRegX64('1'),
    'X2': intRegX64('2'),
    'X3': intRegX64('3'),

    # Condition code registers
    'CondCodesNZ': ccReg('CCREG_NZ'),
    'CondCodesC': ccReg('CCREG_C'),
    'CondCodesV': ccReg('CCREG_V'),
    'CondCodesGE': ccReg('CCREG_GE'),
    'OptCondCodesNZ': ccReg(
            '''((condCode == COND_AL || condCode == COND_UC ||
                 condCode == COND_CC || condCode == COND_CS ||
                 condCode == COND_VS || condCode == COND_VC) ?
                CCREG_ZERO : CCREG_NZ)'''),
    'OptCondCodesC': ccReg(
             '''((condCode == COND_HI || condCode == COND_LS ||
                condCode == COND_CS || condCode == COND_CC) ?
               CCREG_C : CCREG_ZERO)'''),
    'OptShiftRmCondCodesC': ccReg(
            '''((condCode == COND_HI || condCode == COND_LS ||
                 condCode == COND_CS || condCode == COND_CC ||
                 shiftType == ROR) ?
                CCREG_C : CCREG_ZERO)'''),
    'OptCondCodesV': ccReg(
            '''((condCode == COND_VS || condCode == COND_VC ||
                 condCode == COND_GE || condCode == COND_LT ||
                 condCode == COND_GT || condCode == COND_LE) ?
                CCREG_V : CCREG_ZERO)'''),
    'FpCondCodes': ccReg('CCREG_FP'),

    #Abstracted floating point reg operands
    'FpDest': floatReg('(dest + 0)'),
    'FpDestP0': floatReg('(dest + 0)'),
    'FpDestP1': floatReg('(dest + 1)'),
    'FpDestP2': floatReg('(dest + 2)'),
    'FpDestP3': floatReg('(dest + 3)'),
    'FpDestP4': floatReg('(dest + 4)'),
    'FpDestP5': floatReg('(dest + 5)'),
    'FpDestP6': floatReg('(dest + 6)'),
    'FpDestP7': floatReg('(dest + 7)'),
    'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
    'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
    'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
    'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
    'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
    'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
    'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
    'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),

    'FpDest2': floatReg('(dest2 + 0)'),
    'FpDest2P0': floatReg('(dest2 + 0)'),
    'FpDest2P1': floatReg('(dest2 + 1)'),
    'FpDest2P2': floatReg('(dest2 + 2)'),
    'FpDest2P3': floatReg('(dest2 + 3)'),

    'FpOp1': floatReg('(op1 + 0)'),
    'FpOp1P0': floatReg('(op1 + 0)'),
    'FpOp1P1': floatReg('(op1 + 1)'),
    'FpOp1P2': floatReg('(op1 + 2)'),
    'FpOp1P3': floatReg('(op1 + 3)'),
    'FpOp1P4': floatReg('(op1 + 4)'),
    'FpOp1P5': floatReg('(op1 + 5)'),
    'FpOp1P6': floatReg('(op1 + 6)'),
    'FpOp1P7': floatReg('(op1 + 7)'),
    'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
    'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
    'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
    'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
    'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
    'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
    'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
    'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),

    'FpOp2': floatReg('(op2 + 0)'),
    'FpOp2P0': floatReg('(op2 + 0)'),
    'FpOp2P1': floatReg('(op2 + 1)'),
    'FpOp2P2': floatReg('(op2 + 2)'),
    'FpOp2P3': floatReg('(op2 + 3)'),

    # Create AArch64 unpacked view of the FP registers
    'AA64FpOp1P0':   floatReg('((op1 * 4) + 0)'),
    'AA64FpOp1P1':   floatReg('((op1 * 4) + 1)'),
    'AA64FpOp1P2':   floatReg('((op1 * 4) + 2)'),
    'AA64FpOp1P3':   floatReg('((op1 * 4) + 3)'),
    'AA64FpOp2P0':   floatReg('((op2 * 4) + 0)'),
    'AA64FpOp2P1':   floatReg('((op2 * 4) + 1)'),
    'AA64FpOp2P2':   floatReg('((op2 * 4) + 2)'),
    'AA64FpOp2P3':   floatReg('((op2 * 4) + 3)'),
    'AA64FpOp3P0':   floatReg('((op3 * 4) + 0)'),
    'AA64FpOp3P1':   floatReg('((op3 * 4) + 1)'),
    'AA64FpOp3P2':   floatReg('((op3 * 4) + 2)'),
    'AA64FpOp3P3':   floatReg('((op3 * 4) + 3)'),
    'AA64FpDestP0':  floatReg('((dest * 4) + 0)'),
    'AA64FpDestP1':  floatReg('((dest * 4) + 1)'),
    'AA64FpDestP2':  floatReg('((dest * 4) + 2)'),
    'AA64FpDestP3':  floatReg('((dest * 4) + 3)'),
    'AA64FpDest2P0': floatReg('((dest2 * 4) + 0)'),
    'AA64FpDest2P1': floatReg('((dest2 * 4) + 1)'),
    'AA64FpDest2P2': floatReg('((dest2 * 4) + 2)'),
    'AA64FpDest2P3': floatReg('((dest2 * 4) + 3)'),

    'AA64FpOp1P0V0':   floatReg('((((op1+0)) * 4) + 0)'),
    'AA64FpOp1P1V0':   floatReg('((((op1+0)) * 4) + 1)'),
    'AA64FpOp1P2V0':   floatReg('((((op1+0)) * 4) + 2)'),
    'AA64FpOp1P3V0':   floatReg('((((op1+0)) * 4) + 3)'),

    'AA64FpOp1P0V1':   floatReg('((((op1+1)) * 4) + 0)'),
    'AA64FpOp1P1V1':   floatReg('((((op1+1)) * 4) + 1)'),
    'AA64FpOp1P2V1':   floatReg('((((op1+1)) * 4) + 2)'),
    'AA64FpOp1P3V1':   floatReg('((((op1+1)) * 4) + 3)'),

    'AA64FpOp1P0V2':   floatReg('((((op1+2)) * 4) + 0)'),
    'AA64FpOp1P1V2':   floatReg('((((op1+2)) * 4) + 1)'),
    'AA64FpOp1P2V2':   floatReg('((((op1+2)) * 4) + 2)'),
    'AA64FpOp1P3V2':   floatReg('((((op1+2)) * 4) + 3)'),

    'AA64FpOp1P0V3':   floatReg('((((op1+3)) * 4) + 0)'),
    'AA64FpOp1P1V3':   floatReg('((((op1+3)) * 4) + 1)'),
    'AA64FpOp1P2V3':   floatReg('((((op1+3)) * 4) + 2)'),
    'AA64FpOp1P3V3':   floatReg('((((op1+3)) * 4) + 3)'),

    'AA64FpOp1P0V0S':   floatReg('((((op1+0)%32) * 4) + 0)'),
    'AA64FpOp1P1V0S':   floatReg('((((op1+0)%32) * 4) + 1)'),
    'AA64FpOp1P2V0S':   floatReg('((((op1+0)%32) * 4) + 2)'),
    'AA64FpOp1P3V0S':   floatReg('((((op1+0)%32) * 4) + 3)'),

    'AA64FpOp1P0V1S':   floatReg('((((op1+1)%32) * 4) + 0)'),
    'AA64FpOp1P1V1S':   floatReg('((((op1+1)%32) * 4) + 1)'),
    'AA64FpOp1P2V1S':   floatReg('((((op1+1)%32) * 4) + 2)'),
    'AA64FpOp1P3V1S':   floatReg('((((op1+1)%32) * 4) + 3)'),

    'AA64FpOp1P0V2S':   floatReg('((((op1+2)%32) * 4) + 0)'),
    'AA64FpOp1P1V2S':   floatReg('((((op1+2)%32) * 4) + 1)'),
    'AA64FpOp1P2V2S':   floatReg('((((op1+2)%32) * 4) + 2)'),
    'AA64FpOp1P3V2S':   floatReg('((((op1+2)%32) * 4) + 3)'),

    'AA64FpOp1P0V3S':   floatReg('((((op1+3)%32) * 4) + 0)'),
    'AA64FpOp1P1V3S':   floatReg('((((op1+3)%32) * 4) + 1)'),
    'AA64FpOp1P2V3S':   floatReg('((((op1+3)%32) * 4) + 2)'),
    'AA64FpOp1P3V3S':   floatReg('((((op1+3)%32) * 4) + 3)'),

    'AA64FpDestP0V0':   floatReg('((((dest+0)) * 4) + 0)'),
    'AA64FpDestP1V0':   floatReg('((((dest+0)) * 4) + 1)'),
    'AA64FpDestP2V0':   floatReg('((((dest+0)) * 4) + 2)'),
    'AA64FpDestP3V0':   floatReg('((((dest+0)) * 4) + 3)'),

    'AA64FpDestP0V1':   floatReg('((((dest+1)) * 4) + 0)'),
    'AA64FpDestP1V1':   floatReg('((((dest+1)) * 4) + 1)'),
    'AA64FpDestP2V1':   floatReg('((((dest+1)) * 4) + 2)'),
    'AA64FpDestP3V1':   floatReg('((((dest+1)) * 4) + 3)'),

    'AA64FpDestP0V0L':   floatReg('((((dest+0)%32) * 4) + 0)'),
    'AA64FpDestP1V0L':   floatReg('((((dest+0)%32) * 4) + 1)'),
    'AA64FpDestP2V0L':   floatReg('((((dest+0)%32) * 4) + 2)'),
    'AA64FpDestP3V0L':   floatReg('((((dest+0)%32) * 4) + 3)'),

    'AA64FpDestP0V1L':   floatReg('((((dest+1)%32) * 4) + 0)'),
    'AA64FpDestP1V1L':   floatReg('((((dest+1)%32) * 4) + 1)'),
    'AA64FpDestP2V1L':   floatReg('((((dest+1)%32) * 4) + 2)'),
    'AA64FpDestP3V1L':   floatReg('((((dest+1)%32) * 4) + 3)'),

    #Abstracted control reg operands
    'MiscDest': cntrlReg('dest'),
    'MiscOp1': cntrlReg('op1'),
    'MiscNsBankedDest': cntrlNsBankedReg('dest'),
    'MiscNsBankedOp1': cntrlNsBankedReg('op1'),
    'MiscNsBankedDest64': cntrlNsBankedReg64('dest'),
    'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),

    #Fixed index control regs
    'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
    'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
    'Spsr': cntrlRegNC('MISCREG_SPSR'),
    'Fpsr': cntrlRegNC('MISCREG_FPSR'),
    'Fpsid': cntrlRegNC('MISCREG_FPSID'),
    'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
    'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
    'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
    'Cpacr': cntrlReg('MISCREG_CPACR'),
    'Cpacr64': cntrlReg('MISCREG_CPACR_EL1'),
    'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
    'Nsacr': cntrlReg('MISCREG_NSACR'),
    'ElrHyp': cntrlRegNC('MISCREG_ELR_HYP'),
    'Hcr': cntrlReg('MISCREG_HCR'),
    'Hcr64': cntrlReg('MISCREG_HCR_EL2'),
    'Hdcr': cntrlReg('MISCREG_HDCR'),
    'Hcptr': cntrlReg('MISCREG_HCPTR'),
    'CptrEl264': cntrlReg('MISCREG_CPTR_EL2'),
    'CptrEl364': cntrlReg('MISCREG_CPTR_EL3'),
    'Hstr': cntrlReg('MISCREG_HSTR'),
    'Scr': cntrlReg('MISCREG_SCR'),
    'Scr64': cntrlReg('MISCREG_SCR_EL3'),
    'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
    'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
    'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
    'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'),

    #Register fields for microops
    'URa' : intReg('ura'),
    'XURa' : intRegX64('ura'),
    'WURa' : intRegW64('ura'),
    'IWRa' : intRegIWPC('ura'),
    'Fa' : floatReg('ura'),
    'FaP1' : floatReg('ura + 1'),
    'URb' : intReg('urb'),
    'XURb' : intRegX64('urb'),
    'URc' : intReg('urc'),
    'XURc' : intRegX64('urc'),

    #Memory Operand
    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),

    #PCState fields
    'RawPC': pcStateReg('pc', srtPC),
    'PC': pcStateReg('instPC', srtPC),
    'NPC': pcStateReg('instNPC', srtPC),
    'pNPC': pcStateReg('instNPC', srtEPC),
    'IWNPC': pcStateReg('instIWNPC', srtPC),
    'Thumb': pcStateReg('thumb', srtPC),
    'NextThumb': pcStateReg('nextThumb', srtMode),
    'NextJazelle': pcStateReg('nextJazelle', srtMode),
    'NextItState': pcStateReg('nextItstate', srtMode),
    'Itstate': pcStateReg('itstate', srtMode),
    'NextAArch64': pcStateReg('nextAArch64', srtMode),

    #Register operands depending on a field in the instruction encoding. These
    #should be avoided since they may not be portable across different
    #encodings of the same instruction.
    'Rd': intReg('RD'),
    'Rm': intReg('RM'),
    'Rs': intReg('RS'),
    'Rn': intReg('RN'),
    'Rt': intReg('RT')
}};
