
---------- Begin Simulation Statistics ----------
sim_seconds                                  2.870996                       # Number of seconds simulated
sim_ticks                                2870995800500                       # Number of ticks simulated
final_tick                               2870995800500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1013503                       # Simulator instruction rate (inst/s)
host_op_rate                                  1225877                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            22160332076                       # Simulator tick rate (ticks/s)
host_mem_usage                                 622032                       # Number of bytes of host memory used
host_seconds                                   129.56                       # Real time elapsed on the host
sim_insts                                   131304972                       # Number of instructions simulated
sim_ops                                     158819278                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1181796                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1294372                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8555136                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           152212                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           573844                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       414464                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12173424                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1181796                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       152212                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1334008                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8754752                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8772316                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26919                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20744                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       133674                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2533                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8987                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         6476                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                199358                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          136793                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               141184                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           156                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              411633                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              450844                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2979850                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               53017                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              199876                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       144362                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              334                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4240140                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         411633                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          53017                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             464650                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3049378                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6104                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3055496                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3049378                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          156                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             411633                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             456948                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2979850                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              53017                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             199890                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       144362                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             334                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7295636                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        199358                       # Number of read requests accepted
system.physmem.writeReqs                       141184                       # Number of write requests accepted
system.physmem.readBursts                      199358                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     141184                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12748800                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10112                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8785280                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12173424                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8772316                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      158                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11937                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11961                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12063                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12015                       # Per bank write bursts
system.physmem.perBankRdBursts::4               20362                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11984                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12067                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12160                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12406                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12763                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11654                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11199                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11763                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11689                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11766                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11411                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8587                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8807                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8988                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8742                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8269                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8555                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8883                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8651                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8881                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9204                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8442                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8330                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8611                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8076                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8388                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7856                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          86                       # Number of times write queue was full causing retry
system.physmem.totGap                    2870994769000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9732                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  189598                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 136793                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    136138                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     17236                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     10604                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8747                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7299                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5883                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5032                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4260                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3698                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       128                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       84                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       51                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       24                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2554                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3487                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4394                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6479                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6593                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7546                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8490                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8347                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9668                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9980                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8490                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     9434                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7894                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      637                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      442                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      414                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      227                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      252                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      243                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      237                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      225                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      244                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        85519                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      251.803880                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     143.212865                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     307.683468                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          42851     50.11%     50.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18042     21.10%     71.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6336      7.41%     78.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3652      4.27%     82.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2667      3.12%     86.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1677      1.96%     87.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          875      1.02%     88.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          945      1.11%     90.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8474      9.91%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          85519                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6795                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        29.315232                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      564.685462                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6793     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6795                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6795                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.201619                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.574221                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.473858                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5740     84.47%     84.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             356      5.24%     89.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              65      0.96%     90.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              46      0.68%     91.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             271      3.99%     95.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              21      0.31%     95.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              19      0.28%     95.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              18      0.26%     96.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              11      0.16%     96.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               7      0.10%     96.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               2      0.03%     96.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               7      0.10%     96.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             153      2.25%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               7      0.10%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               9      0.13%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               5      0.07%     99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               7      0.10%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.03%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.01%     99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.04%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             3      0.04%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             4      0.06%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             3      0.04%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.03%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            10      0.15%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             3      0.04%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.03%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             2      0.03%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.01%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.01%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             3      0.04%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             2      0.03%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.03%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             2      0.03%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6795                       # Writes before turning the bus around for reads
system.physmem.totQLat                     9377591483                       # Total ticks spent queuing
system.physmem.totMemAccLat               13112591483                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    996000000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       47076.26                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  65826.26                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.44                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.06                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.24                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.06                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.87                       # Average write queue length when enqueuing
system.physmem.readRowHits                     166242                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     84708                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.45                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  61.70                       # Row buffer hit rate for writes
system.physmem.avgGap                      8430662.79                       # Average gap between requests
system.physmem.pageHitRate                      74.58                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  309183420                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  164331090                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 746479860                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                362696040                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           6139024320.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             5630456580                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              369226560                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       11487380430                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        9121751040                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       675280298985                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             709613489745                       # Total energy per rank (pJ)
system.physmem_0.averagePower              247.166328                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           2857680941179                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      688127950                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2609960000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   2808734663750                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  23754548081                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     10016707371                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  25191793348                       # Time in different power states
system.physmem_1.actEnergy                  301429380                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  160213515                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 675808140                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                353853360                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           6242283840.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             5675698050                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              365488800                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       11403357870                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        9537644640                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       675067441050                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             709786212765                       # Total energy per rank (pJ)
system.physmem_1.averagePower              247.226489                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           2857340478310                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      678311229                       # Time in different power states
system.physmem_1.memoryStateTime::REF      2653946000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   2807745675250                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN  24837614861                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     10072973461                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  25007279699                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                     7823                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                7823                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1468                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         6355                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples         7823                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           7823    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         7823                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6429                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12550.163322                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11491.858959                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6296.322703                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         5867     91.26%     91.26% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          463      7.20%     98.46% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151           86      1.34%     99.80% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535            8      0.12%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            1      0.02%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687            3      0.05%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::212992-229375            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6429                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1181300000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     1181300000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1181300000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5000     77.77%     77.77% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1429     22.23%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6429                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7823                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7823                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6429                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6429                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        14252                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    25081905                       # DTB read hits
system.cpu0.dtb.read_misses                      6707                       # DTB read misses
system.cpu0.dtb.write_hits                   18693539                       # DTB write hits
system.cpu0.dtb.write_misses                     1116                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3387                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1738                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                25088612                       # DTB read accesses
system.cpu0.dtb.write_accesses               18694655                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         43775444                       # DTB hits
system.cpu0.dtb.misses                           7823                       # DTB misses
system.cpu0.dtb.accesses                     43783267                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                     3349                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3349                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          299                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3050                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3349                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3349    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3349                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2333                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12879.339906                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 12002.998619                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5903.446394                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          363     15.56%     15.56% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1682     72.10%     87.66% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          212      9.09%     96.74% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           37      1.59%     98.33% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           36      1.54%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343            1      0.04%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-106495            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::122880-131071            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2333                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1180899500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1180899500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1180899500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2034     87.18%     87.18% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          299     12.82%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2333                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3349                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3349                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2333                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2333                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         5682                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   118659015                       # ITB inst hits
system.cpu0.itb.inst_misses                      3349                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2087                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               118662364                       # ITB inst accesses
system.cpu0.itb.hits                        118659015                       # DTB hits
system.cpu0.itb.misses                           3349                       # DTB misses
system.cpu0.itb.accesses                    118662364                       # DTB accesses
system.cpu0.numPwrStateTransitions               3724                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         1862                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    1466902343.272825                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   23730658455.603134                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         1082     58.11%     58.11% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10          775     41.62%     99.73% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.79% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.21%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499963373360                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           1862                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   139623637326                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731372163174                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                      5741991601                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1862                       # number of quiesce instructions executed
system.cpu0.committedInsts                  114996919                       # Number of instructions committed
system.cpu0.committedOps                    138962993                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            122999157                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  9755                       # Number of float alu accesses
system.cpu0.num_func_calls                   12659267                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     15643522                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   122999157                       # number of integer instructions
system.cpu0.num_fp_insts                         9755                       # number of float instructions
system.cpu0.num_int_register_reads          226444380                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          85465434                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                7495                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           503448381                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           52091583                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     44908198                       # number of memory refs
system.cpu0.num_load_insts                   25331105                       # Number of load instructions
system.cpu0.num_store_insts                  19577093                       # Number of store instructions
system.cpu0.num_idle_cycles              5462744326.346097                       # Number of idle cycles
system.cpu0.num_busy_cycles              279247274.653903                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.048632                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.951368                       # Percentage of idle cycles
system.cpu0.Branches                         29039529                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 97695313     68.45%     68.45% # Class of executed instruction
system.cpu0.op_class::IntMult                  108459      0.08%     68.53% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatMultAcc                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatMisc                     0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              7991      0.01%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::MemRead                25328849     17.75%     86.28% # Class of executed instruction
system.cpu0.op_class::MemWrite               19569598     13.71%     99.99% # Class of executed instruction
system.cpu0.op_class::FloatMemRead               2256      0.00%     99.99% # Class of executed instruction
system.cpu0.op_class::FloatMemWrite              7495      0.01%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 142722234                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements           690121                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          498.373175                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42907120                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           690633                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            62.127237                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1207348000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   498.373175                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.973385                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.973385                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          323                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           88                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         88185256                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        88185256                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     23824030                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23824030                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     17964029                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      17964029                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       318863                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       318863                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       364525                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       364525                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361510                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       361510                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     41788059                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41788059                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     42106922                       # number of overall hits
system.cpu0.dcache.overall_hits::total       42106922                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       394827                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       394827                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       324085                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       324085                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       127008                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       127008                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21435                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21435                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19554                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        19554                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       718912                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        718912                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       845920                       # number of overall misses
system.cpu0.dcache.overall_misses::total       845920                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5517390500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5517390500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   6298218500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   6298218500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    337010500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    337010500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    458737500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    458737500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1113000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1113000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  11815609000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  11815609000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  11815609000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  11815609000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     24218857                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     24218857                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     18288114                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     18288114                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       445871                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       445871                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       385960                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       385960                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381064                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381064                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     42506971                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     42506971                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     42952842                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     42952842                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016302                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.016302                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017721                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017721                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.284854                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.284854                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055537                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055537                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051314                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051314                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016913                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.016913                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019694                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.019694                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13974.197560                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13974.197560                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19433.847602                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19433.847602                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15722.439935                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15722.439935                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23460.033753                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23460.033753                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16435.403777                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16435.403777                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13967.761727                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13967.761727                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       690121                       # number of writebacks
system.cpu0.dcache.writebacks::total           690121                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25200                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        25200                       # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15056                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15056                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        25200                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        25200                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        25200                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        25200                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       369627                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       369627                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       324085                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       324085                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       100010                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       100010                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6379                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6379                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19554                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        19554                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       693712                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       693712                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       793722                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       793722                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31768                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31768                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28446                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28446                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60214                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60214                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4739955500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4739955500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5974133500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5974133500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1650418500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1650418500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    101003000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    101003000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    439215500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    439215500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1081000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1081000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10714089000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  10714089000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  12364507500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  12364507500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6631169500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6631169500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6631169500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6631169500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015262                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015262                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017721                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017721                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224303                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224303                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016528                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016528                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051314                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051314                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016320                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016320                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018479                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018479                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12823.618134                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12823.618134                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18433.847602                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18433.847602                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16502.534747                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16502.534747                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15833.672989                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15833.672989                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22461.670246                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22461.670246                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15444.577865                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15444.577865                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15577.881802                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15577.881802                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208737.392974                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208737.392974                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110126.706414                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110126.706414                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          1095423                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.436912                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          117563071                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1095935                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           107.271938                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      14178985000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.436912                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998900                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998900                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          214                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        238413974                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       238413974                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    117563071                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      117563071                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    117563071                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       117563071                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    117563071                       # number of overall hits
system.cpu0.icache.overall_hits::total      117563071                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1095944                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1095944                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1095944                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1095944                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1095944                       # number of overall misses
system.cpu0.icache.overall_misses::total      1095944                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11846969000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  11846969000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  11846969000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  11846969000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  11846969000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  11846969000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    118659015                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    118659015                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    118659015                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    118659015                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    118659015                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    118659015                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009236                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.009236                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009236                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.009236                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009236                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.009236                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10809.830612                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10809.830612                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10809.830612                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10809.830612                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10809.830612                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10809.830612                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1095423                       # number of writebacks
system.cpu0.icache.writebacks::total          1095423                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1095944                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1095944                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1095944                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1095944                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1095944                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1095944                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11298997000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11298997000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11298997000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11298997000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11298997000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11298997000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    863305500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    863305500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    863305500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    863305500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009236                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009236                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009236                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009236                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009236                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009236                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10309.830612                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10309.830612                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10309.830612                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10309.830612                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10309.830612                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10309.830612                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1843455                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1843489                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           30                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       237167                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements          260392                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15616.554479                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           1673878                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          276011                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.064534                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14458.510897                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.380966                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.135465                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1156.527151                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.882477                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000084                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000008                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.070589                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.953159                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          316                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15300                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           27                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          129                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          150                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          176                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          827                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         6046                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6216                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2035                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.019287                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000183                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.933838                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        60952812                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       60952812                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         9949                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4513                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         14462                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       474087                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       474087                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      1283679                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      1283679                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       226501                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       226501                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1033387                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1033387                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       374984                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       374984                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         9949                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4513                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1033387                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       601485                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1649334                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         9949                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4513                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1033387                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       601485                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1649334                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          333                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          154                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          487                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        54609                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        54609                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19552                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        19552                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        42975                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        42975                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        62557                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        62557                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101032                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       101032                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          333                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          154                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        62557                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       144007                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       207051                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          333                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          154                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        62557                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       144007                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       207051                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      8868000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3618500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     12486500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data     29801000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total     29801000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data      8716000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total      8716000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1032499                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1032499                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2749345500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2749345500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3431495000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3431495000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3333037000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3333037000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      8868000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3618500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3431495000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   6082382500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   9526364000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      8868000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3618500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3431495000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   6082382500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   9526364000                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        10282                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4667                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        14949                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       474087                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       474087                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      1283679                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      1283679                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        54609                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        54609                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19552                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        19552                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269476                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       269476                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1095944                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1095944                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       476016                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       476016                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        10282                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4667                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1095944                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       745492                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1856385                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        10282                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4667                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1095944                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       745492                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1856385                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.032387                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.032998                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.032577                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.159476                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.159476                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.057080                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.057080                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.212245                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.212245                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.032387                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.032998                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.057080                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.193170                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.111535                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.032387                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.032998                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.057080                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.193170                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.111535                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26630.630631                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23496.753247                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25639.630390                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   545.715908                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   545.715908                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   445.785597                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   445.785597                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 516249.500000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 516249.500000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63975.462478                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63975.462478                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 54853.893249                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 54853.893249                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32989.914087                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32989.914087                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26630.630631                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23496.753247                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 54853.893249                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42236.714188                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 46009.746391                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26630.630631                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23496.753247                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 54853.893249                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42236.714188                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 46009.746391                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           10486                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks       227470                       # number of writebacks
system.cpu0.l2cache.writebacks::total          227470                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1575                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         1575                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           30                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           30                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1605                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         1605                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1605                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         1605                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          333                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          154                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          487                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       261736                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       261736                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        54609                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        54609                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19552                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19552                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41400                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        41400                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        62557                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        62557                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       101002                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       101002                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          333                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          154                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        62557                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       142402                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       205446                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          333                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          154                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        62557                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       142402                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       261736                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       467182                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31768                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40790                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28446                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28446                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60214                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69236                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      6870000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2694500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      9564500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  16748653122                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  16748653122                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    936375500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    936375500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    292739000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    292739000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       840499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       840499                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2221757000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2221757000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3056153000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3056153000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2721461500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2721461500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      6870000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2694500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3056153000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4943218500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   8008936000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      6870000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2694500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3056153000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4943218500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  16748653122                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  24757589122                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    795640500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6376615000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7172255500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    795640500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6376615000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7172255500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.032387                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.032998                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.032577                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.153631                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.153631                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.057080                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.057080                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.212182                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.212182                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.032387                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.032998                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.057080                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.191017                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.110670                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.032387                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.032998                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.057080                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.191017                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.251662                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19639.630390                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63990.636068                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63990.636068                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17146.908019                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17146.908019                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14972.330196                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14972.330196                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 420249.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 420249.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53665.628019                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53665.628019                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 48853.893249                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48853.893249                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26944.629809                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26944.629809                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 48853.893249                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34713.125518                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38983.168326                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 48853.893249                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34713.125518                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63990.636068                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52993.456773                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200724.471166                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175833.672469                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105899.209486                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103591.419204                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests      3713043                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1871637                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        27791                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       210694                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       209047                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         1647                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq         61395                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1681090                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28446                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28446                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       701864                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      1311457                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict        80209                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       307976                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        86960                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        41708                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       111633                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           49                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           79                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       288540                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       285048                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1095944                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       562349                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3227                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp           12                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3305355                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2550756                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11066                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        24460                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          5891637                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    140283576                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     96129280                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        18668                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        41128                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         236472652                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     885693                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic             18656572                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples      2784580                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.090516                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.288973                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           2534179     91.01%     91.01% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            248754      8.93%     99.94% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              1647      0.06%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       2784580                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    3695245998                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    113887546                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1652938000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1201348488                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      6399000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     14180994                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                     3368                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                3368                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          669                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         2699                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         3368                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           3368    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         3368                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2598                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12496.920708                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11544.208502                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  5669.313441                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191          611     23.52%     23.52% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1671     64.32%     87.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575          230      8.85%     96.69% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767           69      2.66%     99.35% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959           10      0.38%     99.73% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151            3      0.12%     99.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343            2      0.08%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-106495            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2598                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1937787828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1937787828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1937787828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1937     74.56%     74.56% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          661     25.44%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2598                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3368                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3368                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2598                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2598                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         5966                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3952331                       # DTB read hits
system.cpu1.dtb.read_misses                      2852                       # DTB read misses
system.cpu1.dtb.write_hits                    3427850                       # DTB write hits
system.cpu1.dtb.write_misses                      516                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1975                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   341                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3955183                       # DTB read accesses
system.cpu1.dtb.write_accesses                3428366                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          7380181                       # DTB hits
system.cpu1.dtb.misses                           3368                       # DTB misses
system.cpu1.dtb.accesses                      7383549                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                     1746                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1746                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          168                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1578                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         1746                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1746    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1746                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1107                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12746.160795                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11849.716682                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5651.710937                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          170     15.36%     15.36% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          628     56.73%     72.09% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          162     14.63%     86.72% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479           49      4.43%     91.15% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575           38      3.43%     94.58% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           32      2.89%     97.47% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767           17      1.54%     99.01% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863            4      0.36%     99.37% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            1      0.09%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            4      0.36%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::45056-49151            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1107                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1938367828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1938367828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1938367828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          939     84.82%     84.82% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          168     15.18%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1107                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1746                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1746                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1107                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1107                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2853                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    16663369                       # ITB inst hits
system.cpu1.itb.inst_misses                      1746                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1084                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                16665115                       # ITB inst accesses
system.cpu1.itb.hits                         16663369                       # DTB hits
system.cpu1.itb.misses                           1746                       # DTB misses
system.cpu1.itb.accesses                     16665115                       # DTB accesses
system.cpu1.numPwrStateTransitions               5435                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         2718                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    1046549937.704562                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   25917662670.452511                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         1945     71.56%     71.56% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10          767     28.22%     99.78% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            2      0.07%     99.85% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.04%     99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11            1      0.04%     99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.04%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 929980418584                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           2718                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON    26473069819                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844522730681                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                      5741059879                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2718                       # number of quiesce instructions executed
system.cpu1.committedInsts                   16308053                       # Number of instructions committed
system.cpu1.committedOps                     19856285                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             17888019                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
system.cpu1.num_func_calls                    1028859                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1844250                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    17888019                       # number of integer instructions
system.cpu1.num_fp_insts                         1792                       # number of float instructions
system.cpu1.num_int_register_reads           32444258                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          12537466                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            72543530                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            6508973                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      7613771                       # number of memory refs
system.cpu1.num_load_insts                    4063495                       # Number of load instructions
system.cpu1.num_store_insts                   3550276                       # Number of store instructions
system.cpu1.num_idle_cycles              5688122330.646462                       # Number of idle cycles
system.cpu1.num_busy_cycles              52937548.353538                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.009221                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.990779                       # Percentage of idle cycles
system.cpu1.Branches                          2952894                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 12563541     62.17%     62.17% # Class of executed instruction
system.cpu1.op_class::IntMult                   26310      0.13%     62.30% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatMultAcc                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatMisc                     0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              3279      0.02%     62.32% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.32% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.32% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.32% # Class of executed instruction
system.cpu1.op_class::MemRead                 4062979     20.11%     82.43% # Class of executed instruction
system.cpu1.op_class::MemWrite                3549000     17.56%     99.99% # Class of executed instruction
system.cpu1.op_class::FloatMemRead                516      0.00%     99.99% # Class of executed instruction
system.cpu1.op_class::FloatMemWrite              1276      0.01%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  20206967                       # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements           187241                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          470.165247                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            7113602                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           187604                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            37.918179                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     128171950500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   470.165247                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.918291                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.918291                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          363                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          290                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           73                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.708984                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         14979376                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        14979376                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data      3640649                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3640649                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      3239316                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3239316                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        49005                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        49005                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78940                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        78940                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70837                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        70837                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      6879965                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         6879965                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      6928970                       # number of overall hits
system.cpu1.dcache.overall_hits::total        6928970                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       133578                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       133578                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        91863                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        91863                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30193                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30193                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16916                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        16916                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23207                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23207                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       225441                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        225441                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       255634                       # number of overall misses
system.cpu1.dcache.overall_misses::total       255634                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2045952000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2045952000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2531885000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2531885000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    322352500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    322352500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    544400500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    544400500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2036500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2036500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4577837000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4577837000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4577837000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4577837000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3774227                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3774227                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      3331179                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      3331179                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79198                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        79198                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        95856                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        95856                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94044                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        94044                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      7105406                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      7105406                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      7184604                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      7184604                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035392                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035392                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027577                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.027577                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.381234                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.381234                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.176473                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.176473                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.246767                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.246767                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031728                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.031728                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035581                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.035581                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15316.534160                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15316.534160                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27561.531846                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 27561.531846                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19056.071175                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19056.071175                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23458.460809                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23458.460809                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20306.142184                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20306.142184                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17907.778308                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17907.778308                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks       187241                       # number of writebacks
system.cpu1.dcache.writebacks::total           187241                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          248                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          248                       # number of ReadReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11947                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11947                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          248                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          248                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          248                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          248                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       133330                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       133330                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91863                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        91863                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29503                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        29503                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4969                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4969                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23207                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23207                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       225193                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       225193                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       254696                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       254696                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3077                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3077                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2432                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2432                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5509                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5509                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1901282500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1901282500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2440022000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2440022000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    505317500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    505317500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     91175500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     91175500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    521240500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    521240500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1989500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1989500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4341304500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4341304500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4846622000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4846622000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    442663500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    442663500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    442663500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    442663500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035326                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035326                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027577                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027577                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.372522                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.372522                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051838                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051838                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.246767                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.246767                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031693                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.031693                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035450                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035450                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14259.975249                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14259.975249                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26561.531846                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26561.531846                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17127.664983                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17127.664983                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18348.862950                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18348.862950                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22460.486060                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22460.486060                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19278.150298                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19278.150298                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19029.046393                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19029.046393                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143862.040949                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143862.040949                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80352.786350                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80352.786350                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements           503470                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.455555                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           16159382                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           503982                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            32.063411                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      85409649000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.455555                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973546                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973546                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          390                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          118                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            4                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         33830710                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        33830710                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst     16159382                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       16159382                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     16159382                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        16159382                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     16159382                       # number of overall hits
system.cpu1.icache.overall_hits::total       16159382                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       503982                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       503982                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       503982                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        503982                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       503982                       # number of overall misses
system.cpu1.icache.overall_misses::total       503982                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4760681000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4760681000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4760681000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4760681000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4760681000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4760681000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     16663364                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     16663364                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     16663364                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     16663364                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     16663364                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     16663364                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030245                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.030245                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030245                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.030245                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030245                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.030245                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9446.132997                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9446.132997                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9446.132997                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9446.132997                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9446.132997                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9446.132997                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks       503470                       # number of writebacks
system.cpu1.icache.writebacks::total           503470                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       503982                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       503982                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       503982                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       503982                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       503982                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       503982                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4508690000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   4508690000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4508690000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   4508690000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4508690000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   4508690000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     17068500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     17068500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     17068500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     17068500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.030245                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.030245                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.030245                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.030245                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.030245                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.030245                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8946.132997                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8946.132997                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8946.132997                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8946.132997                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8946.132997                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8946.132997                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96432.203390                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96432.203390                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued       202393                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       202393                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        60767                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements           44084                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       14674.344516                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs            603056                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           58488                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           10.310765                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14288.601821                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     2.272921                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.058859                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   381.410915                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.872107                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000139                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000126                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.023279                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.895651                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          311                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14077                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           14                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          292                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          892                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2699                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        10486                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.018982                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.000977                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.859192                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        24261935                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       24261935                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3748                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1963                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total          5711                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks       114339                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total       114339                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       565289                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       565289                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27869                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        27869                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       482614                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       482614                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        98302                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        98302                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3748                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1963                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       482614                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       126171                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         614496                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3748                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1963                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       482614                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       126171                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        614496                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          433                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          316                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          749                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29344                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29344                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23201                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23201                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            6                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34650                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        34650                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        21368                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        21368                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        69500                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        69500                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          433                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          316                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        21368                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       104150                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       126267                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          433                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          316                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        21368                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       104150                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       126267                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      8916500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      6346000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     15262500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     14232000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     14232000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     17729000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     17729000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1919000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1919000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1493005000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1493005000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    842821500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    842821500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1603059500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1603059500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      8916500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      6346000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    842821500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3096064500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3954148500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      8916500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      6346000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    842821500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3096064500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3954148500                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         4181                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2279                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total         6460                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks       114339                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total       114339                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       565289                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       565289                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29344                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29344                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23201                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23201                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62519                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        62519                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       503982                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       503982                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       167802                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       167802                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         4181                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2279                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       503982                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       230321                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       740763                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         4181                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2279                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       503982                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       230321                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       740763                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.103564                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.138657                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.115944                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.554232                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.554232                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.042398                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.042398                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.414179                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.414179                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.103564                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.138657                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.042398                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.452195                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.170455                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.103564                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.138657                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.042398                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.452195                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.170455                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20592.378753                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20082.278481                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20377.169559                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   485.005453                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   485.005453                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   764.148097                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   764.148097                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 319833.333333                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 319833.333333                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43088.167388                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43088.167388                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39443.162673                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39443.162673                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23065.604317                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23065.604317                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20592.378753                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20082.278481                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39443.162673                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29726.975516                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 31315.771342                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20592.378753                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20082.278481                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39443.162673                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29726.975516                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 31315.771342                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches             850                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks        33278                       # number of writebacks
system.cpu1.l2cache.writebacks::total           33278                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           91                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total           91                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data           91                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total           91                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data           91                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total           91                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          433                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          316                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          749                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        26693                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        26693                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29344                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29344                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23201                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23201                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34559                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        34559                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        21368                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        21368                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        69500                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        69500                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          433                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          316                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        21368                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       104059                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       126176                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          433                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          316                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        21368                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       104059                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        26693                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       152869                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3077                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3254                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2432                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2432                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5509                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5686                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6318500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4450000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     10768500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    957745966                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    957745966                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    449306000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    449306000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    347204000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    347204000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1637000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1637000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1274798000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1274798000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    714613500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    714613500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1186059500                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1186059500                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6318500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4450000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    714613500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2460857500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3186239500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6318500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4450000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    714613500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2460857500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    957745966                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4143985466                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15741000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    417705000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    433446000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     15741000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    417705000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    433446000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.103564                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.138657                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.115944                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.552776                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.552776                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.042398                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042398                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.414179                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.414179                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.103564                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.138657                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.042398                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.451800                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.170332                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.103564                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.138657                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.042398                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.451800                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.206367                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14377.169559                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35880.042183                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35880.042183                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15311.682116                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15311.682116                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14965.044610                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14965.044610                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 272833.333333                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 272833.333333                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36887.583553                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36887.583553                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33443.162673                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33443.162673                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17065.604317                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17065.604317                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33443.162673                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23648.675271                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25252.341967                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33443.162673                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23648.675271                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35880.042183                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27108.082515                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135750.731232                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133204.056546                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75822.290797                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76230.390433                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests      1483973                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests       749706                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        11083                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       112750                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       104482                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         8268                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq         12645                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       721727                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2432                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2432                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       148874                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       576372                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict        28336                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        31823                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        70615                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40952                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        85036                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           38                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           79                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        69693                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        67178                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       503982                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       263487                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq          292                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1511788                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       838524                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5603                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        10248                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2366163                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     64477636                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29432570                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         9116                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        16724                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          93936046                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     334351                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic              4909260                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples      1058830                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.130816                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.359612                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0            928586     87.70%     87.70% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            121976     11.52%     99.22% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              8268      0.78%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1058830                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1438248000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     79282585                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    756150000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    376097000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      3324000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy      6067998                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                31015                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31015                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59423                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59423                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56604                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107918                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180876                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71548                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162798                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484070                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             48604000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               106000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               319500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                31000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                15000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                92500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               623000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               46500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6201500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            32041500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187869528                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84719000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36445                       # number of replacements
system.iocache.tags.tagsinuse               14.382505                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36461                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         290037968000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.382505                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.898907                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.898907                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
system.iocache.tags.data_accesses              328311                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36479                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36479                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36479                       # number of overall misses
system.iocache.overall_misses::total            36479                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     41042377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     41042377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4379492151                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4379492151                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4420534528                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4420534528                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4420534528                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4420534528                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36479                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36479                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36479                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36479                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 160950.498039                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 160950.498039                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120900.291271                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120900.291271                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 121180.255161                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 121180.255161                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 121180.255161                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 121180.255161                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           298                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    9                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    33.111111                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36479                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36479                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36479                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36479                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     28292377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     28292377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2566405842                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2566405842                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2594698219                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2594698219                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2594698219                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2594698219                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110950.498039                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 110950.498039                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70848.217811                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70848.217811                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 71128.545711                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 71128.545711                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 71128.545711                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 71128.545711                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   137345                       # number of replacements
system.l2c.tags.tagsinuse                65074.392349                       # Cycle average of tags in use
system.l2c.tags.total_refs                     526935                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   202695                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.599645                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             103119965000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks    6537.248776                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     4.009779                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.050987                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7065.227850                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6920.254188                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.581661                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.954844                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1513.426266                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3159.258777                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2388.379223                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.099751                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000061                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.107807                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.105595                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.571985                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.023093                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.048206                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.036444                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.992956                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        34308                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        31034                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          136                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4715                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        29456                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         1168                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        29797                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.523499                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000122                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.473541                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6118121                       # Number of tag accesses
system.l2c.tags.data_accesses                 6118121                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks       260748                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          260748                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           39886                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4893                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               44779                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2390                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          2219                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              4609                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             3995                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1504                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5499                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          159                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           75                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        44649                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        52745                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        45897                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           46                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           28                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        18994                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        11024                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5470                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           179087                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           159                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            75                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               44649                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               56740                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        45897                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            46                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            28                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               18994                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               12528                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         5470                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  184586                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          159                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           75                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              44649                       # number of overall hits
system.l2c.overall_hits::cpu0.data              56740                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        45897                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           46                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           28                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              18994                       # number of overall hits
system.l2c.overall_hits::cpu1.data              12528                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         5470                       # number of overall hits
system.l2c.overall_hits::total                 184586                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data           631                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           289                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total               920                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data           83                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           96                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             179                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11301                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8030                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19331                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker            7                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        17908                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         9085                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       133844                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         2374                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          942                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6476                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         170639                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             17908                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             20386                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       133844                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2374                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8972                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         6476                       # number of demand (read+write) misses
system.l2c.demand_misses::total                189970                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            7                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            17908                       # number of overall misses
system.l2c.overall_misses::cpu0.data            20386                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       133844                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2374                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8972                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         6476                       # number of overall misses
system.l2c.overall_misses::total               189970                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data     10365500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       935500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     11301000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       563000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       162500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       725500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1654925500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    828235000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2483160500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      1167000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       185500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1949681500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1106313500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  15937420718                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker        90000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    261013000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    123092000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    836855283                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  20215818501                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      1167000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       185500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1949681500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   2761239000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  15937420718                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        90000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    261013000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    951327000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    836855283                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     22698979001                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      1167000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       185500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1949681500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   2761239000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  15937420718                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        90000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    261013000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    951327000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    836855283                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    22698979001                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       260748                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       260748                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        40517                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5182                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45699                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         2473                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2315                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          4788                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15296                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9534                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            24830                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          166                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           77                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        62557                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        61830                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       179741                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           47                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           28                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        21368                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        11966                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11946                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       349726                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          166                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           77                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           62557                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           77126                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       179741                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           47                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           28                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           21368                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           21500                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11946                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              374556                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          166                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           77                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          62557                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          77126                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       179741                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           47                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           28                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          21368                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          21500                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11946                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             374556                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.015574                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.055770                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.020132                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.033562                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.041469                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.037385                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.738821                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.842249                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.778534                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.042169                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.025974                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.286267                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.146935                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.744649                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.021277                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.111101                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.078723                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.542106                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.487922                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.042169                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.025974                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.286267                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.264321                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.744649                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.021277                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.111101                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.417302                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.542106                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.507187                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.042169                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.025974                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.286267                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.264321                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.744649                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.021277                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.111101                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.417302                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.542106                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.507187                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16427.099842                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3237.024221                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 12283.695652                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6783.132530                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1692.708333                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4053.072626                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 146440.624723                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103142.590286                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 128454.839377                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 166714.285714                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        92750                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 108872.096270                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 121773.637865                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker        90000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 109946.503791                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 130670.912951                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 118471.266832                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 166714.285714                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        92750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 108872.096270                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 135447.807319                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        90000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 109946.503791                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 106032.880071                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 119487.176928                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 166714.285714                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        92750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 108872.096270                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 135447.807319                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        90000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 109946.503791                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 106032.880071                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 119487.176928                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks              100603                       # number of writebacks
system.l2c.writebacks::total                   100603                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            4                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            6                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           10                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 10                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                10                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3738                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3738                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data          631                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          289                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          920                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           83                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           96                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          179                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11301                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8030                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19331                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            7                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17904                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9085                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       133844                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2368                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          942                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6476                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       170629                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        17904                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        20386                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       133844                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2368                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8972                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6476                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           189960                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        17904                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        20386                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       133844                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2368                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8972                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6476                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          189960                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31768                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3074                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        44041                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28446                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2432                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30878                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60214                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5506                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        74919                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     14735500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      6305500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     21041000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      2194500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2340500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      4535000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1541915500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    747935000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2289850500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      1097000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       165500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1770529000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1015463500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14598976726                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker        80000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    236880000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    113671002                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    772093287                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  18508956015                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1097000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       165500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1770529000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2557379000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  14598976726                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        80000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    236880000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    861606002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    772093287                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  20798806515                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1097000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       165500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1770529000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2557379000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14598976726                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        80000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    236880000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    861606002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    772093287                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  20798806515                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    633244000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5804773000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     12555000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    362314500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6812886500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    633244000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5804773000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     12555000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    362314500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6812886500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.015574                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.055770                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.020132                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.033562                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.041469                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.037385                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.738821                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.842249                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.778534                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.042169                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.025974                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.286203                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.146935                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.744649                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.021277                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.110820                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.078723                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.542106                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.487893                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.042169                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.025974                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.286203                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.264321                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.744649                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.021277                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.110820                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.417302                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.542106                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.507160                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.042169                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.025974                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.286203                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.264321                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.744649                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.021277                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.110820                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.417302                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.542106                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.507160                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23352.614897                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21818.339100                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22870.652174                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26439.759036                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24380.208333                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25335.195531                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136440.624723                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93142.590286                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 118454.839377                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        82750                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 98890.136282                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111773.637865                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker        80000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100033.783784                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120669.853503                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108474.854890                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        82750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 98890.136282                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125447.807319                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        80000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100033.783784                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96032.768836                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 109490.453332                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        82750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 98890.136282                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125447.807319                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        80000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100033.783784                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96032.768836                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 109490.453332                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182723.904558                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117864.183474                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154694.182693                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96402.381506                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65803.577915                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 90936.698301                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        502698                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       282285                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          634                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               44041                       # Transaction distribution
system.membus.trans_dist::ReadResp             214925                       # Transaction distribution
system.membus.trans_dist::WriteReq              30878                       # Transaction distribution
system.membus.trans_dist::WriteResp             30878                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       136793                       # Transaction distribution
system.membus.trans_dist::CleanEvict            16421                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            64440                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          38073                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39751                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19302                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        170884                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp         4530                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107918                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13584                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       647548                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       769084                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72939                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72939                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 842023                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162798                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27168                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18628620                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18818654                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21135774                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           126969                       # Total snoops (count)
system.membus.snoopTraffic                      37632                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            424292                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.012213                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.109837                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  419110     98.78%     98.78% # Request fanout histogram
system.membus.snoop_fanout::1                    5182      1.22%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              424292                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88179000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11330000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           970733801                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1113560532                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            7243389                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      1013922                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       527446                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       187526                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          29573                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        28355                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops         1218                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              44044                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            511645                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30878                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30878                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       361351                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          119836                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          109190                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         42682                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         151872                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           79                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           79                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            50757                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           50757                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       467605                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4574                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp         3427                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1275330                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       317115                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1592445                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     35259052                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5662514                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               40921566                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          390876                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  15646988                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples           887171                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.397282                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.492133                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 535932     60.41%     60.41% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 350021     39.45%     99.86% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                   1218      0.14%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             887171                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          894860010                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2155585                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         676392933                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         238880542                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
