[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000

[system]
type=System
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]

[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain

[system.cpu0]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
tracer=system.cpu0.tracer
workload=system.cpu0.workload
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side

[system.cpu0.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu0.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.slave[1]

[system.cpu0.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768

[system.cpu0.dtb]
type=SparcTLB
eventq_index=0
size=64

[system.cpu0.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu0.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.slave[0]

[system.cpu0.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768

[system.cpu0.interrupts]
type=SparcInterrupts
eventq_index=0

[system.cpu0.isa]
type=SparcISA
eventq_index=0

[system.cpu0.itb]
type=SparcTLB
eventq_index=0
size=64

[system.cpu0.tracer]
type=ExeTracer
eventq_index=0

[system.cpu0.workload]
type=LiveProcess
cmd=test_atomic 4
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false

[system.cpu1]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
tracer=system.cpu1.tracer
workload=system.cpu0.workload
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side

[system.cpu1.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu1.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.slave[3]

[system.cpu1.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768

[system.cpu1.dtb]
type=SparcTLB
eventq_index=0
size=64

[system.cpu1.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu1.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.slave[2]

[system.cpu1.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768

[system.cpu1.interrupts]
type=SparcInterrupts
eventq_index=0

[system.cpu1.isa]
type=SparcISA
eventq_index=0

[system.cpu1.itb]
type=SparcTLB
eventq_index=0
size=64

[system.cpu1.tracer]
type=ExeTracer
eventq_index=0

[system.cpu2]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=2
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu2.interrupts
isa=system.cpu2.isa
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
tracer=system.cpu2.tracer
workload=system.cpu0.workload
dcache_port=system.cpu2.dcache.cpu_side
icache_port=system.cpu2.icache.cpu_side

[system.cpu2.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu2.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu2.dcache_port
mem_side=system.toL2Bus.slave[5]

[system.cpu2.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768

[system.cpu2.dtb]
type=SparcTLB
eventq_index=0
size=64

[system.cpu2.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu2.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu2.icache_port
mem_side=system.toL2Bus.slave[4]

[system.cpu2.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768

[system.cpu2.interrupts]
type=SparcInterrupts
eventq_index=0

[system.cpu2.isa]
type=SparcISA
eventq_index=0

[system.cpu2.itb]
type=SparcTLB
eventq_index=0
size=64

[system.cpu2.tracer]
type=ExeTracer
eventq_index=0

[system.cpu3]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=3
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu3.interrupts
isa=system.cpu3.isa
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
tracer=system.cpu3.tracer
workload=system.cpu0.workload
dcache_port=system.cpu3.dcache.cpu_side
icache_port=system.cpu3.icache.cpu_side

[system.cpu3.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu3.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu3.dcache_port
mem_side=system.toL2Bus.slave[7]

[system.cpu3.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768

[system.cpu3.dtb]
type=SparcTLB
eventq_index=0
size=64

[system.cpu3.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu3.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu3.icache_port
mem_side=system.toL2Bus.slave[6]

[system.cpu3.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768

[system.cpu3.interrupts]
type=SparcInterrupts
eventq_index=0

[system.cpu3.isa]
type=SparcISA
eventq_index=0

[system.cpu3.itb]
type=SparcTLB
eventq_index=0
size=64

[system.cpu3.tracer]
type=ExeTracer
eventq_index=0

[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain

[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000

[system.l2c]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=4194304
system=system
tags=system.l2c.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[1]

[system.l2c.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304

[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.l2c.mem_side

[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system

[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
port=system.membus.master[0]

[system.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side

[system.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system

[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

