
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000021                       # Number of seconds simulated
sim_ticks                                    21268000                       # Number of ticks simulated
final_tick                                   21268000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  49400                       # Simulator instruction rate (inst/s)
host_op_rate                                    49392                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              181337178                       # Simulator tick rate (ticks/s)
host_mem_usage                                 231948                       # Number of bytes of host memory used
host_seconds                                     0.12                       # Real time elapsed on the host
sim_insts                                        5792                       # Number of instructions simulated
sim_ops                                          5792                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             21952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              6400                       # Number of bytes read from this memory
system.physmem.bytes_read::total                28352                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        21952                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           21952                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                343                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                100                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   443                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst           1032160993                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            300921572                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1333082565                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst      1032160993                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total         1032160993                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst          1032160993                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           300921572                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1333082565                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           445                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         445                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    28480                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     28480                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  71                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  42                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  55                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  58                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  53                       # Per bank write bursts
system.physmem.perBankRdBursts::5                  62                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  52                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  10                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   9                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::10                  1                       # Per bank write bursts
system.physmem.perBankRdBursts::11                  0                       # Per bank write bursts
system.physmem.perBankRdBursts::12                  0                       # Per bank write bursts
system.physmem.perBankRdBursts::13                  0                       # Per bank write bursts
system.physmem.perBankRdBursts::14                  4                       # Per bank write bursts
system.physmem.perBankRdBursts::15                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        21217500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     445                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       235                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       147                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        44                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples           75                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      351.573333                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     215.062906                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     340.509998                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             23     30.67%     30.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           18     24.00%     54.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           11     14.67%     69.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            2      2.67%     72.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            3      4.00%     76.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            4      5.33%     81.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            2      2.67%     84.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            3      4.00%     88.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            9     12.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             75                       # Bytes accessed per row activation
system.physmem.totQLat                        5980000                       # Total ticks spent queuing
system.physmem.totMemAccLat                  14323750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      2225000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13438.20                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  32188.20                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                        1339.10                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                     1339.10                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                          10.46                       # Data bus utilization in percentage
system.physmem.busUtilRead                      10.46                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.85                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        360                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.90                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        47679.78                       # Average gap between requests
system.physmem.pageHitRate                      80.90                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                     528360                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                     254265                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                   2877420                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           1229280.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy                3922170                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy                  28320                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy           5666370                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy             64320                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy                 14570505                       # Total energy per rank (pJ)
system.physmem_0.averagePower              685.066353                       # Core power per rank (mW)
system.physmem_0.totalIdleTime               12593250                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE          17500                       # Time in different power states
system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF              0                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN       167250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT         8137250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN     12426000                       # Time in different power states
system.physmem_1.actEnergy                      78540                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                      30360                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                    299880                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           1229280.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy                 747840                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy                1408800                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy           6431880                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy            712320                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy                  0                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy                 10938900                       # Total energy per rank (pJ)
system.physmem_1.averagePower              514.317955                       # Core power per rank (mW)
system.physmem_1.totalIdleTime               13775500                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE        3585000                       # Time in different power states
system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF              0                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN      1854750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT         1201500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN     14106750                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                    2411                       # Number of BP lookups
system.cpu.branchPred.condPredicted              1982                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               409                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 2056                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     693                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             33.706226                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     227                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 35                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups             130                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits                 19                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses              111                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted           37                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                    9                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON        21268000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                            42537                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles               7674                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          13369                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        2411                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches                939                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                          4149                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                     849                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                    5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           146                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           22                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                      1861                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   290                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              12420                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.076409                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.475819                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                    10086     81.21%     81.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                      166      1.34%     82.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      214      1.72%     84.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                      147      1.18%     85.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                      241      1.94%     87.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                      150      1.21%     88.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                      280      2.25%     90.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      148      1.19%     92.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                      988      7.95%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                12420                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.056680                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.314291                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                     7247                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                  2821                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      1946                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                   130                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                    276                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved                  324                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   149                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts                  11479                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   451                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                    276                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                     7415                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                     800                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles            463                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      1897                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                  1569                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                  11042                       # Number of instructions processed by rename
system.cpu.rename.IQFullEvents                     12                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                      2                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                   1522                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands                9711                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 17897                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups            17871                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups                26                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                  4998                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                     4713                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 27                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             27                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                       381                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 1937                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1590                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                55                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores               30                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                      10171                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  63                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                      8808                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued                53                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined            4442                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined         3474                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             47                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         12420                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.709179                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.511732                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0                9305     74.92%     74.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                 969      7.80%     82.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                 656      5.28%     88.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                 462      3.72%     91.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                 429      3.45%     95.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 293      2.36%     97.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 212      1.71%     99.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                  64      0.52%     99.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                  30      0.24%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           12420                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                      12      6.06%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc                    0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                     88     44.44%     50.51% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                    87     43.94%     94.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead                 0      0.00%     94.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite               11      5.56%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                  5530     62.78%     62.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     62.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.81% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 1811     20.56%     83.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1439     16.34%     99.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead               2      0.02%     99.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite             24      0.27%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                   8808                       # Type of FU issued
system.cpu.iq.rate                           0.207067                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                         198                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.022480                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              30220                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             14647                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses         8115                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                  67                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                 36                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           27                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                   8967                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      39                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads               79                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads          976                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores          544                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked             7                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                    276                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                     722                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                    71                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts               10234                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                32                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  1937                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 1590                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 53                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                     12                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                    60                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect             68                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          256                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                  324                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                  8463                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                  1703                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               345                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                         3080                       # number of memory reference insts executed
system.cpu.iew.exec_branches                     1358                       # Number of branches executed
system.cpu.iew.exec_stores                       1377                       # Number of stores executed
system.cpu.iew.exec_rate                     0.198956                       # Inst execution rate
system.cpu.iew.wb_sent                           8242                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                          8142                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                      4448                       # num instructions producing a value
system.cpu.iew.wb_consumers                      7158                       # num instructions consuming a value
system.cpu.iew.wb_rate                       0.191410                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.621403                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts            4444                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts               270                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        11718                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.494282                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.358473                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0         9553     81.52%     81.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1          850      7.25%     88.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2          527      4.50%     93.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          215      1.83%     95.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          176      1.50%     96.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5          112      0.96%     97.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6          126      1.08%     98.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7           49      0.42%     99.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8          110      0.94%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        11718                       # Number of insts commited each cycle
system.cpu.commit.committedInsts                 5792                       # Number of instructions committed
system.cpu.commit.committedOps                   5792                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                           2007                       # Number of memory references committed
system.cpu.commit.loads                           961                       # Number of loads committed
system.cpu.commit.membars                           7                       # Number of memory barriers committed
system.cpu.commit.branches                       1037                       # Number of branches committed
system.cpu.commit.fp_insts                         22                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                      5698                       # Number of committed integer instructions.
system.cpu.commit.function_calls                  103                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu             3783     65.31%     65.31% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult               0      0.00%     65.31% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     65.31% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              2      0.03%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc             0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.35% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead             960     16.57%     81.92% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite           1027     17.73%     99.65% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead            1      0.02%     99.67% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite           19      0.33%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total              5792                       # Class of committed instruction
system.cpu.commit.bw_lim_events                   110                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                        21844                       # The number of ROB reads
system.cpu.rob.rob_writes                       21175                       # The number of ROB writes
system.cpu.timesIdled                             228                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           30117                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                        5792                       # Number of Instructions Simulated
system.cpu.committedOps                          5792                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               7.344095                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         7.344095                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.136164                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.136164                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                    13368                       # number of integer regfile reads
system.cpu.int_regfile_writes                    7153                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        25                       # number of floating regfile reads
system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse            64.389343                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                2206                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               102                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             21.627451                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    64.389343                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.015720                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.015720                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          102                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.024902                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              5390                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             5390                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data         1485                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1485                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          721                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            721                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          2206                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             2206                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         2206                       # number of overall hits
system.cpu.dcache.overall_hits::total            2206                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          113                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           113                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          325                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          325                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          438                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            438                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          438                       # number of overall misses
system.cpu.dcache.overall_misses::total           438                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      8211000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      8211000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     32489496                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     32489496                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     40700496                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     40700496                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     40700496                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     40700496                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1598                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1598                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data         1046                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total         1046                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2644                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2644                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2644                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2644                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070713                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.070713                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.310707                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.310707                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.165658                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.165658                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.165658                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.165658                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72663.716814                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 72663.716814                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99967.680000                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 99967.680000                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 92923.506849                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 92923.506849                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 92923.506849                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 92923.506849                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          612                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          102                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           56                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          278                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          278                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          334                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          334                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          334                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          334                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           57                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           57                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           47                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           47                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          104                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          104                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          104                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          104                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4669500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      4669500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4693998                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      4693998                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9363498                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      9363498                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9363498                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      9363498                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035670                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035670                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044933                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.044933                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.039334                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.039334                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.039334                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.039334                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81921.052632                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81921.052632                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99872.297872                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99872.297872                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90033.634615                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 90033.634615                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90033.634615                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 90033.634615                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                 0                       # number of replacements
system.cpu.icache.tags.tagsinuse           168.912200                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                1425                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               349                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              4.083095                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   168.912200                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.082477                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.082477                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          349                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          179                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.170410                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              4071                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             4071                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst         1425                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            1425                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          1425                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             1425                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         1425                       # number of overall hits
system.cpu.icache.overall_hits::total            1425                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          436                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           436                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          436                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            436                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          436                       # number of overall misses
system.cpu.icache.overall_misses::total           436                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     33901500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     33901500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     33901500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     33901500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     33901500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     33901500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         1861                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         1861                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         1861                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         1861                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         1861                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         1861                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.234283                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.234283                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.234283                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.234283                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.234283                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.234283                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77755.733945                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 77755.733945                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77755.733945                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 77755.733945                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77755.733945                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 77755.733945                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          567                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs   113.400000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           86                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           86                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           86                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           86                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           86                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           86                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          350                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          350                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          350                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          350                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          350                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          350                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     28298000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     28298000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     28298000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     28298000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     28298000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     28298000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.188071                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.188071                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.188071                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.188071                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.188071                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.188071                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80851.428571                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80851.428571                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80851.428571                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 80851.428571                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80851.428571                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 80851.428571                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          231.224808                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  8                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              443                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.018059                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   167.706281                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    63.518527                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005118                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.001938                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.007056                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          443                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.013519                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             4075                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            4075                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            6                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total            6                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data            2                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total            2                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst            6                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data            2                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               8                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            6                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data            2                       # number of overall hits
system.cpu.l2cache.overall_hits::total              8                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data           47                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           47                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          344                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          344                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data           55                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total           55                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          344                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          102                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           446                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          344                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          102                       # number of overall misses
system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4620000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      4620000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     27705000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     27705000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      4563000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total      4563000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     27705000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      9183000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     36888000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     27705000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      9183000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     36888000                       # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data           47                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           47                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          350                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          350                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           57                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total           57                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          350                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          104                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          454                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          350                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          104                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          454                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.982857                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.982857                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.964912                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.964912                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.982857                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.980769                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.982379                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.982857                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.980769                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.982379                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98297.872340                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98297.872340                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80537.790698                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80537.790698                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82963.636364                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82963.636364                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80537.790698                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90029.411765                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82708.520179                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80537.790698                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90029.411765                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82708.520179                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           47                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           47                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          344                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          344                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           55                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total           55                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          344                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          102                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          446                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          344                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          102                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4150000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4150000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     24275000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     24275000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4033000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4033000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24275000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8183000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     32458000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24275000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8183000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     32458000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.982857                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.964912                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.964912                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.980769                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.982379                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.982857                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980769                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.982379                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88297.872340                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88297.872340                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70566.860465                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70566.860465                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73327.272727                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73327.272727                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70566.860465                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80225.490196                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72775.784753                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70566.860465                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80225.490196                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72775.784753                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests          454                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests            8                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp           404                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           47                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           47                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          350                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq           57                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          699                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          206                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               905                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22336                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         6528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              28864                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples          454                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.017621                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.131715                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                446     98.24%     98.24% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  8      1.76%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            454                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         227000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        523500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          2.5                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        153000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests           445                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED     21268000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                396                       # Transaction distribution
system.membus.trans_dist::ReadExReq                47                       # Transaction distribution
system.membus.trans_dist::ReadExResp               47                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           398                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          888                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    888                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28352                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   28352                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               445                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     445    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 445                       # Request fanout histogram
system.membus.reqLayer0.occupancy              553000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.6                       # Layer utilization (%)
system.membus.respLayer1.occupancy            2325250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             10.9                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
