
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000028                       # Number of seconds simulated
sim_ticks                                    27725000                       # Number of ticks simulated
final_tick                                   27725000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  72342                       # Simulator instruction rate (inst/s)
host_op_rate                                    72337                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              132265036                       # Simulator tick rate (ticks/s)
host_mem_usage                                 269700                       # Number of bytes of host memory used
host_seconds                                     0.21                       # Real time elapsed on the host
sim_insts                                       15162                       # Number of instructions simulated
sim_ops                                         15162                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             19008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                27840                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        19008                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           19008                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                297                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   435                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            685590622                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            318557259                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1004147881                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       685590622                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          685590622                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           685590622                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           318557259                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1004147881                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           436                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         436                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    27904                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     27904                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  97                       # Per bank write bursts
system.physmem.perBankRdBursts::1                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::2                  38                       # Per bank write bursts
system.physmem.perBankRdBursts::3                  20                       # Per bank write bursts
system.physmem.perBankRdBursts::4                  16                       # Per bank write bursts
system.physmem.perBankRdBursts::5                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  29                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  32                       # Per bank write bursts
system.physmem.perBankRdBursts::8                   4                       # Per bank write bursts
system.physmem.perBankRdBursts::9                   1                       # Per bank write bursts
system.physmem.perBankRdBursts::10                  1                       # Per bank write bursts
system.physmem.perBankRdBursts::11                  0                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 48                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 31                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 58                       # Per bank write bursts
system.physmem.perBankRdBursts::15                 33                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        27691500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     436                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       274                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       117                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples           36                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      487.111111                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     330.231493                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     390.430808                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127              3      8.33%      8.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255            9     25.00%     33.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383            8     22.22%     55.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            2      5.56%     61.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            2      5.56%     66.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            1      2.78%     69.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           11     30.56%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             36                       # Bytes accessed per row activation
system.physmem.totQLat                        2136500                       # Total ticks spent queuing
system.physmem.totMemAccLat                  10682750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      2180000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                     6366250                       # Total ticks spent accessing banks
system.physmem.avgQLat                        4900.23                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    14601.49                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  24501.72                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                        1006.46                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                     1006.46                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           7.86                       # Data bus utilization in percentage
system.physmem.busUtilRead                       7.86                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.48                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        362                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.03                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        63512.61                       # Average gap between requests
system.physmem.pageHitRate                      83.03                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               4.51                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                   1004147881                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                 351                       # Transaction distribution
system.membus.trans_dist::ReadResp                350                       # Transaction distribution
system.membus.trans_dist::ReadExReq                85                       # Transaction distribution
system.membus.trans_dist::ReadExResp               85                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          871                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    871                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        27840                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total               27840                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                  27840                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy              519500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
system.membus.respLayer1.occupancy            4047500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             14.6                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                    5146                       # Number of BP lookups
system.cpu.branchPred.condPredicted              3529                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect              2366                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                 4100                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                    2719                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             66.317073                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                     174                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  5                       # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls                   18                       # Number of system calls
system.cpu.numCycles                            55451                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken         2893                       # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken         2253                       # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads        14397                       # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites        11099                       # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses        25496                       # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads            0                       # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites            0                       # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses            0                       # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards           5052                       # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens                       3844                       # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect         1541                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect          762                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted           2303                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted              1055                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct     68.582490                       # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions            11045                       # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
system.cpu.contextSwitches                          1                       # Number of context switches
system.cpu.threadCycles                         21862                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled                             439                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           37883                       # Number of cycles cpu's stages were not processed
system.cpu.runCycles                            17568                       # Number of cycles cpu stages are processed.
system.cpu.activity                         31.682026                       # Percentage of cycles cpu is active
system.cpu.comLoads                              2225                       # Number of Load instructions committed
system.cpu.comStores                             1448                       # Number of Store instructions committed
system.cpu.comBranches                           3358                       # Number of Branches instructions committed
system.cpu.comNops                                726                       # Number of Nop instructions committed
system.cpu.comNonSpec                             222                       # Number of Non-Speculative instructions committed
system.cpu.comInts                               7166                       # Number of Integer instructions committed
system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
system.cpu.committedInsts                       15162                       # Number of Instructions committed (Per-Thread)
system.cpu.committedOps                         15162                       # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total                 15162                       # Number of Instructions committed (Total)
system.cpu.cpi                               3.657235                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
system.cpu.cpi_total                         3.657235                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.273431                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
system.cpu.ipc_total                         0.273431                       # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles                    42025                       # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles                     13426                       # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization               24.212368                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles                    46098                       # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles                      9353                       # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization               16.867144                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles                    46648                       # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles                      8803                       # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization               15.875277                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles                    52573                       # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles                      2878                       # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization                5.190168                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles                    46142                       # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles                      9309                       # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization               16.787795                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements                 0                       # number of replacements
system.cpu.icache.tags.tagsinuse           168.846335                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                3004                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               299                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             10.046823                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   168.846335                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.082444                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.082444                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          299                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          220                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.145996                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              7069                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             7069                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst         3004                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            3004                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          3004                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             3004                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         3004                       # number of overall hits
system.cpu.icache.overall_hits::total            3004                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          381                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           381                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          381                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            381                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          381                       # number of overall misses
system.cpu.icache.overall_misses::total           381                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     25942000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     25942000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     25942000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     25942000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     25942000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     25942000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         3385                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         3385                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         3385                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         3385                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         3385                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         3385                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.112555                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.112555                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.112555                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.112555                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.112555                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.112555                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68089.238845                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 68089.238845                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68089.238845                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 68089.238845                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68089.238845                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 68089.238845                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           80                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           80                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           80                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           80                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           80                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          301                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          301                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          301                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          301                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20512000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     20512000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20512000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     20512000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20512000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     20512000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.088922                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.088922                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.088922                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68146.179402                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68146.179402                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68146.179402                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 68146.179402                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68146.179402                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 68146.179402                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput              1008764653                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq            354                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           352                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           85                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           85                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          600                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          276                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               876                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        19136                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8832                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total          27968                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus             27968                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy         219500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        499500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.8                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        221500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          199.869816                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              350                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.005714                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   168.179067                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    31.690749                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005132                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.000967                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.006100                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          260                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010681                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             3947                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            3947                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          299                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          352                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           85                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           85                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          299                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           437                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          299                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
system.cpu.l2cache.overall_misses::total          437                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20188500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3701000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     23889500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6006500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      6006500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     20188500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      9707500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     29896000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     20188500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      9707500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     29896000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          301                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          354                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           85                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           85                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          301                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          439                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          301                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          439                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993355                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.994350                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993355                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.995444                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993355                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.995444                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67520.066890                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69830.188679                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67867.897727                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70664.705882                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70664.705882                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67520.066890                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70344.202899                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68411.899314                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67520.066890                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70344.202899                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68411.899314                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          299                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          352                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           85                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           85                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          299                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          437                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          299                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          437                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16473000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3042500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     19515500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4962500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4962500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16473000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8005000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     24478000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16473000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8005000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     24478000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994350                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.995444                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.995444                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55093.645485                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57405.660377                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55441.761364                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58382.352941                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58382.352941                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55093.645485                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58007.246377                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56013.729977                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55093.645485                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58007.246377                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56013.729977                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse            98.543212                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                3193                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             23.137681                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    98.543212                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.024058                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.024058                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.033691                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              7484                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             7484                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data         2167                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            2167                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data         1020                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total           1020                       # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data          3187                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             3187                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         3187                       # number of overall hits
system.cpu.dcache.overall_hits::total            3187                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           58                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            58                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          422                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          422                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          480                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            480                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          480                       # number of overall misses
system.cpu.dcache.overall_misses::total           480                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      4273500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      4273500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     25910250                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     25910250                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     30183750                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     30183750                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     30183750                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     30183750                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         2225                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         2225                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         3667                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         3667                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         3667                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         3667                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026067                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.026067                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.292649                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.292649                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.130897                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.130897                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.130897                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.130897                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73681.034483                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 73681.034483                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61398.696682                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61398.696682                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62882.812500                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 62882.812500                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62882.812500                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 62882.812500                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         1097                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                33                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    33.242424                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data            5                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          337                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          337                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          342                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          342                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          342                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          342                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           53                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           85                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           85                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3755500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      3755500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6094500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      6094500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9850000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      9850000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9850000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      9850000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023820                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023820                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.058946                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.037633                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.037633                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70858.490566                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70858.490566                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        71700                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        71700                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71376.811594                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71376.811594                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71376.811594                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71376.811594                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
