
---------- Begin Simulation Statistics ----------
sim_seconds                                  1.860192                       # Number of seconds simulated
sim_ticks                                1860191785500                       # Number of ticks simulated
final_tick                               1860191785500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 128947                       # Simulator instruction rate (inst/s)
host_op_rate                                   128947                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4527634915                       # Simulator tick rate (ticks/s)
host_mem_usage                                 347764                       # Number of bytes of host memory used
host_seconds                                   410.85                       # Real time elapsed on the host
sim_insts                                    52978349                       # Number of instructions simulated
sim_ops                                      52978349                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            963264                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24877248                       # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
system.physmem.bytes_read::total             28492800                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       963264                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          963264                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7515392                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7515392                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              15051                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             388707                       # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                445200                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117428                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               117428                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               517830                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13373486                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide           1425814                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                15317130                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          517830                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             517830                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           4040117                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4040117                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           4040117                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              517830                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13373486                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide          1425814                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               19357247                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        445200                       # Number of read requests accepted
system.physmem.writeReqs                       117428                       # Number of write requests accepted
system.physmem.readBursts                      445200                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     117428                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 28485504                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7296                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7513728                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  28492800                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7515392                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      114                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            178                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               28210                       # Per bank write bursts
system.physmem.perBankRdBursts::1               27995                       # Per bank write bursts
system.physmem.perBankRdBursts::2               28357                       # Per bank write bursts
system.physmem.perBankRdBursts::3               27829                       # Per bank write bursts
system.physmem.perBankRdBursts::4               27761                       # Per bank write bursts
system.physmem.perBankRdBursts::5               27267                       # Per bank write bursts
system.physmem.perBankRdBursts::6               27371                       # Per bank write bursts
system.physmem.perBankRdBursts::7               27375                       # Per bank write bursts
system.physmem.perBankRdBursts::8               27696                       # Per bank write bursts
system.physmem.perBankRdBursts::9               27269                       # Per bank write bursts
system.physmem.perBankRdBursts::10              28017                       # Per bank write bursts
system.physmem.perBankRdBursts::11              27509                       # Per bank write bursts
system.physmem.perBankRdBursts::12              27546                       # Per bank write bursts
system.physmem.perBankRdBursts::13              28232                       # Per bank write bursts
system.physmem.perBankRdBursts::14              28342                       # Per bank write bursts
system.physmem.perBankRdBursts::15              28310                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7920                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7516                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7873                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7373                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7309                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6720                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6881                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6774                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7136                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6679                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7411                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6967                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7107                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7877                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8064                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7795                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
system.physmem.totGap                    1860186344000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  445200                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 117428                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    322906                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     56729                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     22897                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      5869                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      1157                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      4278                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      3757                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3842                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3993                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2551                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     2136                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2038                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1891                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1835                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1567                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1541                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1538                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1552                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                     1725                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                     1258                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       16                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                       10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      765                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                      934                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3347                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4688                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4756                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4816                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4872                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5401                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5474                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6284                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     3432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2435                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1613                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1063                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1099                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1072                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1289                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1446                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1531                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1699                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1801                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1872                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1823                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1946                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1928                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1837                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1841                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     1726                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     1489                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     1270                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      915                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      461                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      300                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       22                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        48603                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      651.388927                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     428.580055                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     419.495686                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           8350     17.18%     17.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         6347     13.06%     30.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         2940      6.05%     36.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1813      3.73%     40.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1501      3.09%     43.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          899      1.85%     44.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          723      1.49%     46.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          886      1.82%     48.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        25144     51.73%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          48603                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6893                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        64.568403                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     2543.170744                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191           6890     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6893                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6893                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.032062                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.789521                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        3.768510                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               5850     84.87%     84.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 28      0.41%     85.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                 70      1.02%     86.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                418      6.06%     92.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                134      1.94%     94.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 49      0.71%     95.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 24      0.35%     95.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 22      0.32%     95.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 53      0.77%     96.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 38      0.55%     97.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 20      0.29%     97.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                 34      0.49%     97.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                 19      0.28%     98.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                 34      0.49%     98.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  7      0.10%     98.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                 10      0.15%     98.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  2      0.03%     98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34                  2      0.03%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  3      0.04%     98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36                  6      0.09%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  5      0.07%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38                  5      0.07%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39                  8      0.12%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40                  4      0.06%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41                  2      0.03%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43                  1      0.01%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44                  2      0.03%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45                  5      0.07%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46                  2      0.03%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47                  6      0.09%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48                  6      0.09%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::49                  4      0.06%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50                  2      0.03%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::51                  1      0.01%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52                  2      0.03%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::53                  2      0.03%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54                  3      0.04%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::55                  1      0.01%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56                  6      0.09%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::57                  1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58                  2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6893                       # Writes before turning the bus around for reads
system.physmem.totQLat                    10196532000                       # Total ticks spent queuing
system.physmem.totMemAccLat               17805650750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2225430000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  5383688750                       # Total ticks spent accessing banks
system.physmem.avgQLat                       22909.13                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    12095.84                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  40004.97                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          15.31                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.04                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       15.32                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.04                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.54                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.57                       # Average write queue length when enqueuing
system.physmem.readRowHits                     402462                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     96189                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.42                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  81.91                       # Row buffer hit rate for writes
system.physmem.avgGap                      3306245.59                       # Average gap between requests
system.physmem.pageHitRate                      88.65                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               0.41                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     19400105                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              295926                       # Transaction distribution
system.membus.trans_dist::ReadResp             295846                       # Transaction distribution
system.membus.trans_dist::WriteReq               9597                       # Transaction distribution
system.membus.trans_dist::WriteResp              9597                       # Transaction distribution
system.membus.trans_dist::Writeback            117428                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              181                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             181                       # Transaction distribution
system.membus.trans_dist::ReadExReq            156840                       # Transaction distribution
system.membus.trans_dist::ReadExResp           156840                       # Transaction distribution
system.membus.trans_dist::BadAddressError           80                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33054                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884064                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          160                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917278                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124679                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       124679                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1041957                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44140                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30699136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30743276                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5309056                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            36052332                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               36052332                       # Total data (bytes)
system.membus.snoop_data_through_bus            35584                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy            29929000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy          1552530249                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              100500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3767548549                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy          376726994                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                41685                       # number of replacements
system.iocache.tags.tagsinuse                1.261130                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         1710337661000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide     1.261130                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide     0.078821                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.078821                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
system.iocache.tags.data_accesses              375525                       # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
system.iocache.overall_misses::total            41725                       # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide     21133883                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     21133883                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide  13194182648                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  13194182648                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide  13215316531                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  13215316531                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide  13215316531                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  13215316531                       # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122161.173410                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 317534.237774                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 317534.237774                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 316724.182888                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 316724.182888                       # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 316724.182888                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 316724.182888                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        393531                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                28535                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    13.791169                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           41512                       # number of writebacks
system.iocache.writebacks::total                41512                       # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136883                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     12136883                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  11031075660                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total  11031075660                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide  11043212543                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total  11043212543                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide  11043212543                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total  11043212543                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 265476.406912                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 265476.406912                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 264666.567837                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 264666.567837                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 264666.567837                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 264666.567837                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                13847711                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11622265                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            397151                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9355929                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 5809145                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             62.090520                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                  903416                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              38861                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                      9926060                       # DTB read hits
system.cpu.dtb.read_misses                      41229                       # DTB read misses
system.cpu.dtb.read_acv                           545                       # DTB read access violations
system.cpu.dtb.read_accesses                   943227                       # DTB read accesses
system.cpu.dtb.write_hits                     6592681                       # DTB write hits
system.cpu.dtb.write_misses                     10567                       # DTB write misses
system.cpu.dtb.write_acv                          408                       # DTB write access violations
system.cpu.dtb.write_accesses                  338977                       # DTB write accesses
system.cpu.dtb.data_hits                     16518741                       # DTB hits
system.cpu.dtb.data_misses                      51796                       # DTB misses
system.cpu.dtb.data_acv                           953                       # DTB access violations
system.cpu.dtb.data_accesses                  1282204                       # DTB accesses
system.cpu.itb.fetch_hits                     1307907                       # ITB hits
system.cpu.itb.fetch_misses                     36763                       # ITB misses
system.cpu.itb.fetch_acv                         1058                       # ITB acv
system.cpu.itb.fetch_accesses                 1344670                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.numCycles                        122133073                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           28029052                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       70711644                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    13847711                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            6712561                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      13244944                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1986135                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               38034896                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                32174                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        253831                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       364385                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          294                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8541461                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                263003                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           81242947                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.870373                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.213979                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 67998003     83.70%     83.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                   851901      1.05%     84.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1695578      2.09%     86.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   822984      1.01%     87.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2755109      3.39%     91.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                   560259      0.69%     91.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   643349      0.79%     92.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1008302      1.24%     93.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  4907462      6.04%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             81242947                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.113382                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.578972                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29204589                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              37726390                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  12112827                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                958015                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1241125                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved               582779                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 42656                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts               69393384                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                129440                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1241125                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 30348079                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                14012797                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       20034433                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  11321379                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               4285132                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               65602946                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  7156                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 505213                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               1511728                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands            43797820                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups              79654521                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups         79475437                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            166633                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              38179156                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  5618656                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1682920                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         240154                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12205182                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             10434201                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             6904424                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1321264                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           860087                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   58162225                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2049609                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  56784496                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            110090                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         6876207                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined      3554384                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        1388666                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      81242947                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.698947                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.361354                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            56591956     69.66%     69.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            10816248     13.31%     82.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             5164366      6.36%     89.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             3390360      4.17%     93.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2636798      3.25%     96.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             1463129      1.80%     98.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6              751413      0.92%     99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              332295      0.41%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8               96382      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        81242947                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   91428     11.57%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 372699     47.16%     58.73% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                326088     41.27%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              38710597     68.17%     68.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                61705      0.11%     68.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.29% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd               25607      0.05%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             10355398     18.24%     86.58% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             6671255     11.75%     98.33% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess             949012      1.67%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               56784496                       # Type of FU issued
system.cpu.iq.rate                           0.464940                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                      790215                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.013916                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          195020122                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes          66766340                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     55549754                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads              692121                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             335594                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       327937                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses               57205980                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  361445                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads           599867                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1342082                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         3325                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14250                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores       526611                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        17915                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        172386                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1241125                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                10205447                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                698563                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            63733516                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            684669                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              10434201                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              6904424                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1805473                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 512478                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 17546                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14250                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         200257                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       411476                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               611733                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              56321962                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts               9995488                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            462533                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       3521682                       # number of nop insts executed
system.cpu.iew.exec_refs                     16613940                       # number of memory reference insts executed
system.cpu.iew.exec_branches                  8922207                       # Number of branches executed
system.cpu.iew.exec_stores                    6618452                       # Number of stores executed
system.cpu.iew.exec_rate                     0.461152                       # Inst execution rate
system.cpu.iew.wb_sent                       55993079                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      55877691                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  27722224                       # num instructions producing a value
system.cpu.iew.wb_consumers                  37565081                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.457515                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.737979                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         7447390                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls          660943                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            565908                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     80001822                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.702098                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.631989                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     59240837     74.05%     74.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      8588333     10.74%     84.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4609463      5.76%     90.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2533581      3.17%     93.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1517845      1.90%     95.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       611107      0.76%     96.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       522353      0.65%     97.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       526375      0.66%     97.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      1851928      2.31%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     80001822                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             56169084                       # Number of instructions committed
system.cpu.commit.committedOps               56169084                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       15469932                       # Number of memory references committed
system.cpu.commit.loads                       9092119                       # Number of loads committed
system.cpu.commit.membars                      226344                       # Number of memory barriers committed
system.cpu.commit.branches                    8439731                       # Number of branches committed
system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  52018783                       # Number of committed integer instructions.
system.cpu.commit.function_calls               740550                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               1851928                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    141516799                       # The number of ROB reads
system.cpu.rob.rob_writes                   128475885                       # The number of ROB writes
system.cpu.timesIdled                         1198400                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        40890126                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   3598244060                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                    52978349                       # Number of Instructions Simulated
system.cpu.committedOps                      52978349                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              52978349                       # Number of Instructions Simulated
system.cpu.cpi                               2.305339                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         2.305339                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.433776                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.433776                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                 73853807                       # number of integer regfile reads
system.cpu.int_regfile_writes                40298046                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    166062                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   167446                       # number of floating regfile writes
system.cpu.misc_regfile_reads                 2027357                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 938942                       # number of misc regfile writes
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.iobus.throughput                       1454553                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
system.iobus.trans_dist::WriteReq               51149                       # Transaction distribution
system.iobus.trans_dist::WriteResp              51149                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5050                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total        33054                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  116504                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20200                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total        44140                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              2705748                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 2705748                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              4661000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer29.occupancy           380111537                       # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            23457000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            43192006                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.cpu.toL2Bus.throughput               111856774                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2116112                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2116015                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq          9597                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp         9597                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       840541                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           62                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           63                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       342408                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       300857                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           80                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2017437                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3676056                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           5693493                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64554304                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143513388                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      208067692                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         208057644                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        17408                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     2478840496                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1516414125                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2186111163                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.icache.tags.replacements           1008048                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.665585                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7476650                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1008556                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              7.413222                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       26682759250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.665585                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.995441                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.995441                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          315                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses           9550236                       # Number of tag accesses
system.cpu.icache.tags.data_accesses          9550236                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      7476651                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7476651                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7476651                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7476651                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7476651                       # number of overall hits
system.cpu.icache.overall_hits::total         7476651                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1064809                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1064809                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1064809                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1064809                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1064809                       # number of overall misses
system.cpu.icache.overall_misses::total       1064809                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14791038698                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14791038698                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14791038698                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14791038698                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14791038698                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14791038698                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8541460                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8541460                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8541460                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8541460                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8541460                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8541460                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124664                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.124664                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.124664                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.124664                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.124664                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.124664                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13890.790459                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13890.790459                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13890.790459                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13890.790459                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13890.790459                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13890.790459                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         5929                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          286                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               183                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    32.398907                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          286                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        56033                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        56033                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        56033                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        56033                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        56033                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        56033                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1008776                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1008776                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1008776                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1008776                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1008776                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1008776                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12131918870                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12131918870                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12131918870                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12131918870                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12131918870                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12131918870                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.118103                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.118103                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.118103                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.118103                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.118103                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.118103                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.375399                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.375399                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.375399                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12026.375399                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.375399                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12026.375399                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           338266                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65338.058683                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            2543929                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           403433                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             6.305704                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       5551710750                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 53796.698722                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  5304.345669                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  6237.014293                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.820872                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.080938                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.095169                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996980                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65167                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          492                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3493                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3306                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2414                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55462                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994370                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         26707389                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        26707389                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst       993608                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       826462                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1820070                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       840541                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       840541                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           20                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           20                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            1                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       185429                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       185429                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       993608                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1011891                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2005499                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       993608                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1011891                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2005499                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        15053                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       273771                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       288824                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           42                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           42                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       115427                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       115427                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        15053                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       389198                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        404251                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        15053                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       389198                       # number of overall misses
system.cpu.l2cache.overall_misses::total       404251                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1161439993                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17964720233                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  19126160226                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       262498                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       262498                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9625411610                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9625411610                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1161439993                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  27590131843                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  28751571836                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1161439993                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  27590131843                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  28751571836                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1008661                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1100233                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2108894                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       840541                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       840541                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           62                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           62                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       300856                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       300856                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1008661                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1401089                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2409750                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1008661                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1401089                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2409750                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014924                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248830                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.136955                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.677419                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.677419                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383662                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.383662                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014924                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.277782                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.167756                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014924                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.277782                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.167756                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77156.712483                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65619.514971                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66220.813457                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  6249.952381                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  6249.952381                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83389.602173                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83389.602173                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77156.712483                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70889.706121                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71123.069172                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77156.712483                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70889.706121                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71123.069172                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        75916                       # number of writebacks
system.cpu.l2cache.writebacks::total            75916                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15052                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273771                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       288823                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           42                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           42                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115427                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       115427                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        15052                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       389198                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       404250                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        15052                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       389198                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       404250                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    971628757                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14552447267                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15524076024                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       573037                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       573037                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8203174390                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8203174390                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    971628757                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22755621657                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  23727250414                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    971628757                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22755621657                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  23727250414                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334007000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334007000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882413000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882413000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3216420000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3216420000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014923                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248830                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136955                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.677419                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.677419                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383662                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383662                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014923                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277782                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.167756                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014923                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277782                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.167756                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64551.472030                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53155.547034                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53749.445245                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13643.738095                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13643.738095                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71068.072375                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71068.072375                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64551.472030                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58467.981996                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58694.497004                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64551.472030                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58467.981996                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58694.497004                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1400496                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.994513                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            11811358                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1401008                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs              8.430614                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          25856000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.994513                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          415                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           94                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          63734677                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         63734677                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data      7206132                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total         7206132                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      4203012                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        4203012                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       186466                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       186466                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       215515                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       215515                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      11409144                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         11409144                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     11409144                       # number of overall hits
system.cpu.dcache.overall_hits::total        11409144                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1805019                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1805019                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1944584                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1944584                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22688                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22688                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      3749603                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3749603                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3749603                       # number of overall misses
system.cpu.dcache.overall_misses::total       3749603                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  40356893890                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  40356893890                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  77719104532                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  77719104532                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    321753501                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    321753501                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        13000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total        13000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 118075998422                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 118075998422                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 118075998422                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 118075998422                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data      9011151                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total      9011151                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6147596                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6147596                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209154                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       209154                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       215516                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       215516                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     15158747                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     15158747                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     15158747                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     15158747                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.200309                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.200309                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.316316                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.316316                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.108475                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.108475                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000005                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000005                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.247356                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.247356                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.247356                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.247356                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22358.154618                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22358.154618                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39966.956702                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39966.956702                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14181.659952                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14181.659952                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        13000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31490.266682                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31490.266682                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31490.266682                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31490.266682                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs      3050951                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          663                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             86776                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    35.158926                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    94.714286                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       840541                       # number of writebacks
system.cpu.dcache.writebacks::total            840541                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       721694                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       721694                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1644324                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1644324                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5123                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total         5123                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2366018                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2366018                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2366018                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2366018                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1083325                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1083325                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300260                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       300260                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17565                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        17565                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1383585                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1383585                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1383585                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1383585                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27323478009                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  27323478009                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11844407335                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11844407335                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    200869499                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    200869499                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        11000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        11000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  39167885344                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  39167885344                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  39167885344                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  39167885344                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424097000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424097000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997590998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997590998                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421687998                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421687998                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120220                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120220                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048842                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048842                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.083981                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.083981                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000005                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091273                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.091273                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091273                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.091273                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25221.866023                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25221.866023                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39447.170236                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39447.170236                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11435.781327                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11435.781327                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        11000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28308.983795                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28308.983795                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28308.983795                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28308.983795                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     6439                       # number of quiesce instructions executed
system.cpu.kern.inst.hwrei                     211003                       # number of hwrei instructions executed
system.cpu.kern.ipl_count::0                    74661     40.97%     40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22                    1879      1.03%     42.07% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31                  105563     57.93%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total               182234                       # number of times we switched to this ipl
system.cpu.kern.ipl_good::0                     73294     49.32%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31                    73294     49.32%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total                148598                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0             1817851866500     97.72%     97.72% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21                64172000      0.00%     97.73% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22               559556500      0.03%     97.76% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31             41715361500      2.24%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total         1860190956500                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0                  0.981691                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31                 0.694315                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total              0.815424                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
system.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
system.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
system.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
system.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
system.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
system.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
system.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
system.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
system.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
system.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
system.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
system.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
system.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
system.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
system.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
system.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
system.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
system.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
system.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
system.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
system.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
system.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
system.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
system.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
system.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
system.cpu.kern.syscall::total                    326                       # number of syscalls executed
system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
system.cpu.kern.callpal::swpipl                175119     91.23%     93.43% # number of callpals executed
system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # number of callpals executed
system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
system.cpu.kern.callpal::total                 191963                       # number of callpals executed
system.cpu.kern.mode_switch::kernel              5851                       # number of protection mode switches
system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
system.cpu.kern.mode_good::kernel                1910                      
system.cpu.kern.mode_good::user                  1740                      
system.cpu.kern.mode_good::idle                   170                      
system.cpu.kern.mode_switch_good::kernel     0.326440                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total      0.394384                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel        29573655500      1.59%      1.59% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user           2713841000      0.15%      1.74% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle         1827903452000     98.26%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed

---------- End Simulation Statistics   ----------
