
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000028                       # Number of seconds simulated
sim_ticks                                    28358000                       # Number of ticks simulated
final_tick                                   28358000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  50744                       # Simulator instruction rate (inst/s)
host_op_rate                                    91910                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              267330545                       # Simulator tick rate (ticks/s)
host_mem_usage                                 295388                       # Number of bytes of host memory used
host_seconds                                     0.11                       # Real time elapsed on the host
sim_insts                                        5381                       # Number of instructions simulated
sim_ops                                          9748                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             14528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
system.physmem.bytes_read::total                23104                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        14528                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           14528                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                227                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   361                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            512306933                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            302419070                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               814726003                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       512306933                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          512306933                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           512306933                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           302419070                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              814726003                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                    814726003                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                 282                       # Transaction distribution
system.membus.trans_dist::ReadResp                282                       # Transaction distribution
system.membus.trans_dist::ReadExReq                79                       # Transaction distribution
system.membus.trans_dist::ReadExResp               79                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          722                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total          722                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    722                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        23104                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total        23104                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total               23104                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                  23104                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy              361000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy            3249000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             11.5                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.workload.num_syscalls                   11                       # Number of system calls
system.cpu.numCycles                            56716                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                        5381                       # Number of instructions committed
system.cpu.committedOps                          9748                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses                  9654                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                         209                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts          899                       # number of instructions that are conditional controls
system.cpu.num_int_insts                         9654                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads               18335                       # number of times the integer registers were read
system.cpu.num_int_register_writes               7527                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads                 6487                       # number of times the CC registers were read
system.cpu.num_cc_register_writes                3536                       # number of times the CC registers were written
system.cpu.num_mem_refs                          1988                       # number of memory refs
system.cpu.num_load_insts                        1053                       # Number of load instructions
system.cpu.num_store_insts                        935                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                      56716                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.Branches                              1208                       # Number of branches fetched
system.cpu.icache.tags.replacements                 0                       # number of replacements
system.cpu.icache.tags.tagsinuse           105.550219                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                6637                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               228                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             29.109649                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   105.550219                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.051538                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.051538                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          228                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          132                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.111328                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses             13958                       # Number of tag accesses
system.cpu.icache.tags.data_accesses            13958                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst         6637                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            6637                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          6637                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             6637                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         6637                       # number of overall hits
system.cpu.icache.overall_hits::total            6637                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          228                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           228                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          228                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            228                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          228                       # number of overall misses
system.cpu.icache.overall_misses::total           228                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     12498000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     12498000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     12498000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     12498000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     12498000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     12498000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         6865                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         6865                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         6865                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         6865                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         6865                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         6865                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.033212                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.033212                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.033212                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.033212                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.033212                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.033212                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54815.789474                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54815.789474                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          228                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          228                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          228                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          228                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          228                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12042000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     12042000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12042000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     12042000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12042000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     12042000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.033212                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.033212                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.033212                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.033212                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.033212                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.033212                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          134.034140                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              282                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.003546                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   105.558330                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    28.475810                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003221                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.000869                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.004090                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          282                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.008606                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             3257                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            3257                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          227                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          282                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           79                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           79                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          227                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          134                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           361                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          227                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          134                       # number of overall misses
system.cpu.l2cache.overall_misses::total          361                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11804000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2860000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     14664000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4108000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      4108000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     11804000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      6968000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     18772000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     11804000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      6968000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     18772000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          228                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           55                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          283                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           79                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           79                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          228                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          134                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          362                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          228                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          134                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          362                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.995614                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.996466                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.995614                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.997238                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.995614                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.997238                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          227                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          282                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           79                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           79                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          227                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          134                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          361                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          227                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          361                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9080000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2200000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     11280000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3160000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3160000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9080000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5360000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     14440000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9080000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5360000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     14440000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.996466                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.997238                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.997238                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse            80.797237                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                1854                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               134                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             13.835821                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    80.797237                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.019726                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.019726                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          134                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          101                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.032715                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              4110                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             4110                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data          998                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total             998                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          856                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            856                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          1854                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             1854                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         1854                       # number of overall hits
system.cpu.dcache.overall_hits::total            1854                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            55                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data           79                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           79                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          134                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            134                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          134                       # number of overall misses
system.cpu.dcache.overall_misses::total           134                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      3025000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      3025000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      4345000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      4345000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data      7370000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total      7370000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data      7370000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total      7370000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1053                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1053                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          935                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          935                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         1988                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         1988                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         1988                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         1988                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052232                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.052232                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084492                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.084492                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.067404                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.067404                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.067404                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.067404                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        55000                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data        55000                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total        55000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data        55000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total        55000                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           55                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           79                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           79                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          134                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          134                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          134                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2915000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      2915000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4187000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      4187000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7102000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      7102000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7102000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      7102000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.052232                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.052232                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084492                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084492                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067404                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.067404                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067404                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.067404                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput               816982862                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq            283                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           283                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           79                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           79                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          456                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          268                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               724                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        14592                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8576                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total          23168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus             23168                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy         181000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        342000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        201000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
