
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.068245                       # Number of seconds simulated
sim_ticks                                 68245472000                       # Number of ticks simulated
final_tick                                68245472000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 123424                       # Simulator instruction rate (inst/s)
host_op_rate                                   157791                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               30849723                       # Simulator tick rate (ticks/s)
host_mem_usage                                 321440                       # Number of bytes of host memory used
host_seconds                                  2212.19                       # Real time elapsed on the host
sim_insts                                   273036725                       # Number of instructions simulated
sim_ops                                     349064449                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            193792                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            272576                       # Number of bytes read from this memory
system.physmem.bytes_read::total               466368                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       193792                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          193792                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3028                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               4259                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  7287                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              2839632                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3994053                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 6833684                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2839632                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2839632                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2839632                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3994053                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6833684                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          7288                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        7288                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   466432                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    466432                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 606                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 802                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 608                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 526                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 441                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 356                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 162                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 220                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 205                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 290                       # Per bank write bursts
system.physmem.perBankRdBursts::10                324                       # Per bank write bursts
system.physmem.perBankRdBursts::11                417                       # Per bank write bursts
system.physmem.perBankRdBursts::12                531                       # Per bank write bursts
system.physmem.perBankRdBursts::13                687                       # Per bank write bursts
system.physmem.perBankRdBursts::14                611                       # Per bank write bursts
system.physmem.perBankRdBursts::15                502                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     68245446000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    7288                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                      4342                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       590                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       174                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples          580                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      479.779310                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     274.986956                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     421.744260                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            159     27.41%     27.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          117     20.17%     47.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383           45      7.76%     55.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           23      3.97%     59.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           14      2.41%     61.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           13      2.24%     63.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            6      1.03%     65.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023            2      0.34%     65.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          201     34.66%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total            580                       # Bytes accessed per row activation
system.physmem.totQLat                       57907000                       # Total ticks spent queuing
system.physmem.totMemAccLat                 195684500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     36440000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                   101337500                       # Total ticks spent accessing banks
system.physmem.avgQLat                        7945.53                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    13904.71                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  26850.23                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           6.83                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        6.83                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.16                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       5839                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.12                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                      9364084.25                       # Average gap between requests
system.physmem.pageHitRate                      80.12                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               1.16                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                      6833684                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                4468                       # Transaction distribution
system.membus.trans_dist::ReadResp               4467                       # Transaction distribution
system.membus.trans_dist::ReadExReq              2820                       # Transaction distribution
system.membus.trans_dist::ReadExResp             2820                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14575                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  14575                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       466368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total              466368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                 466368                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy             8915000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           67732500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                35342667                       # Number of BP lookups
system.cpu.branchPred.condPredicted          21189046                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1621967                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             18355176                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                16729462                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             91.143021                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 6774978                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               8404                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  191                       # Number of system calls
system.cpu.numCycles                        136490945                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           38825213                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      317051968                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    35342667                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           23504440                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      70679896                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 6716000                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               21545367                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  106                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          1322                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           66                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  37451719                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                502899                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          136134435                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.985255                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.454681                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 66077496     48.54%     48.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  6747770      4.96%     53.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  5691244      4.18%     57.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  6070617      4.46%     62.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  4899295      3.60%     65.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  4080163      3.00%     68.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  3177720      2.33%     71.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  4131471      3.03%     74.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 35258659     25.90%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            136134435                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.258938                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.322879                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 45319095                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              16701200                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  66547822                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               2552537                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                5013781                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              7320658                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 69067                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              400437341                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                211449                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                5013781                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 50843684                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 1928767                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         335631                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  63516277                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              14496295                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              392925979                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    32                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1658279                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              10203172                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents            22306                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           431444746                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            2730832248                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1570013245                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups         200164445                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             384566193                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 46878553                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              11940                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          11939                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  36493417                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            103352368                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            91160183                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           4261604                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          5303451                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  383671023                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               22900                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 373754233                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1199031                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        33881433                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     97712598                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            780                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     136134435                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.745479                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.022556                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            24740289     18.17%     18.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            19905513     14.62%     32.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            20515084     15.07%     47.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            18158642     13.34%     61.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            24030824     17.65%     78.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            15691878     11.53%     90.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             8802431      6.47%     96.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             3372838      2.48%     99.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              916936      0.67%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       136134435                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                    8938      0.05%      0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   4692      0.03%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd             46049      0.26%      0.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp              3482      0.02%      0.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt               434      0.00%      0.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 2      0.00%      0.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc           186470      1.05%      1.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult             3938      0.02%      1.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc        241178      1.36%      2.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.80% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                9277159     52.37%     55.16% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               7942822     44.84%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             126226981     33.77%     33.77% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2175715      0.58%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    4      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         6775957      1.81%     36.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         8464752      2.26%     38.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         3426733      0.92%     39.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv         1595441      0.43%     39.78% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       20845390      5.58%     45.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult        7170609      1.92%     47.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc      7125607      1.91%     49.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt         175287      0.05%     49.23% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            101514689     27.16%     76.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            88257068     23.61%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              373754233                       # Type of FU issued
system.cpu.iq.rate                           2.738308                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    17715164                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.047398                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          653197592                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         287339977                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    249810515                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           249359504                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes          130249499                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses    118015221                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              262881293                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses               128588104                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         11104968                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      8703620                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       109542                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14223                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      8784600                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       184473                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          1790                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                5013781                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  291002                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 36408                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           383695470                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            852736                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             103352368                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             91160183                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              11866                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                    327                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                   282                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14223                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        1256888                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       362770                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1619658                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             369836414                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             100211998                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           3917819                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          1547                       # number of nop insts executed
system.cpu.iew.exec_refs                    187429987                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 31988466                       # Number of branches executed
system.cpu.iew.exec_stores                   87217989                       # Number of stores executed
system.cpu.iew.exec_rate                     2.709604                       # Inst execution rate
system.cpu.iew.wb_sent                      368475660                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     367825736                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 182824140                       # num instructions producing a value
system.cpu.iew.wb_consumers                 363330392                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       2.694873                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.503190                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        34630475                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1553283                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    131120654                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.662167                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.659302                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     34358811     26.20%     26.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     28410916     21.67%     47.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     13299289     10.14%     58.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     11469684      8.75%     66.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     13783827     10.51%     77.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7406623      5.65%     82.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      3875247      2.96%     85.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3903446      2.98%     88.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     14612811     11.14%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    131120654                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            273037337                       # Number of instructions committed
system.cpu.commit.committedOps              349065061                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      177024331                       # Number of memory references committed
system.cpu.commit.loads                      94648748                       # Number of loads committed
system.cpu.commit.membars                       11033                       # Number of memory barriers committed
system.cpu.commit.branches                   30563497                       # Number of branches committed
system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 279584611                       # Number of committed integer instructions.
system.cpu.commit.function_calls              6225112                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              14612811                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    500200856                       # The number of ROB reads
system.cpu.rob.rob_writes                   772408679                       # The number of ROB writes
system.cpu.timesIdled                            6691                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          356510                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   273036725                       # Number of Instructions Simulated
system.cpu.committedOps                     349064449                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             273036725                       # Number of Instructions Simulated
system.cpu.cpi                               0.499900                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.499900                       # CPI: Total CPI of All Threads
system.cpu.ipc                               2.000402                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         2.000402                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1768035388                       # number of integer regfile reads
system.cpu.int_regfile_writes               232615737                       # number of integer regfile writes
system.cpu.fp_regfile_reads                 188041949                       # number of floating regfile reads
system.cpu.fp_regfile_writes                132439422                       # number of floating regfile writes
system.cpu.misc_regfile_reads              1200568638                       # number of misc regfile reads
system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                20175639                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq          17638                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         17637                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback         1039                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         2838                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         2838                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31713                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10277                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             41990                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1014784                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       362112                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total        1376896                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus           1376896                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy       11796500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      24305488                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       7381711                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements             13966                       # number of replacements
system.cpu.icache.tags.tagsinuse          1849.581585                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            37434387                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             15856                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           2360.897263                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1849.581585                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.903116                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.903116                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1890                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          206                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1531                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.922852                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          74919290                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         74919290                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     37434387                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        37434387                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      37434387                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         37434387                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     37434387                       # number of overall hits
system.cpu.icache.overall_hits::total        37434387                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        17330                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         17330                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        17330                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          17330                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        17330                       # number of overall misses
system.cpu.icache.overall_misses::total         17330                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    451723484                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    451723484                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    451723484                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    451723484                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    451723484                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    451723484                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     37451717                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     37451717                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     37451717                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     37451717                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     37451717                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     37451717                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000463                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000463                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000463                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000463                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000463                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000463                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26065.982920                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 26065.982920                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 26065.982920                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 26065.982920                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 26065.982920                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 26065.982920                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1035                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                26                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    39.807692                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1473                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1473                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1473                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1473                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1473                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1473                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15857                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        15857                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        15857                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        15857                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        15857                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        15857                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    359348009                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    359348009                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    359348009                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    359348009                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    359348009                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    359348009                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000423                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000423                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000423                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000423                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000423                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000423                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22661.790313                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22661.790313                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22661.790313                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 22661.790313                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22661.790313                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 22661.790313                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         3939.930856                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              13213                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             5393                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             2.450028                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   375.867414                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2777.143346                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   786.920096                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.011471                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084752                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.024015                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.120237                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         5393                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1243                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4011                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.164581                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses           180351                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses          180351                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        12816                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data          303                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          13119                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks         1039                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total         1039                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           18                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           18                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        12816                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data          321                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           13137                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        12816                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data          321                       # number of overall hits
system.cpu.l2cache.overall_hits::total          13137                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3041                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         1478                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         4519                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         2820                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2820                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3041                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         4298                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          7339                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3041                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         4298                       # number of overall misses
system.cpu.l2cache.overall_misses::total         7339                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    215304250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    106779500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    322083750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    200114250                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    200114250                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    215304250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    306893750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    522198000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    215304250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    306893750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    522198000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        15857                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data         1781                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        17638                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks         1039                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total         1039                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         2838                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         2838                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        15857                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         4619                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        20476                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        15857                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         4619                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        20476                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.191777                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.829871                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.256208                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.993658                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.993658                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.191777                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.930504                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.358420                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.191777                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.930504                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.358420                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70800.476817                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72245.940460                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71273.235229                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70962.500000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70962.500000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70800.476817                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71403.850628                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71153.835672                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70800.476817                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71403.850628                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71153.835672                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           12                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           39                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           51                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           12                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           39                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           51                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           12                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           39                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           51                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3029                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1439                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         4468                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2820                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         2820                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3029                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         4259                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         7288                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3029                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         4259                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         7288                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    176626500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     86490250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    263116750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    165285750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    165285750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    176626500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    251776000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    428402500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    176626500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    251776000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    428402500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.191020                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.807973                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.253317                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.993658                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.993658                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.191020                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922061                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.355929                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.191020                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922061                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.355929                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58311.819082                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60104.412787                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58889.156222                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58611.968085                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58611.968085                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58311.819082                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59116.224466                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58781.901756                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58311.819082                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59116.224466                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58781.901756                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements              1416                       # number of replacements
system.cpu.dcache.tags.tagsinuse          3111.494128                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           170791722                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              4619                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          36975.908638                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  3111.494128                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.759642                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.759642                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         3203                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          686                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         2450                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.781982                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         341638239                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        341638239                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     88738255                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        88738255                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     82031563                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       82031563                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        11009                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        11009                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     170769818                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        170769818                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    170769818                       # number of overall hits
system.cpu.dcache.overall_hits::total       170769818                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         3984                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          3984                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        21102                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        21102                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data        25086                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total          25086                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data        25086                       # number of overall misses
system.cpu.dcache.overall_misses::total         25086                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data    232475203                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total    232475203                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   1255700879                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   1255700879                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       170250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       170250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   1488176082                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   1488176082                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   1488176082                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   1488176082                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     88742239                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     88742239                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     82052665                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     82052665                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11011                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        11011                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    170794904                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    170794904                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    170794904                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    170794904                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000045                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000257                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000257                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000182                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000182                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000147                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000147                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000147                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000147                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58352.209588                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 58352.209588                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59506.249597                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59506.249597                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85125                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85125                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59322.972255                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 59322.972255                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59322.972255                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 59322.972255                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        26768                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets         1267                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               424                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              13                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    63.132075                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    97.461538                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks         1039                       # number of writebacks
system.cpu.dcache.writebacks::total              1039                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2202                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total         2202                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18265                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        18265                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        20467                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        20467                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        20467                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        20467                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1782                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total         1782                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2837                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         2837                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         4619                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         4619                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         4619                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         4619                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    111706789                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    111706789                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    203137000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    203137000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    314843789                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    314843789                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    314843789                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    314843789                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62686.189113                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62686.189113                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71602.749383                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71602.749383                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68162.760121                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68162.760121                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68162.760121                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68162.760121                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
