
---------- Begin Simulation Statistics ----------
sim_seconds                                  2.550648                       # Number of seconds simulated
sim_ticks                                2550647964000                       # Number of ticks simulated
final_tick                               2550647964000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  57676                       # Simulator instruction rate (inst/s)
host_op_rate                                    74213                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2439007396                       # Simulator tick rate (ticks/s)
host_mem_usage                                 470664                       # Number of bytes of host memory used
host_seconds                                  1045.77                       # Real time elapsed on the host
sim_insts                                    60315890                       # Number of instructions simulated
sim_ops                                      77609880                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker         2048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           483008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          5043284                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           315584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4051356                       # Number of bytes read from this memory
system.physmem.bytes_read::total            131006576                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       483008                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       315584                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          798592                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3785856                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1521376                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       1494724                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6801956                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker           32                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              7547                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             78836                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              4931                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             63309                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15293483                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           59154                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           380344                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           373681                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               813179                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47482259                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           803                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              189367                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1977256                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           251                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              123727                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1588363                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51362077                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         189367                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         123727                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             313094                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1484272                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             596466                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data             586017                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2666756                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1484272                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47482259                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          803                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             189367                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            2573722                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          251                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             123727                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            2174381                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54028833                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15293483                       # Number of read requests accepted
system.physmem.writeReqs                       813179                       # Number of write requests accepted
system.physmem.readBursts                    15293483                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     813179                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                976671488                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                   2111424                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6834624                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 131006576                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6801956                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                    32991                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  706366                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4694                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              955809                       # Per bank write bursts
system.physmem.perBankRdBursts::1              953120                       # Per bank write bursts
system.physmem.perBankRdBursts::2              953063                       # Per bank write bursts
system.physmem.perBankRdBursts::3              953290                       # Per bank write bursts
system.physmem.perBankRdBursts::4              955524                       # Per bank write bursts
system.physmem.perBankRdBursts::5              952811                       # Per bank write bursts
system.physmem.perBankRdBursts::6              952747                       # Per bank write bursts
system.physmem.perBankRdBursts::7              952554                       # Per bank write bursts
system.physmem.perBankRdBursts::8              956154                       # Per bank write bursts
system.physmem.perBankRdBursts::9              953015                       # Per bank write bursts
system.physmem.perBankRdBursts::10             952848                       # Per bank write bursts
system.physmem.perBankRdBursts::11             952579                       # Per bank write bursts
system.physmem.perBankRdBursts::12             956184                       # Per bank write bursts
system.physmem.perBankRdBursts::13             953741                       # Per bank write bursts
system.physmem.perBankRdBursts::14             953594                       # Per bank write bursts
system.physmem.perBankRdBursts::15             953459                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6616                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6407                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6542                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6564                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6491                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6761                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6753                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6706                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7029                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6806                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6476                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6118                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7056                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6677                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6959                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6830                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2550646795500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                      44                       # Read request sizes (log2)
system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  154623                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 754025                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  59154                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1055042                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    994364                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    947765                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    947544                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    945397                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                    945218                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2783572                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   2783267                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   3699218                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     24042                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    23218                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    23233                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    22770                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    22263                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    21886                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    21619                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       50                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       16                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       297                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       290                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       284                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       277                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       277                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       276                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       273                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       269                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2390                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3959                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4958                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5019                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5011                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4981                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5456                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5074                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5855                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5373                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4897                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4875                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4842                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      982                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1034                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      915                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      954                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      918                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      899                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      867                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      895                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      858                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      852                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      852                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      853                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      851                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      847                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      846                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      844                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      863                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       965273                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean     1013.486813                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     999.850047                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev      92.541667                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           4202      0.44%      0.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         3517      0.36%      0.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         1855      0.19%      0.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1291      0.13%      1.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          949      0.10%      1.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          717      0.07%      1.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          589      0.06%      1.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          765      0.08%      1.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       951388     98.56%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         965273                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5001                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      3051.486103                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    52637.524815                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-65535          4974     99.46%     99.46% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::65536-131071            1      0.02%     99.48% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::131072-196607            8      0.16%     99.64% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-262143            6      0.12%     99.76% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::393216-458751            1      0.02%     99.78% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::589824-655359            2      0.04%     99.82% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.84% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06            7      0.14%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5001                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5001                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        21.353929                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.695200                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        9.701170                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1                   8      0.16%      0.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2                   2      0.04%      0.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3                   3      0.06%      0.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4                   1      0.02%      0.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5                   8      0.16%      0.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::6                   1      0.02%      0.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::7                   1      0.02%      0.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8                   3      0.06%      0.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::9                   5      0.10%      0.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::10                  2      0.04%      0.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::11                  5      0.10%      0.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12                  2      0.04%      0.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::13                  1      0.02%      0.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::14                  1      0.02%      0.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::15                 10      0.20%      1.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               2816     56.31%     57.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 26      0.52%     57.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                135      2.70%     60.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                879     17.58%     78.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 49      0.98%     79.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 23      0.46%     79.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 15      0.30%     79.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 25      0.50%     80.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 14      0.28%     80.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 18      0.36%     81.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  7      0.14%     81.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                 15      0.30%     81.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                 16      0.32%     81.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                 18      0.36%     82.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                 15      0.30%     82.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                  8      0.16%     82.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                 16      0.32%     82.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33                 10      0.20%     83.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  1      0.02%     83.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39                  1      0.02%     83.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40                  3      0.06%     83.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41                243      4.86%     88.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42                480      9.60%     97.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43                 27      0.54%     98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44                 20      0.40%     98.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45                 27      0.54%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46                 21      0.42%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47                 16      0.32%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48                  2      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::49                  1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5001                       # Writes before turning the bus around for reads
system.physmem.totQLat                   577566851750                       # Total ticks spent queuing
system.physmem.totMemAccLat              682115428000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  76302460000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                 28246116250                       # Total ticks spent accessing banks
system.physmem.avgQLat                       37847.20                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                     1850.93                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44698.13                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         382.91                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.68                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       51.36                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.67                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.01                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.99                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         6.73                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        15.38                       # Average write queue length when enqueuing
system.physmem.readRowHits                   14274135                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     91331                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.54                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  85.51                       # Row buffer hit rate for writes
system.physmem.avgGap                       158359.74                       # Average gap between requests
system.physmem.pageHitRate                      93.48                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               4.60                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     54969038                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16346130                       # Transaction distribution
system.membus.trans_dist::ReadResp           16346133                       # Transaction distribution
system.membus.trans_dist::WriteReq             763365                       # Transaction distribution
system.membus.trans_dist::WriteResp            763365                       # Transaction distribution
system.membus.trans_dist::Writeback             59154                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4693                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4694                       # Transaction distribution
system.membus.trans_dist::ReadExReq            131434                       # Transaction distribution
system.membus.trans_dist::ReadExResp           131434                       # Transaction distribution
system.membus.trans_dist::LoadLockedReq             3                       # Transaction distribution
system.membus.trans_dist::StoreCondReq              3                       # Transaction distribution
system.membus.trans_dist::StoreCondResp             3                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383060                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3790                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1885926                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4272780                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34550412                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390486                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio         7580                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16698004                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     19096138                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           140206666                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              140206666                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1487459000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3645000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         17565357500                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4737629056                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        37816335199                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    64394                       # number of replacements
system.l2c.tags.tagsinuse                51423.269942                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1904392                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   129782                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    14.673776                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             2513283956500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   36971.606132                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    22.825180                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000372                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4577.267389                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3052.603978                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     7.951997                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3614.635006                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3176.379887                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.564142                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000348                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.069844                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.046579                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000121                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.055155                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.048468                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.784657                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           21                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65367                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3070                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6838                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55080                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000320                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.997421                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 18929537                       # Number of tag accesses
system.l2c.tags.data_accesses                18929537                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker        32378                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         6463                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             508619                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             187861                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        31368                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         7240                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             462078                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             199585                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1435592                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          608227                       # number of Writeback hits
system.l2c.Writeback_hits::total               608227                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              20                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              19                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  39                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             5                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data             6                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                11                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            60126                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            52843                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               112969                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker         32378                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          6463                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              508619                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              247987                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         31368                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          7240                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              462078                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              252428                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1548561                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        32378                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         6463                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             508619                       # number of overall hits
system.l2c.overall_hits::cpu0.data             247987                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        31368                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         7240                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             462078                       # number of overall hits
system.l2c.overall_hits::cpu1.data             252428                       # number of overall hits
system.l2c.overall_hits::total                1548561                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           32                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7439                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6013                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           10                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             4938                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4716                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                23150                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1629                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1286                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2915                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          73716                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          59496                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133212                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           32                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7439                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             79729                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           10                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              4938                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             64212                       # number of demand (read+write) misses
system.l2c.demand_misses::total                156362                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           32                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7439                       # number of overall misses
system.l2c.overall_misses::cpu0.data            79729                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           10                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             4938                       # number of overall misses
system.l2c.overall_misses::cpu1.data            64212                       # number of overall misses
system.l2c.overall_misses::total               156362                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      2459000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       158000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    535184750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    452595249                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       747500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    359066750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    362580750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1712791999                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       209991                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       255489                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       465480                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   5481304360                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4400908112                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9882212472                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      2459000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       158000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    535184750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   5933899609                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       747500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    359066750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   4763488862                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     11595004471                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      2459000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       158000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    535184750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   5933899609                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       747500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    359066750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   4763488862                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    11595004471                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker        32410                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         6465                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         516058                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         193874                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        31378                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7240                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         467016                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         204301                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1458742                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       608227                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           608227                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1649                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1305                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2954                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            6                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            6                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            12                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       133842                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       112339                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246181                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        32410                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         6465                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          516058                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          327716                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        31378                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7240                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          467016                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          316640                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1704923                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        32410                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         6465                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         516058                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         327716                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        31378                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7240                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         467016                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         316640                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1704923                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000987                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000309                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.014415                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.031015                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000319                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010574                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.023084                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.015870                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.987871                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.985441                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.986798                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.166667                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.083333                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.550769                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.529611                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.541114                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000987                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000309                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014415                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.243287                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000319                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010574                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.202792                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.091712                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000987                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000309                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014415                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.243287                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000319                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010574                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.202792                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.091712                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 76843.750000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        79000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71943.103912                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 75269.457675                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72715.016201                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76883.110687                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 73986.695421                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   128.907919                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   198.669518                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   159.684391                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74357.050844                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73969.814979                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 74184.101072                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 76843.750000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        79000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 71943.103912                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 74425.862722                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 72715.016201                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 74183.779698                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 74154.874400                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 76843.750000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        79000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 71943.103912                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 74425.862722                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 72715.016201                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 74183.779698                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 74154.874400                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               59154                       # number of writebacks
system.l2c.writebacks::total                    59154                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            40                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            22                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                78                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             40                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             22                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 78                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            40                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            22                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                78                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           32                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         7430                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         5973                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           10                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         4931                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4694                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           23072                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1629                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1286                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2915                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        73716                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        59496                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        133212                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           32                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         7430                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        79689                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           10                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         4931                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        64190                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           156284                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           32                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         7430                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        79689                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           10                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         4931                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        64190                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          156284                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2062500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       133500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    441209000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    375003749                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    296681500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    302775000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1418490249                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     16291629                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     12864285                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     29155914                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        10001                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4563686640                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3660844388                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8224531028                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2062500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       133500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    441209000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   4938690389                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    296681500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   3963619388                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   9643021277                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2062500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       133500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    441209000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   4938690389                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    296681500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   3963619388                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   9643021277                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6566249                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83827031250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83117321750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166950919249                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8951884751                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8422103999                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  17373988750                       # number of WriteReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       116250                       # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total       116250                       # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data        60000                       # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total        60000                       # number of StoreCondReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6566249                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92778916001                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91539425749                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184324907999                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000987                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000309                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014398                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.030809                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000319                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010559                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.022976                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.015816                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.987871                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.985441                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.986798                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.166667                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.083333                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.550769                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.529611                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.541114                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000987                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000309                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014398                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.243165                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000319                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010559                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.202722                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.091666                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000987                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000309                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014398                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.243165                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000319                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010559                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.202722                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.091666                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59382.099596                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62783.149004                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60166.599067                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64502.556455                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 61481.026742                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.332037                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.028816                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61909.037929                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61530.932970                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61740.166261                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59382.099596                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61974.555949                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60166.599067                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61748.237856                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 61701.909837                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59382.099596                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61974.555949                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60166.599067                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61748.237856                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 61701.909837                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    58424320                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2676714                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2676716                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            763365                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           763365                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           608227                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2954                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            12                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2966                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           246181                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          246181                       # Transaction distribution
system.toL2Bus.trans_dist::LoadLockedReq            3                       # Transaction distribution
system.toL2Bus.trans_dist::StoreCondReq             3                       # Transaction distribution
system.toL2Bus.trans_dist::StoreCondResp            3                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1967568                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5797861                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        37552                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       149979                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7952960                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     62924224                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     85579658                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        54820                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       255152                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          148813854                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             148813854                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus          206020                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4963822946                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4432706696                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        4484503287                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          23902881                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          86618127                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      48419467                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16322169                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16322169                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8177                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8177                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7940                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          522                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1030                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2383060                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                32660692                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15880                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1044                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2060                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390486                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            123501014                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               123501014                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              3975000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               522000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               521000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374883000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         37825687801                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
system.cpu0.branchPred.lookups                7508483                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          5992866                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           375676                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups             4822577                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                3918936                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            81.262279                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 722501                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             39246                       # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    25709068                       # DTB read hits
system.cpu0.dtb.read_misses                     39624                       # DTB read misses
system.cpu0.dtb.write_hits                    6152335                       # DTB write hits
system.cpu0.dtb.write_misses                    10221                       # DTB write misses
system.cpu0.dtb.flush_tlb                         514                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                760                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    5608                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                     1406                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   264                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      646                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                25748692                       # DTB read accesses
system.cpu0.dtb.write_accesses                6162556                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         31861403                       # DTB hits
system.cpu0.dtb.misses                          49845                       # DTB misses
system.cpu0.dtb.accesses                     31911248                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                     5876098                       # ITB inst hits
system.cpu0.itb.inst_misses                      7014                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         514                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                760                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2644                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1469                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 5883112                       # ITB inst accesses
system.cpu0.itb.hits                          5876098                       # DTB hits
system.cpu0.itb.misses                           7014                       # DTB misses
system.cpu0.itb.accesses                      5883112                       # DTB accesses
system.cpu0.numCycles                       242192321                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          15567613                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      45445847                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    7508483                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           4641437                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     10272972                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2435180                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                     81106                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              50250706                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                1544                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             1986                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles        48114                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles      1489776                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          378                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  5874191                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               367063                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   2900                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples          79394723                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.721041                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.068559                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                69128739     87.07%     87.07% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  676261      0.85%     87.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                  870795      1.10%     89.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 1169302      1.47%     90.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1115285      1.40%     91.90% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  553948      0.70%     92.59% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 1287197      1.62%     94.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  378519      0.48%     94.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4214677      5.31%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            79394723                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.031002                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.187644                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                16658432                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             51288095                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  9197431                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               656874                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1591763                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1006093                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                91406                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              54494283                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               303520                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1591763                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                17551658                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               20345183                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      27653568                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  8896202                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              3354292                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              51932303                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                  196                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                500448                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              2179621                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents             261                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           53595851                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            240832893                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       219678051                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             5082                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             39195467                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                14400384                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            591696                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        540219                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  6961736                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            10014185                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            6974197                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1050889                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1353332                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  48232956                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1025841                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 61971057                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            88766                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        9957722                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     24611703                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        275811                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples     79394723                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.780544                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.499047                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           56910995     71.68%     71.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1            7345017      9.25%     80.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            3503110      4.41%     85.34% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            2918035      3.68%     89.02% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            6157997      7.76%     96.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1482939      1.87%     98.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             783446      0.99%     99.63% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             227116      0.29%     99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              66068      0.08%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total       79394723                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  29670      0.67%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     1      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4193006     94.32%     94.99% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               222912      5.01%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            15869      0.03%      0.03% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             29065604     46.90%     46.93% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               46869      0.08%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                 10      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              7      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.00% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          1239      0.00%     47.01% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     47.01% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc           10      0.00%     47.01% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.01% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            26385475     42.58%     89.58% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            6455974     10.42%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              61971057                       # Type of FU issued
system.cpu0.iq.rate                          0.255875                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    4445589                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.071737                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         207909567                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         59225484                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     43186225                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              11292                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              6130                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5133                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              66394829                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   5948                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          311727                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2130667                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         3740                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        15655                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       850179                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads     17067257                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       348827                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1591763                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               15715155                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               239745                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           49373573                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           105603                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             10014185                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             6974197                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            727713                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 55741                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 4727                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         15655                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        183161                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       144870                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              328031                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             60906320                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             26058550                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          1064737                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       114776                       # number of nop insts executed
system.cpu0.iew.exec_refs                    32455686                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 5967734                       # Number of branches executed
system.cpu0.iew.exec_stores                   6397136                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.251479                       # Inst execution rate
system.cpu0.iew.wb_sent                      60414213                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     43191358                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 23287316                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 42834885                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.178335                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.543653                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        9785836                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls         750030                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           285660                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples     77802960                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.502286                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.465598                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     63388396     81.47%     81.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      7400911      9.51%     90.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      1988257      2.56%     93.54% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1098992      1.41%     94.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4       865715      1.11%     96.07% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       575312      0.74%     96.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       733525      0.94%     97.75% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       350428      0.45%     98.20% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1401424      1.80%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total     77802960                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            29900744                       # Number of instructions committed
system.cpu0.commit.committedOps              39079359                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      14007536                       # Number of memory references committed
system.cpu0.commit.loads                      7883518                       # Number of loads committed
system.cpu0.commit.membars                     209346                       # Number of memory barriers committed
system.cpu0.commit.branches                   5162239                       # Number of branches committed
system.cpu0.commit.fp_insts                      5086                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 34792812                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              507721                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1401424                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   124291086                       # The number of ROB reads
system.cpu0.rob.rob_writes                   99365166                       # The number of ROB writes
system.cpu0.timesIdled                         908697                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                      162797598                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  2248209209                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   29823122                       # Number of Instructions Simulated
system.cpu0.committedOps                     39001737                       # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total             29823122                       # Number of Instructions Simulated
system.cpu0.cpi                              8.120958                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        8.120958                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.123138                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.123138                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               276680521                       # number of integer regfile reads
system.cpu0.int_regfile_writes               43875243                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                    44965                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                   42348                       # number of floating regfile writes
system.cpu0.misc_regfile_reads              137565982                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                581037                       # number of misc regfile writes
system.cpu0.icache.tags.replacements           983714                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.569506                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           10510100                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           984226                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.678543                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       7060452000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   317.023627                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   194.545879                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.619187                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.379972                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999159                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          163                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         12559701                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        12559701                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst      5314791                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      5195309                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       10510100                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst      5314791                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      5195309                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        10510100                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst      5314791                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      5195309                       # number of overall hits
system.cpu0.icache.overall_hits::total       10510100                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       559278                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       506065                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1065343                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       559278                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       506065                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1065343                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       559278                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       506065                       # number of overall misses
system.cpu0.icache.overall_misses::total      1065343                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7693667190                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6830219775                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  14523886965                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   7693667190                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   6830219775                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  14523886965                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   7693667190                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   6830219775                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  14523886965                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst      5874069                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      5701374                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     11575443                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst      5874069                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      5701374                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     11575443                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst      5874069                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      5701374                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     11575443                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.095211                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.088762                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.092035                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.095211                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.088762                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.092035                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.095211                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.088762                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.092035                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13756.427376                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13496.724284                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13633.061807                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13756.427376                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13496.724284                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13633.061807                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13756.427376                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13496.724284                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13633.061807                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         6850                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              406                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.871921                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        42606                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        38478                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        81084                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        42606                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst        38478                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        81084                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        42606                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst        38478                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        81084                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       516672                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       467587                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       984259                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       516672                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       467587                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       984259                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       516672                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       467587                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       984259                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6254333936                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5558733090                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11813067026                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6254333936                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5558733090                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11813067026                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6254333936                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5558733090                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11813067026                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      9017250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      9017250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      9017250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total      9017250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.087958                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.082013                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085030                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.087958                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.082013                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.085030                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.087958                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.082013                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.085030                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12105.037502                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11888.125825                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12001.990356                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12105.037502                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11888.125825                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12001.990356                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12105.037502                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11888.125825                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12001.990356                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           643844                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.993221                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           21529454                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           644356                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            33.412359                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         43687250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   256.274589                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   255.718633                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.500536                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.499450                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          190                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          304                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        101648096                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       101648096                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      7014056                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      6760706                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       13774762                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3747600                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      3513292                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       7260892                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       116614                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       126440                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       243054                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       119391                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       128245                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247636                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10761656                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     10273998                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        21035654                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10761656                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     10273998                       # number of overall hits
system.cpu0.dcache.overall_hits::total       21035654                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       333491                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       414863                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       748354                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1635288                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1327358                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2962646                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7514                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         6065                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        13579                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            6                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            6                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      1968779                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      1742221                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3711000                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      1968779                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      1742221                       # number of overall misses
system.cpu0.dcache.overall_misses::total      3711000                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5348440293                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6102853229                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  11451293522                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  83999211786                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  64837852526                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 148837064312                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    107360498                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     81153996                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    188514494                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        90501                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        78000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       168501                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  89347652079                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  70940705755                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 160288357834                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  89347652079                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  70940705755                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 160288357834                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      7347547                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      7175569                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     14523116                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5382888                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      4840650                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10223538                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124128                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       132505                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       256633                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       119397                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       128251                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247648                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12730435                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     12016219                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     24746654                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12730435                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     12016219                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     24746654                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.045388                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.057816                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.051528                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.303794                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.274211                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.289787                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060534                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.045772                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.052912                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000050                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000047                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000048                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.154651                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.144989                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.149960                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.154651                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.144989                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.149960                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16037.735030                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14710.526677                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15301.974095                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51366.616636                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 48847.298563                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 50237.883403                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14288.062018                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13380.708326                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13882.796524                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15083.500000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        13000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14041.750000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45382.265901                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40718.545899                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 43192.766864                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45382.265901                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40718.545899                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 43192.766864                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs        37128                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        22269                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs             3473                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            273                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    10.690469                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    81.571429                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       608227                       # number of writebacks
system.cpu0.dcache.writebacks::total           608227                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       146313                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       215949                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       362262                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1499850                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1213774                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      2713624                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          765                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          618                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1383                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1646163                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      1429723                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      3075886                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1646163                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      1429723                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      3075886                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       187178                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       198914                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       386092                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       135438                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       113584                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       249022                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6749                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5447                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12196                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            6                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            6                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       322616                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       312498                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       635114                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       322616                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       312498                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       635114                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2596085748                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2657791594                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5253877342                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6365986816                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5155346718                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11521333534                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     84972752                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62985504                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    147958256                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        78499                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        66000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       144499                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8962072564                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7813138312                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  16775210876                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8962072564                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7813138312                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  16775210876                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91546998750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90791256750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182338255500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13710487847                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  13068639684                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26779127531                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       155750                       # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total       155750                       # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data        96000                       # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total        96000                       # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105257486597                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103859896434                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209117383031                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.025475                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.027721                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026585                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025161                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.023465                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024358                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.054371                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.041108                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.047523                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000050                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000047                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000048                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025342                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026006                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.025665                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.025342                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.026006                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.025665                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13869.609399                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.510975                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13607.837878                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47002.959406                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45387.965893                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46266.328011                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12590.421099                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11563.338351                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.703509                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        11000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12041.583333                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27779.380328                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25002.202612                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26412.913077                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27779.380328                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25002.202612                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26412.913077                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total          inf                       # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total          inf                       # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups                7323132                       # Number of BP lookups
system.cpu1.branchPred.condPredicted          5902490                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           346200                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups             4511574                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                3765481                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            83.462690                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                 676459                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect             34463                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    25506602                       # DTB read hits
system.cpu1.dtb.read_misses                     36488                       # DTB read misses
system.cpu1.dtb.write_hits                    5558527                       # DTB write hits
system.cpu1.dtb.write_misses                     8439                       # DTB write misses
system.cpu1.dtb.flush_tlb                         510                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                679                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    5463                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     2276                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   232                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      679                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                25543090                       # DTB read accesses
system.cpu1.dtb.write_accesses                5566966                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         31065129                       # DTB hits
system.cpu1.dtb.misses                          44927                       # DTB misses
system.cpu1.dtb.accesses                     31110056                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                     5703436                       # ITB inst hits
system.cpu1.itb.inst_misses                      7020                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         510                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                679                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2688                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     1487                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 5710456                       # ITB inst accesses
system.cpu1.itb.hits                          5703436                       # DTB hits
system.cpu1.itb.misses                           7020                       # DTB misses
system.cpu1.itb.accesses                      5710456                       # DTB accesses
system.cpu1.numCycles                       237056909                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          14419718                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      45234990                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    7323132                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           4441940                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                      9947853                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                2287798                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     84999                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              49482147                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                1272                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             1896                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles        44871                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles      1235484                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          189                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  5701379                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               352457                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   3064                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples          76794959                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.726229                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.078871                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                66855647     87.06%     87.06% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  632615      0.82%     87.88% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  843009      1.10%     88.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 1133482      1.48%     90.45% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1002056      1.30%     91.76% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  554704      0.72%     92.48% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1272745      1.66%     94.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  372184      0.48%     94.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 4128517      5.38%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            76794959                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.030892                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.190819                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                15530724                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             50222847                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                  8895356                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               650267                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1493551                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              963840                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                85500                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              53154493                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               286161                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1493551                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                16374919                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               19306160                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      27715779                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                  8656578                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              3245827                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              50687701                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                  339                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                605911                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents              2002092                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents             648                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           53113804                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            234485879                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       214384735                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             5365                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             39540919                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                13572884                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            579809                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        536931                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  6499660                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads             9772559                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            6360216                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           888468                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         1099515                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  47171321                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             962588                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 61070577                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued            91971                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        9248404                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     23463374                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        229936                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     76794959                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.795242                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.505673                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           54534134     71.01%     71.01% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            7328500      9.54%     80.56% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            3483988      4.54%     85.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            2874889      3.74%     88.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            6131286      7.98%     96.82% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1377966      1.79%     98.61% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             776904      1.01%     99.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             225300      0.29%     99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              61992      0.08%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       76794959                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  29712      0.67%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     3      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.67% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4180230     94.88%     95.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               195658      4.44%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass            12649      0.02%      0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             28971083     47.44%     47.46% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               46630      0.08%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                 12      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              7      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc           875      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.54% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            26162080     42.84%     90.38% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            5877234      9.62%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              61070577                       # Type of FU issued
system.cpu1.iq.rate                          0.257620                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    4405603                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.072140                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         203466895                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         57390461                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     42382296                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              11528                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              6422                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5160                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              65457468                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   6063                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          311906                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      1999074                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         3048                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        15122                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       750838                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads     17042744                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked       332080                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1493551                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               14864582                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               222698                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           48241525                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts            96453                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts              9772559                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             6360216                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            687199                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 48610                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 4313                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         15122                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        168053                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       134565                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              302618                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             60042253                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             25845364                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          1028324                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       107616                       # number of nop insts executed
system.cpu1.iew.exec_refs                    31671376                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 5872062                       # Number of branches executed
system.cpu1.iew.exec_stores                   5826012                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.253282                       # Inst execution rate
system.cpu1.iew.wb_sent                      59578158                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     42387456                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 23643387                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 43005248                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.178807                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.549779                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        9166908                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         732652                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           262014                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     75301408                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.513681                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.486972                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     60995111     81.00%     81.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      7470337      9.92%     90.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1928698      2.56%     93.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3      1074141      1.43%     94.91% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       820415      1.09%     96.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       494186      0.66%     96.66% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       699344      0.93%     97.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       371316      0.49%     98.08% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1447860      1.92%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     75301408                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            30565527                       # Number of instructions committed
system.cpu1.commit.committedOps              38680902                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      13382863                       # Number of memory references committed
system.cpu1.commit.loads                      7773485                       # Number of loads committed
system.cpu1.commit.membars                     194338                       # Number of memory barriers committed
system.cpu1.commit.branches                   5145142                       # Number of branches committed
system.cpu1.commit.fp_insts                      5126                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 34406663                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              483721                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1447860                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   120827478                       # The number of ROB reads
system.cpu1.rob.rob_writes                   97232532                       # The number of ROB writes
system.cpu1.timesIdled                         865086                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                      160261950                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  2316983227                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   30492768                       # Number of Instructions Simulated
system.cpu1.committedOps                     38608143                       # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total             30492768                       # Number of Instructions Simulated
system.cpu1.cpi                              7.774201                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        7.774201                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.128631                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.128631                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               272500909                       # number of integer regfile reads
system.cpu1.int_regfile_writes               43779735                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                    45015                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                   42294                       # number of floating regfile writes
system.cpu1.misc_regfile_reads              133085319                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                592959                       # number of misc regfile writes
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736889440801                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1736889440801                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736889440801                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1736889440801                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   83061                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------
