
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.202387                       # Number of seconds simulated
sim_ticks                                202386636500                       # Number of ticks simulated
final_tick                               202386636500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 118405                       # Simulator instruction rate (inst/s)
host_op_rate                                   133495                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               47430504                       # Simulator tick rate (ticks/s)
host_mem_usage                                 317288                       # Number of bytes of host memory used
host_seconds                                  4267.01                       # Real time elapsed on the host
sim_insts                                   505237723                       # Number of instructions simulated
sim_ops                                     569624283                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            215296                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9261568                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9476864                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       215296                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          215296                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6245824                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6245824                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3364                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             144712                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                148076                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97591                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97591                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              1063786                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             45761757                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                46825542                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1063786                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1063786                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          30860852                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               30860852                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          30860852                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1063786                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            45761757                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               77686394                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        148077                       # Number of read requests accepted
system.physmem.writeReqs                        97591                       # Number of write requests accepted
system.physmem.readBursts                      148077                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97591                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9467712                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9216                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6243712                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9476928                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6245824                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      144                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              9                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9595                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9241                       # Per bank write bursts
system.physmem.perBankRdBursts::2                9230                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8948                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9774                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9652                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9107                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8317                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8793                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8911                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8931                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9713                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9649                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9746                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8931                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9395                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6267                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6152                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6088                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5869                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6257                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6287                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6043                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5545                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5805                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5895                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5984                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6504                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6370                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6330                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6044                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6118                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    202386616500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  148077                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97591                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    138091                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      9280                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       494                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        59                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1942                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2625                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4944                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5396                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5464                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5554                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5550                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5554                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6518                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5915                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5951                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5705                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5565                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      917                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      289                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      217                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        39628                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      257.573029                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     159.018208                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     287.256707                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          15558     39.26%     39.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11171     28.19%     67.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4346     10.97%     78.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2186      5.52%     83.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1365      3.44%     87.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          780      1.97%     89.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          563      1.42%     90.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          515      1.30%     92.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3144      7.93%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          39628                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5484                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        26.971554                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      384.653172                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5482     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5484                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5484                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.789570                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.450739                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        4.762634                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            3346     61.01%     61.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            1810     33.01%     94.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21             182      3.32%     97.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              11      0.20%     97.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25               3      0.05%     97.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27               4      0.07%     97.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29               3      0.05%     97.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31               1      0.02%     97.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33               3      0.05%     97.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35               1      0.02%     97.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37               1      0.02%     97.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39              12      0.22%     98.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41              29      0.53%     98.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43              19      0.35%     98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45               8      0.15%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47               7      0.13%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49               7      0.13%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51               8      0.15%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53               9      0.16%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54-55               6      0.11%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-57               4      0.07%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58-59               3      0.05%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::62-63               1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-65               2      0.04%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::66-67               1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-73               1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-77               1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::90-91               1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5484                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1351646500                       # Total ticks spent queuing
system.physmem.totMemAccLat                4559189000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    739665000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  2467877500                       # Total ticks spent accessing banks
system.physmem.avgQLat                        9136.88                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    16682.40                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30819.28                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          46.78                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          30.85                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       46.83                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       30.86                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.61                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.37                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.24                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        20.36                       # Average write queue length when enqueuing
system.physmem.readRowHits                     116029                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     64903                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   78.43                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  66.51                       # Row buffer hit rate for writes
system.physmem.avgGap                       823821.65                       # Average gap between requests
system.physmem.pageHitRate                      73.69                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               4.51                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     77686394                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               46784                       # Transaction distribution
system.membus.trans_dist::ReadResp              46783                       # Transaction distribution
system.membus.trans_dist::Writeback             97591                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                9                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               9                       # Transaction distribution
system.membus.trans_dist::ReadExReq            101293                       # Transaction distribution
system.membus.trans_dist::ReadExResp           101293                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       393762                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 393762                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15722688                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            15722688                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               15722688                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1083423500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1396187241                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               182802497                       # Number of BP lookups
system.cpu.branchPred.condPredicted         143128799                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           7265604                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             92710665                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                87222146                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             94.079949                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                12678300                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             116271                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        404773274                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          119371431                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      761670050                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   182802497                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           99900446                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     170159805                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                35695191                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               77489066                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   40                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           409                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           15                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 114520254                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2435167                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          394646362                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.164609                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.986746                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                224499175     56.89%     56.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 14180048      3.59%     60.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 22900330      5.80%     66.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 22746018      5.76%     72.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 20904181      5.30%     77.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 11597078      2.94%     80.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 13062660      3.31%     83.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 11996924      3.04%     86.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 52759948     13.37%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            394646362                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.451617                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.881720                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                129065441                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              72977589                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 158843318                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               6208520                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               27551494                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             26113840                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 76933                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              825615862                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                295408                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               27551494                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                135663599                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                10124037                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       47858907                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 158270703                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              15177622                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              800676203                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  1362                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                3041401                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               8927839                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              380                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           954380743                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3518821037                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3237543722                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               408                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             666252291                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                288128452                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            2293069                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        2293066                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  41767697                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            170285712                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            73492930                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          28608200                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         15804502                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  755130380                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             3775454                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 665331830                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1375167                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       187454297                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    480174835                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         797822                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     394646362                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.685894                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.735410                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           139160941     35.26%     35.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            69972049     17.73%     52.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            71433490     18.10%     71.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            53381143     13.53%     84.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            31203736      7.91%     92.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            16006372      4.06%     96.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             8742132      2.22%     98.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             2922216      0.74%     99.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1824283      0.46%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       394646362                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  481604      5.01%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                6543314     68.07%     73.08% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2587932     26.92%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             447808389     67.31%     67.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               383403      0.06%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                  94      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            153377795     23.05%     90.42% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            63762146      9.58%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              665331830                       # Type of FU issued
system.cpu.iq.rate                           1.643715                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     9612850                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014448                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1736297816                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         947166381                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    646062448                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 223                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                298                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              674944567                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     113                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          8567764                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     44256157                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        42344                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       810357                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     16632453                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        19504                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          8568                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               27551494                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 5275843                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                386509                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           760464256                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1125230                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             170285712                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             73492930                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            2286912                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 220350                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 11309                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         810357                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        4338774                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4002387                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8341161                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             655913475                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             150097155                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           9418355                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       1558422                       # number of nop insts executed
system.cpu.iew.exec_refs                    212571042                       # number of memory reference insts executed
system.cpu.iew.exec_branches                138499517                       # Number of branches executed
system.cpu.iew.exec_stores                   62473887                       # Number of stores executed
system.cpu.iew.exec_rate                     1.620447                       # Inst execution rate
system.cpu.iew.wb_sent                      651035258                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     646062464                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 374747617                       # num instructions producing a value
system.cpu.iew.wb_consumers                 646369396                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.596109                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.579773                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       189524475                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           7191502                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    367094868                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.555370                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.229648                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    159372239     43.41%     43.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     98509322     26.83%     70.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     33822268      9.21%     79.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     18793314      5.12%     84.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     16194287      4.41%     88.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7448885      2.03%     91.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      7004810      1.91%     92.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3214010      0.88%     93.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     22735733      6.19%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    367094868                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            506581607                       # Number of instructions committed
system.cpu.commit.committedOps              570968167                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      182890032                       # Number of memory references committed
system.cpu.commit.loads                     126029555                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  121548301                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 470727693                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              22735733                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1104844639                       # The number of ROB reads
system.cpu.rob.rob_writes                  1548657613                       # The number of ROB writes
system.cpu.timesIdled                          329536                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        10126912                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   505237723                       # Number of Instructions Simulated
system.cpu.committedOps                     569624283                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             505237723                       # Number of Instructions Simulated
system.cpu.cpi                               0.801154                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.801154                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.248199                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.248199                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3058738251                       # number of integer regfile reads
system.cpu.int_regfile_writes               752038270                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.misc_regfile_reads               237846973                       # number of misc regfile reads
system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               735012008                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq         864661                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        864660                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1110883                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           79                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           79                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       348779                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       348779                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        33728                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3504101                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3537829                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1076352                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    147674432                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      148750784                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         148750784                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus         5824                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     2273084998                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      25918735                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1823048732                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.cpu.icache.tags.replacements             14973                       # number of replacements
system.cpu.icache.tags.tagsinuse          1095.994633                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           114499162                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             16828                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           6804.086166                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1095.994633                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.535154                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.535154                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1855                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           54                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           79                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          300                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1379                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.905762                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         229057415                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        229057415                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    114499162                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       114499162                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     114499162                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        114499162                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    114499162                       # number of overall hits
system.cpu.icache.overall_hits::total       114499162                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        21091                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         21091                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        21091                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          21091                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        21091                       # number of overall misses
system.cpu.icache.overall_misses::total         21091                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    555853234                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    555853234                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    555853234                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    555853234                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    555853234                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    555853234                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    114520253                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    114520253                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    114520253                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    114520253                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    114520253                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    114520253                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000184                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000184                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000184                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000184                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000184                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000184                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26354.996634                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 26354.996634                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 26354.996634                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 26354.996634                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 26354.996634                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 26354.996634                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          663                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    60.272727                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4181                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         4181                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         4181                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         4181                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         4181                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         4181                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        16910                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        16910                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        16910                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        16910                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        16910                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        16910                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    402050014                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    402050014                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    402050014                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    402050014                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    402050014                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    402050014                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000148                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000148                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000148                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23775.873093                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23775.873093                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23775.873093                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 23775.873093                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23775.873093                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23775.873093                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           115331                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        27082.895535                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1781400                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           146592                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.152096                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     102338963500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23017.339474                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   360.906574                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  3704.649487                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.702433                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011014                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.113057                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.826504                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31261                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2190                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7667                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21324                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.954010                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         19089931                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        19089931                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        13449                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       804311                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         817760                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1110883                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1110883                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           71                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           71                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       247485                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       247485                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        13449                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1051796                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1065245                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        13449                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1051796                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1065245                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3370                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        43440                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        46810                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            8                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            8                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       101294                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       101294                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3370                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       144734                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        148104                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3370                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       144734                       # number of overall misses
system.cpu.l2cache.overall_misses::total       148104                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    250298750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3365658750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3615957500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        23499                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        23499                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7297338249                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7297338249                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    250298750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10662996999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10913295749                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    250298750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10662996999                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10913295749                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        16819                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       847751                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       864570                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1110883                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1110883                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           79                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           79                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       348779                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       348779                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        16819                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1196530                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1213349                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        16819                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1196530                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1213349                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.200369                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.051241                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.054143                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.101266                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.101266                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.290425                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.290425                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.200369                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.120961                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.122062                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200369                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.120961                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.122062                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74272.626113                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77478.332182                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77247.543260                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  2937.375000                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  2937.375000                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72041.169753                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72041.169753                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74272.626113                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73673.062300                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73686.704944                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74272.626113                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73673.062300                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73686.704944                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        97591                       # number of writebacks
system.cpu.l2cache.writebacks::total            97591                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           26                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           26                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           26                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3365                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        43419                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        46784                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            8                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            8                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101294                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       101294                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3365                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       144713                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       148078                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3365                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       144713                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       148078                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    207676000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2821069500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3028745500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        80008                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        80008                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6013621251                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6013621251                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    207676000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8834690751                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9042366751                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    207676000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8834690751                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9042366751                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.200071                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.051217                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.054112                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.101266                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.101266                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.290425                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.290425                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200071                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.120944                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.122041                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200071                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.120944                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.122041                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61716.493314                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64973.156913                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64738.917151                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59367.990710                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59367.990710                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61716.493314                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61049.738109                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61064.889795                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61716.493314                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61049.738109                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61064.889795                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1192434                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4057.447359                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           190168921                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1196530                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            158.933684                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4256684250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4057.447359                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.990588                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.990588                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2348                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         1681                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         391443552                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        391443552                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    136203085                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       136203085                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     50988219                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       50988219                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488837                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488837                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     187191304                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        187191304                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    187191304                       # number of overall hits
system.cpu.dcache.overall_hits::total       187191304                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1703703                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1703703                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      3251087                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      3251087                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           39                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           39                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      4954790                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4954790                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      4954790                       # number of overall misses
system.cpu.dcache.overall_misses::total       4954790                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  29263316713                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  29263316713                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  70545580472                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  70545580472                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       635500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       635500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  99808897185                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  99808897185                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  99808897185                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  99808897185                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    137906788                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    137906788                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488876                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488876                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    192146094                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    192146094                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    192146094                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    192146094                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012354                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.012354                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.059940                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.059940                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000026                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000026                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.025787                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.025787                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.025787                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.025787                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17176.301687                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17176.301687                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21699.074947                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 21699.074947                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16294.871795                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16294.871795                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20143.920769                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20143.920769                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20143.920769                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20143.920769                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        17635                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        54424                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1686                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             666                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.459668                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    81.717718                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1110883                       # number of writebacks
system.cpu.dcache.writebacks::total           1110883                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       855409                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       855409                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2902772                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2902772                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           39                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           39                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3758181                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3758181                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3758181                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3758181                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       848294                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       848294                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348315                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       348315                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1196609                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1196609                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1196609                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1196609                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12295329526                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12295329526                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10170217738                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10170217738                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22465547264                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  22465547264                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22465547264                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  22465547264                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006151                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006151                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006422                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006422                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006228                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006228                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006228                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006228                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14494.184240                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14494.184240                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29198.334088                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29198.334088                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18774.342550                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18774.342550                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18774.342550                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18774.342550                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
