
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000025                       # Number of seconds simulated
sim_ticks                                    24975000                       # Number of ticks simulated
final_tick                                   24975000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  86020                       # Simulator instruction rate (inst/s)
host_op_rate                                    86001                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              369354314                       # Simulator tick rate (ticks/s)
host_mem_usage                                 263428                       # Number of bytes of host memory used
host_seconds                                     0.07                       # Real time elapsed on the host
sim_insts                                        5814                       # Number of instructions simulated
sim_ops                                          5814                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             20288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                29120                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        20288                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           20288                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                317                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   455                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            812332332                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            353633634                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1165965966                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       812332332                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          812332332                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           812332332                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           353633634                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1165965966                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                           455                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                         455                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                    29120                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                     29120                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                  28                       # Per bank write bursts
system.physmem.perBankRdBursts::1                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::2                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::3                   0                       # Per bank write bursts
system.physmem.perBankRdBursts::4                   8                       # Per bank write bursts
system.physmem.perBankRdBursts::5                   3                       # Per bank write bursts
system.physmem.perBankRdBursts::6                  12                       # Per bank write bursts
system.physmem.perBankRdBursts::7                  51                       # Per bank write bursts
system.physmem.perBankRdBursts::8                  59                       # Per bank write bursts
system.physmem.perBankRdBursts::9                  75                       # Per bank write bursts
system.physmem.perBankRdBursts::10                 36                       # Per bank write bursts
system.physmem.perBankRdBursts::11                 19                       # Per bank write bursts
system.physmem.perBankRdBursts::12                 52                       # Per bank write bursts
system.physmem.perBankRdBursts::13                 28                       # Per bank write bursts
system.physmem.perBankRdBursts::14                 77                       # Per bank write bursts
system.physmem.perBankRdBursts::15                  7                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                        24894000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                     455                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                       303                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       122                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        23                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples           75                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      267.093333                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     186.339521                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     256.296765                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127             18     24.00%     24.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255           29     38.67%     62.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383            9     12.00%     74.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511            8     10.67%     85.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639            4      5.33%     90.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767            1      1.33%     92.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895            1      1.33%     93.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151            5      6.67%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total             75                       # Bytes accessed per row activation
system.physmem.totQLat                        3086250                       # Total ticks spent queuing
system.physmem.totMemAccLat                  13542500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                      2275000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                     8181250                       # Total ticks spent accessing banks
system.physmem.avgQLat                        6782.97                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    17980.77                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29763.74                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                        1165.97                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                     1165.97                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           9.11                       # Data bus utilization in percentage
system.physmem.busUtilRead                       9.11                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.51                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                        344                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.60                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                        54712.09                       # Average gap between requests
system.physmem.pageHitRate                      75.60                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               0.04                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                   1165965966                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                 404                       # Transaction distribution
system.membus.trans_dist::ReadResp                404                       # Transaction distribution
system.membus.trans_dist::ReadExReq                51                       # Transaction distribution
system.membus.trans_dist::ReadExResp               51                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          910                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    910                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        29120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total               29120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                  29120                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy              552000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy            4258000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             17.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                    1156                       # Number of BP lookups
system.cpu.branchPred.condPredicted               861                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect               603                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups                  879                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                     339                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             38.566553                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                      86                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                 32                       # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                    8                       # Number of system calls
system.cpu.numCycles                            49951                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken          432                       # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken          724                       # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads         5088                       # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites         3396                       # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses         8484                       # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads            3                       # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites            1                       # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses            4                       # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards           1328                       # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens                       2229                       # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect          274                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect          320                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted            594                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted               321                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct     64.918033                       # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions             3133                       # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies                 3                       # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides                    1                       # Number of Divide Operations Executed
system.cpu.contextSwitches                          1                       # Number of context switches
system.cpu.threadCycles                          9487                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled                             463                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           44568                       # Number of cycles cpu's stages were not processed
system.cpu.runCycles                             5383                       # Number of cycles cpu stages are processed.
system.cpu.activity                         10.776561                       # Percentage of cycles cpu is active
system.cpu.comLoads                              1163                       # Number of Load instructions committed
system.cpu.comStores                              925                       # Number of Store instructions committed
system.cpu.comBranches                            915                       # Number of Branches instructions committed
system.cpu.comNops                                657                       # Number of Nop instructions committed
system.cpu.comNonSpec                              10                       # Number of Non-Speculative instructions committed
system.cpu.comInts                               2144                       # Number of Integer instructions committed
system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
system.cpu.committedInsts                        5814                       # Number of Instructions committed (Per-Thread)
system.cpu.committedOps                          5814                       # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total                  5814                       # Number of Instructions committed (Total)
system.cpu.cpi                               8.591503                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
system.cpu.cpi_total                         8.591503                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.116394                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
system.cpu.ipc_total                         0.116394                       # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles                    46303                       # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles                      3648                       # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization                7.303157                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles                    47138                       # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles                      2813                       # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization                5.631519                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles                    47184                       # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles                      2767                       # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization                5.539429                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles                    48713                       # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles                      1238                       # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization                2.478429                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles                    47063                       # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles                      2888                       # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization                5.781666                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements                13                       # number of replacements
system.cpu.icache.tags.tagsinuse           150.508435                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                 428                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               319                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              1.341693                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   150.508435                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.073490                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.073490                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          306                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.149414                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses              1875                       # Number of tag accesses
system.cpu.icache.tags.data_accesses             1875                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst          428                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total             428                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst           428                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total              428                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst          428                       # number of overall hits
system.cpu.icache.overall_hits::total             428                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          350                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           350                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          350                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            350                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          350                       # number of overall misses
system.cpu.icache.overall_misses::total           350                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     25364500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     25364500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     25364500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     25364500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     25364500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     25364500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst          778                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total          778                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst          778                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total          778                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst          778                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total          778                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.449871                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.449871                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.449871                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.449871                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.449871                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.449871                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        72470                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total        72470                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst        72470                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total        72470                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst        72470                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total        72470                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           31                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           31                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           31                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           31                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           31                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           31                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          319                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          319                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          319                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          319                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          319                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          319                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23031000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     23031000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23031000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     23031000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23031000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     23031000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.410026                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.410026                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.410026                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.410026                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.410026                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.410026                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72197.492163                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72197.492163                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72197.492163                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 72197.492163                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72197.492163                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 72197.492163                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput              1171091091                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq            406                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           406                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           51                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           51                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          638                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          276                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               914                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20416                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8832                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total          29248                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus             29248                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy         228500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        538000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        225500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          208.255183                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              404                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.004950                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   152.186433                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    56.068750                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004644                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.001711                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.006355                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          404                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          249                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012329                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             4111                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            4111                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          317                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          404                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           51                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           51                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          317                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           455                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          317                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
system.cpu.l2cache.overall_misses::total          455                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22685500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6903000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     29588500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3846500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      3846500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     22685500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     10749500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     33435000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     22685500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     10749500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     33435000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          319                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          406                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           51                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           51                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          319                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          457                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          319                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          457                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993730                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.995074                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993730                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.995624                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993730                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.995624                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71563.091483                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79344.827586                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73238.861386                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75421.568627                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75421.568627                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71563.091483                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77894.927536                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73483.516484                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71563.091483                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77894.927536                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73483.516484                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          317                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          404                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           51                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           51                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          317                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          455                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          317                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          455                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18705000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5824500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24529500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3204500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3204500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18705000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9029000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     27734000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18705000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9029000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     27734000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995074                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.995624                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.995624                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59006.309148                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66948.275862                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60716.584158                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59006.309148                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65427.536232                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60953.846154                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59006.309148                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65427.536232                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60953.846154                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse            90.278621                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                1638                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.869565                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data    90.278621                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.022041                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.022041                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.033691                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              4314                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             4314                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data         1066                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1066                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          572                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            572                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          1638                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             1638                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         1638                       # number of overall hits
system.cpu.dcache.overall_hits::total            1638                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           97                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            97                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          353                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          353                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          450                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            450                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          450                       # number of overall misses
system.cpu.dcache.overall_misses::total           450                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      7687000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      7687000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     21761250                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     21761250                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     29448250                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     29448250                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     29448250                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     29448250                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2088                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2088                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2088                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2088                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.083405                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.083405                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.381622                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.381622                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.215517                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.215517                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.215517                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.215517                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79247.422680                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 79247.422680                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61646.600567                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61646.600567                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65440.555556                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 65440.555556                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65440.555556                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 65440.555556                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          265                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                13                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.384615                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           10                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           10                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          302                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          302                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          312                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          312                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          312                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          312                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6996500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      6996500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3900500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      3900500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10897000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     10897000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10897000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     10897000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074807                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074807                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.066092                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.066092                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80419.540230                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80419.540230                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76480.392157                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76480.392157                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78963.768116                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78963.768116                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78963.768116                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78963.768116                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
