
---------- Begin Simulation Statistics ----------
sim_seconds                                  5.882581                       # Number of seconds simulated
sim_ticks                                5882580526000                       # Number of ticks simulated
final_tick                               5882580526000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 532297                       # Simulator instruction rate (inst/s)
host_op_rate                                   829367                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1040955661                       # Simulator tick rate (ticks/s)
host_mem_usage                                 302560                       # Number of bytes of host memory used
host_seconds                                  5651.13                       # Real time elapsed on the host
sim_insts                                  3008081022                       # Number of instructions simulated
sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             43200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         125326976                       # Number of bytes read from this memory
system.physmem.bytes_read::total            125370176                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        43200                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           43200                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     65178944                       # Number of bytes written to this memory
system.physmem.bytes_written::total          65178944                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                675                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1958234                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1958909                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1018421                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1018421                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                 7344                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             21304762                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                21312105                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst            7344                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total               7344                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          11079992                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               11079992                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          11079992                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst                7344                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            21304762                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               32392097                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     32392097                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq             1177614                       # Transaction distribution
system.membus.trans_dist::ReadResp            1177614                       # Transaction distribution
system.membus.trans_dist::Writeback           1018421                       # Transaction distribution
system.membus.trans_dist::ReadExReq            781295                       # Transaction distribution
system.membus.trans_dist::ReadExResp           781295                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4936239                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4936239                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4936239                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190549120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total    190549120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           190549120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              190549120                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy         11124698000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy        17630181000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.numCycles                      11765161052                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  3008081022                       # Number of instructions committed
system.cpu.committedOps                    4686862596                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses            4684368009                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                    33534539                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    182173300                       # number of instructions that are conditional controls
system.cpu.num_int_insts                   4684368009                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads         10688755601                       # number of times the integer registers were read
system.cpu.num_int_register_writes         3999841477                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads           1226718827                       # number of times the CC registers were read
system.cpu.num_cc_register_writes          1355930461                       # number of times the CC registers were written
system.cpu.num_mem_refs                    1677713084                       # number of memory refs
system.cpu.num_load_insts                  1239184746                       # Number of load instructions
system.cpu.num_store_insts                  438528338                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                11765161052                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.Branches                         248500691                       # Number of branches fetched
system.cpu.icache.tags.replacements                10                       # number of replacements
system.cpu.icache.tags.tagsinuse           555.705054                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs          4013232208                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               675                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          5945529.197037                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   555.705054                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.271340                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.271340                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          665                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          632                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.324707                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses        8026466441                       # Number of tag accesses
system.cpu.icache.tags.data_accesses       8026466441                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst   4013232208                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total      4013232208                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst    4013232208                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total       4013232208                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst   4013232208                       # number of overall hits
system.cpu.icache.overall_hits::total      4013232208                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          675                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           675                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          675                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            675                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          675                       # number of overall misses
system.cpu.icache.overall_misses::total           675                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     37156000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     37156000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     37156000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     37156000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     37156000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     37156000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst   4013232883                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total   4013232883                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst   4013232883                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total   4013232883                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst   4013232883                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total   4013232883                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55045.925926                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55045.925926                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          675                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          675                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          675                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          675                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          675                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     35806000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     35806000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     35806000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     35806000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     35806000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     35806000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1926197                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        31136.249379                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            8965026                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1955980                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.583393                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     340768635000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.641016                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.469873                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000783                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.479548                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.950203                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        29783                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          996                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          743                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27921                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908905                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        106336271                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       106336271                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.data      6045911                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        6045911                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      3697956                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3697956                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1108532                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1108532                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data      7154443                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7154443                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data      7154443                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7154443                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          675                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1176939                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1177614                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       781295                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       781295                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          675                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1958234                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1958909                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          675                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1958234                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1958909                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     35131000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  61200881000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  61236012000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  40627414000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  40627414000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     35131000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 101828295000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 101863426000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     35131000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 101828295000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 101863426000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          675                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      7222850                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7223525                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      3697956                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3697956                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889827                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1889827                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          675                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9112677                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9113352                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          675                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9112677                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9113352                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.162947                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.163025                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413421                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.413421                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.214891                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.214949                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.214891                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.214949                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52045.925926                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.045032                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.071331                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.094715                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.094715                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52045.925926                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.064854                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000.080657                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52045.925926                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.064854                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000.080657                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1018421                       # number of writebacks
system.cpu.l2cache.writebacks::total          1018421                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          675                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1176939                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1177614                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       781295                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       781295                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          675                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1958234                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1958909                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1958234                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1958909                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     27031000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  47077613000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  47104644000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31251874000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31251874000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     27031000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  78329487000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  78356518000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     27031000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  78329487000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  78356518000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.162947                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163025                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413421                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413421                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214891                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.214949                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214891                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.214949                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           9108581                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4084.587030                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs          1668600407                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9112677                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            183.107599                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle       58853922000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4084.587030                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997214                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997214                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          926                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2744                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3          320                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4            2                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        3364538845                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       3364538845                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data   1231961896                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total      1231961896                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    436638511                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      436638511                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data    1668600407                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total       1668600407                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data   1668600407                       # number of overall hits
system.cpu.dcache.overall_hits::total      1668600407                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      7222850                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       7222850                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1889827                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1889827                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      9112677                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9112677                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9112677                       # number of overall misses
system.cpu.dcache.overall_misses::total       9112677                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 143328541000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  57382215000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  57382215000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 200710756000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 200710756000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 200710756000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 200710756000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data   1239184746                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total   1239184746                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    438528338                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    438528338                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data   1677713084                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total   1677713084                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data   1677713084                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total   1677713084                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.005829                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.005829                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.004309                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.004309                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.005432                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.005432                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.005432                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.005432                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22025.443895                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22025.443895                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3697956                       # number of writebacks
system.cpu.dcache.writebacks::total           3697956                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222850                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7222850                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889827                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1889827                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9112677                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9112677                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9112677                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9112677                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53602561000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  53602561000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 182485402000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 182485402000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.005829                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.005829                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.004309                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.004309                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005432                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.005432                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005432                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.005432                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput               139381638                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        7223525                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       7223525                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      3697956                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1889827                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1889827                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1350                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21923310                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          21924660                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        43200                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    819880512                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      819923712                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         819923712                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy    10103610000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       1012500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13669015500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
